1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * sama5d2.dtsi - Device Tree Include file for SAMA5D2 family SoC 4 * 5 * Copyright (C) 2015 Atmel, 6 * 2015 Ludovic Desroches <ludovic.desroches@atmel.com> 7 */ 8 9#include <dt-bindings/dma/at91.h> 10#include <dt-bindings/interrupt-controller/irq.h> 11#include <dt-bindings/clock/at91.h> 12#include <dt-bindings/iio/adc/at91-sama5d2_adc.h> 13 14/ { 15 #address-cells = <1>; 16 #size-cells = <1>; 17 model = "Atmel SAMA5D2 family SoC"; 18 compatible = "atmel,sama5d2"; 19 interrupt-parent = <&aic>; 20 21 aliases { 22 serial0 = &uart1; 23 serial1 = &uart3; 24 }; 25 26 cpus { 27 #address-cells = <1>; 28 #size-cells = <0>; 29 30 cpu@0 { 31 device_type = "cpu"; 32 compatible = "arm,cortex-a5"; 33 reg = <0>; 34 next-level-cache = <&L2>; 35 clocks = <&pmc PMC_TYPE_CORE PMC_MCK_PRES>; 36 clock-names = "cpu"; 37 }; 38 }; 39 40 pmu { 41 compatible = "arm,cortex-a5-pmu"; 42 interrupts = <2 IRQ_TYPE_LEVEL_HIGH 0>; 43 }; 44 45 etb@740000 { 46 compatible = "arm,coresight-etb10", "arm,primecell"; 47 reg = <0x740000 0x1000>; 48 49 clocks = <&pmc PMC_TYPE_CORE PMC_MCK>; 50 clock-names = "apb_pclk"; 51 52 in-ports { 53 port { 54 etb_in: endpoint { 55 remote-endpoint = <&etm_out>; 56 }; 57 }; 58 }; 59 }; 60 61 etm@73c000 { 62 compatible = "arm,coresight-etm3x", "arm,primecell"; 63 reg = <0x73c000 0x1000>; 64 65 clocks = <&pmc PMC_TYPE_CORE PMC_MCK>; 66 clock-names = "apb_pclk"; 67 68 out-ports { 69 port { 70 etm_out: endpoint { 71 remote-endpoint = <&etb_in>; 72 }; 73 }; 74 }; 75 }; 76 77 memory@20000000 { 78 device_type = "memory"; 79 reg = <0x20000000 0x20000000>; 80 }; 81 82 clocks { 83 slow_xtal: slow_xtal { 84 compatible = "fixed-clock"; 85 #clock-cells = <0>; 86 clock-frequency = <0>; 87 }; 88 89 main_xtal: main_xtal { 90 compatible = "fixed-clock"; 91 #clock-cells = <0>; 92 clock-frequency = <0>; 93 }; 94 }; 95 96 ns_sram: sram@200000 { 97 compatible = "atmel,sama5d2-sram", "mmio-sram"; 98 reg = <0x00200000 0x20000>; 99 #address-cells = <1>; 100 #size-cells = <1>; 101 ranges = <0 0x00200000 0x20000>; 102 status = "disabled"; 103 secure-status = "okay"; 104 }; 105 106 ahb { 107 compatible = "simple-bus"; 108 #address-cells = <1>; 109 #size-cells = <1>; 110 ranges; 111 112 nfc_sram: sram@100000 { 113 compatible = "mmio-sram"; 114 no-memory-wc; 115 reg = <0x00100000 0x2400>; 116 #address-cells = <1>; 117 #size-cells = <1>; 118 ranges = <0 0x00100000 0x2400>; 119 120 }; 121 122 usb0: gadget@300000 { 123 compatible = "atmel,sama5d3-udc"; 124 reg = <0x00300000 0x100000 125 0xfc02c000 0x400>; 126 interrupts = <42 IRQ_TYPE_LEVEL_HIGH 2>; 127 clocks = <&pmc PMC_TYPE_PERIPHERAL 42>, <&pmc PMC_TYPE_CORE PMC_UTMI>; 128 clock-names = "pclk", "hclk"; 129 status = "disabled"; 130 }; 131 132 usb1: ohci@400000 { 133 compatible = "atmel,at91rm9200-ohci", "usb-ohci"; 134 reg = <0x00400000 0x100000>; 135 interrupts = <41 IRQ_TYPE_LEVEL_HIGH 2>; 136 clocks = <&pmc PMC_TYPE_PERIPHERAL 41>, <&pmc PMC_TYPE_PERIPHERAL 41>, <&pmc PMC_TYPE_SYSTEM 6>; 137 clock-names = "ohci_clk", "hclk", "uhpck"; 138 status = "disabled"; 139 }; 140 141 usb2: ehci@500000 { 142 compatible = "atmel,at91sam9g45-ehci", "usb-ehci"; 143 reg = <0x00500000 0x100000>; 144 interrupts = <41 IRQ_TYPE_LEVEL_HIGH 2>; 145 clocks = <&pmc PMC_TYPE_CORE PMC_UTMI>, <&pmc PMC_TYPE_PERIPHERAL 41>; 146 clock-names = "usb_clk", "ehci_clk"; 147 status = "disabled"; 148 }; 149 150 L2: cache-controller@a00000 { 151 compatible = "arm,pl310-cache"; 152 reg = <0x00a00000 0x1000>; 153 interrupts = <63 IRQ_TYPE_LEVEL_HIGH 4>; 154 cache-unified; 155 cache-level = <2>; 156 }; 157 158 ebi: ebi@10000000 { 159 compatible = "atmel,sama5d3-ebi"; 160 #address-cells = <2>; 161 #size-cells = <1>; 162 atmel,smc = <&hsmc>; 163 reg = <0x10000000 0x10000000 164 0x60000000 0x30000000>; 165 ranges = <0x0 0x0 0x10000000 0x10000000 166 0x1 0x0 0x60000000 0x10000000 167 0x2 0x0 0x70000000 0x10000000 168 0x3 0x0 0x80000000 0x10000000>; 169 clocks = <&pmc PMC_TYPE_CORE PMC_MCK2>; 170 status = "disabled"; 171 172 nand_controller: nand-controller { 173 compatible = "atmel,sama5d3-nand-controller"; 174 atmel,nfc-sram = <&nfc_sram>; 175 atmel,nfc-io = <&nfc_io>; 176 ecc-engine = <&pmecc>; 177 #address-cells = <2>; 178 #size-cells = <1>; 179 ranges; 180 status = "disabled"; 181 }; 182 }; 183 184 sdmmc0: sdio-host@a0000000 { 185 compatible = "atmel,sama5d2-sdhci"; 186 reg = <0xa0000000 0x300>; 187 interrupts = <31 IRQ_TYPE_LEVEL_HIGH 0>; 188 clocks = <&pmc PMC_TYPE_PERIPHERAL 31>, <&pmc PMC_TYPE_GCK 31>, <&pmc PMC_TYPE_CORE PMC_MAIN>; 189 clock-names = "hclock", "multclk", "baseclk"; 190 assigned-clocks = <&pmc PMC_TYPE_GCK 31>; 191 assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_UTMI>; 192 assigned-clock-rates = <480000000>; 193 status = "disabled"; 194 }; 195 196 sdmmc1: sdio-host@b0000000 { 197 compatible = "atmel,sama5d2-sdhci"; 198 reg = <0xb0000000 0x300>; 199 interrupts = <32 IRQ_TYPE_LEVEL_HIGH 0>; 200 clocks = <&pmc PMC_TYPE_PERIPHERAL 32>, <&pmc PMC_TYPE_GCK 32>, <&pmc PMC_TYPE_CORE PMC_MAIN>; 201 clock-names = "hclock", "multclk", "baseclk"; 202 assigned-clocks = <&pmc PMC_TYPE_GCK 32>; 203 assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_UTMI>; 204 assigned-clock-rates = <480000000>; 205 status = "disabled"; 206 }; 207 208 nfc_io: nfc-io@c0000000 { 209 compatible = "atmel,sama5d3-nfc-io", "syscon"; 210 reg = <0xc0000000 0x8000000>; 211 }; 212 213 apb { 214 compatible = "simple-bus"; 215 #address-cells = <1>; 216 #size-cells = <1>; 217 ranges; 218 219 hlcdc: hlcdc@f0000000 { 220 compatible = "atmel,sama5d2-hlcdc"; 221 reg = <0xf0000000 0x2000>; 222 interrupts = <45 IRQ_TYPE_LEVEL_HIGH 0>; 223 clocks = <&pmc PMC_TYPE_PERIPHERAL 45>, <&pmc PMC_TYPE_SYSTEM 3>, <&clk32k>; 224 clock-names = "periph_clk","sys_clk", "slow_clk"; 225 status = "disabled"; 226 227 hlcdc-display-controller { 228 compatible = "atmel,hlcdc-display-controller"; 229 #address-cells = <1>; 230 #size-cells = <0>; 231 232 port@0 { 233 #address-cells = <1>; 234 #size-cells = <0>; 235 reg = <0>; 236 }; 237 }; 238 239 hlcdc_pwm: hlcdc-pwm { 240 compatible = "atmel,hlcdc-pwm"; 241 #pwm-cells = <3>; 242 }; 243 }; 244 245 isc: isc@f0008000 { 246 compatible = "atmel,sama5d2-isc"; 247 reg = <0xf0008000 0x4000>; 248 interrupts = <46 IRQ_TYPE_LEVEL_HIGH 5>; 249 clocks = <&pmc PMC_TYPE_PERIPHERAL 46>, <&pmc PMC_TYPE_SYSTEM 18>, <&pmc PMC_TYPE_GCK 46>; 250 clock-names = "hclock", "iscck", "gck"; 251 #clock-cells = <0>; 252 clock-output-names = "isc-mck"; 253 status = "disabled"; 254 }; 255 256 ramc0: ramc@f000c000 { 257 compatible = "atmel,sama5d3-ddramc"; 258 reg = <0xf000c000 0x200>; 259 clocks = <&pmc PMC_TYPE_SYSTEM 2>, <&pmc PMC_TYPE_PERIPHERAL 13>; 260 clock-names = "ddrck", "mpddr"; 261 }; 262 263 dma0: dma-controller@f0010000 { 264 compatible = "atmel,sama5d4-dma"; 265 reg = <0xf0010000 0x1000>; 266 interrupts = <6 IRQ_TYPE_LEVEL_HIGH 0>; 267 #dma-cells = <1>; 268 clocks = <&pmc PMC_TYPE_PERIPHERAL 6>; 269 clock-names = "dma_clk"; 270 }; 271 272 /* Place dma1 here despite its address */ 273 dma1: dma-controller@f0004000 { 274 compatible = "atmel,sama5d4-dma"; 275 reg = <0xf0004000 0x1000>; 276 interrupts = <7 IRQ_TYPE_LEVEL_HIGH 0>; 277 #dma-cells = <1>; 278 clocks = <&pmc PMC_TYPE_PERIPHERAL 7>; 279 clock-names = "dma_clk"; 280 }; 281 282 pmc: pmc@f0014000 { 283 compatible = "atmel,sama5d2-pmc", "syscon"; 284 reg = <0xf0014000 0x160>; 285 interrupts = <74 IRQ_TYPE_LEVEL_HIGH 7>; 286 #clock-cells = <2>; 287 clocks = <&clk32k>, <&main_xtal>; 288 clock-names = "slow_clk", "main_xtal"; 289 }; 290 291 qspi0: spi@f0020000 { 292 compatible = "atmel,sama5d2-qspi"; 293 reg = <0xf0020000 0x100>, <0xd0000000 0x08000000>; 294 reg-names = "qspi_base", "qspi_mmap"; 295 interrupts = <52 IRQ_TYPE_LEVEL_HIGH 7>; 296 clocks = <&pmc PMC_TYPE_PERIPHERAL 52>; 297 #address-cells = <1>; 298 #size-cells = <0>; 299 status = "disabled"; 300 }; 301 302 qspi1: spi@f0024000 { 303 compatible = "atmel,sama5d2-qspi"; 304 reg = <0xf0024000 0x100>, <0xd8000000 0x08000000>; 305 reg-names = "qspi_base", "qspi_mmap"; 306 interrupts = <53 IRQ_TYPE_LEVEL_HIGH 7>; 307 clocks = <&pmc PMC_TYPE_PERIPHERAL 53>; 308 #address-cells = <1>; 309 #size-cells = <0>; 310 status = "disabled"; 311 }; 312 313 sha@f0028000 { 314 compatible = "atmel,at91sam9g46-sha"; 315 reg = <0xf0028000 0x100>; 316 interrupts = <12 IRQ_TYPE_LEVEL_HIGH 0>; 317 dmas = <&dma0 318 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 319 AT91_XDMAC_DT_PERID(30))>; 320 dma-names = "tx"; 321 clocks = <&pmc PMC_TYPE_PERIPHERAL 12>; 322 clock-names = "sha_clk"; 323 status = "okay"; 324 }; 325 326 aes@f002c000 { 327 compatible = "atmel,at91sam9g46-aes"; 328 reg = <0xf002c000 0x100>; 329 interrupts = <9 IRQ_TYPE_LEVEL_HIGH 0>; 330 dmas = <&dma0 331 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 332 AT91_XDMAC_DT_PERID(26))>, 333 <&dma0 334 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 335 AT91_XDMAC_DT_PERID(27))>; 336 dma-names = "tx", "rx"; 337 clocks = <&pmc PMC_TYPE_PERIPHERAL 9>; 338 clock-names = "aes_clk"; 339 status = "okay"; 340 }; 341 342 spi0: spi@f8000000 { 343 compatible = "atmel,at91rm9200-spi"; 344 reg = <0xf8000000 0x100>; 345 interrupts = <33 IRQ_TYPE_LEVEL_HIGH 7>; 346 dmas = <&dma0 347 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 348 AT91_XDMAC_DT_PERID(6))>, 349 <&dma0 350 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 351 AT91_XDMAC_DT_PERID(7))>; 352 dma-names = "tx", "rx"; 353 clocks = <&pmc PMC_TYPE_PERIPHERAL 33>; 354 clock-names = "spi_clk"; 355 atmel,fifo-size = <16>; 356 #address-cells = <1>; 357 #size-cells = <0>; 358 status = "disabled"; 359 }; 360 361 ssc0: ssc@f8004000 { 362 compatible = "atmel,at91sam9g45-ssc"; 363 reg = <0xf8004000 0x4000>; 364 interrupts = <43 IRQ_TYPE_LEVEL_HIGH 4>; 365 dmas = <&dma0 366 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 367 AT91_XDMAC_DT_PERID(21))>, 368 <&dma0 369 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 370 AT91_XDMAC_DT_PERID(22))>; 371 dma-names = "tx", "rx"; 372 clocks = <&pmc PMC_TYPE_PERIPHERAL 43>; 373 clock-names = "pclk"; 374 status = "disabled"; 375 }; 376 377 macb0: ethernet@f8008000 { 378 compatible = "atmel,sama5d2-gem"; 379 reg = <0xf8008000 0x1000>; 380 interrupts = <5 IRQ_TYPE_LEVEL_HIGH 3 /* Queue 0 */ 381 66 IRQ_TYPE_LEVEL_HIGH 3 /* Queue 1 */ 382 67 IRQ_TYPE_LEVEL_HIGH 3>; /* Queue 2 */ 383 #address-cells = <1>; 384 #size-cells = <0>; 385 clocks = <&pmc PMC_TYPE_PERIPHERAL 5>, <&pmc PMC_TYPE_PERIPHERAL 5>; 386 clock-names = "hclk", "pclk"; 387 status = "disabled"; 388 }; 389 390 tcb0: timer@f800c000 { 391 compatible = "atmel,sama5d2-tcb", "simple-mfd", "syscon"; 392 #address-cells = <1>; 393 #size-cells = <0>; 394 reg = <0xf800c000 0x100>; 395 interrupts = <35 IRQ_TYPE_LEVEL_HIGH 0>; 396 clocks = <&pmc PMC_TYPE_PERIPHERAL 35>, <&pmc PMC_TYPE_GCK 35>, <&clk32k>; 397 clock-names = "t0_clk", "gclk", "slow_clk"; 398 }; 399 400 tcb1: timer@f8010000 { 401 compatible = "atmel,sama5d2-tcb", "simple-mfd", "syscon"; 402 #address-cells = <1>; 403 #size-cells = <0>; 404 reg = <0xf8010000 0x100>; 405 interrupts = <36 IRQ_TYPE_LEVEL_HIGH 0>; 406 clocks = <&pmc PMC_TYPE_PERIPHERAL 36>, <&pmc PMC_TYPE_GCK 36>, <&clk32k>; 407 clock-names = "t0_clk", "gclk", "slow_clk"; 408 status = "disabled"; 409 secure-status = "okay"; 410 }; 411 412 hsmc: hsmc@f8014000 { 413 compatible = "atmel,sama5d2-smc", "syscon", "simple-mfd"; 414 reg = <0xf8014000 0x1000>; 415 interrupts = <17 IRQ_TYPE_LEVEL_HIGH 6>; 416 clocks = <&pmc PMC_TYPE_PERIPHERAL 17>; 417 #address-cells = <1>; 418 #size-cells = <1>; 419 ranges; 420 421 pmecc: ecc-engine@f8014070 { 422 compatible = "atmel,sama5d2-pmecc"; 423 reg = <0xf8014070 0x490>, 424 <0xf8014500 0x100>; 425 }; 426 }; 427 428 pdmic: pdmic@f8018000 { 429 compatible = "atmel,sama5d2-pdmic"; 430 reg = <0xf8018000 0x124>; 431 interrupts = <48 IRQ_TYPE_LEVEL_HIGH 7>; 432 dmas = <&dma0 433 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) 434 | AT91_XDMAC_DT_PERID(50))>; 435 dma-names = "rx"; 436 clocks = <&pmc PMC_TYPE_PERIPHERAL 48>, <&pmc PMC_TYPE_GCK 48>; 437 clock-names = "pclk", "gclk"; 438 status = "disabled"; 439 }; 440 441 uart0: serial@f801c000 { 442 compatible = "atmel,at91sam9260-usart"; 443 reg = <0xf801c000 0x100>; 444 interrupts = <24 IRQ_TYPE_LEVEL_HIGH 7>; 445 dmas = <&dma0 446 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 447 AT91_XDMAC_DT_PERID(35))>, 448 <&dma0 449 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 450 AT91_XDMAC_DT_PERID(36))>; 451 dma-names = "tx", "rx"; 452 clocks = <&pmc PMC_TYPE_PERIPHERAL 24>; 453 clock-names = "usart"; 454 status = "disabled"; 455 }; 456 457 uart1: serial@f8020000 { 458 compatible = "atmel,at91sam9260-usart"; 459 reg = <0xf8020000 0x100>; 460 interrupts = <25 IRQ_TYPE_LEVEL_HIGH 7>; 461 dmas = <&dma0 462 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 463 AT91_XDMAC_DT_PERID(37))>, 464 <&dma0 465 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 466 AT91_XDMAC_DT_PERID(38))>; 467 dma-names = "tx", "rx"; 468 clocks = <&pmc PMC_TYPE_PERIPHERAL 25>; 469 clock-names = "usart"; 470 status = "disabled"; 471 }; 472 473 uart2: serial@f8024000 { 474 compatible = "atmel,at91sam9260-usart"; 475 reg = <0xf8024000 0x100>; 476 interrupts = <26 IRQ_TYPE_LEVEL_HIGH 7>; 477 dmas = <&dma0 478 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 479 AT91_XDMAC_DT_PERID(39))>, 480 <&dma0 481 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 482 AT91_XDMAC_DT_PERID(40))>; 483 dma-names = "tx", "rx"; 484 clocks = <&pmc PMC_TYPE_PERIPHERAL 26>; 485 clock-names = "usart"; 486 status = "disabled"; 487 }; 488 489 i2c0: i2c@f8028000 { 490 compatible = "atmel,sama5d2-i2c"; 491 reg = <0xf8028000 0x100>; 492 interrupts = <29 IRQ_TYPE_LEVEL_HIGH 7>; 493 dmas = <&dma0 494 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 495 AT91_XDMAC_DT_PERID(0))>, 496 <&dma0 497 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 498 AT91_XDMAC_DT_PERID(1))>; 499 dma-names = "tx", "rx"; 500 #address-cells = <1>; 501 #size-cells = <0>; 502 clocks = <&pmc PMC_TYPE_PERIPHERAL 29>; 503 atmel,fifo-size = <16>; 504 status = "disabled"; 505 }; 506 507 pwm0: pwm@f802c000 { 508 compatible = "atmel,sama5d2-pwm"; 509 reg = <0xf802c000 0x4000>; 510 interrupts = <38 IRQ_TYPE_LEVEL_HIGH 7>; 511 #pwm-cells = <3>; 512 clocks = <&pmc PMC_TYPE_PERIPHERAL 38>; 513 status = "disabled"; 514 }; 515 516 sfr: sfr@f8030000 { 517 compatible = "atmel,sama5d2-sfr", "syscon"; 518 reg = <0xf8030000 0x98>; 519 status = "disabled"; 520 secure-status = "okay"; 521 }; 522 523 flx0: flexcom@f8034000 { 524 compatible = "atmel,sama5d2-flexcom"; 525 reg = <0xf8034000 0x200>; 526 clocks = <&pmc PMC_TYPE_PERIPHERAL 19>; 527 #address-cells = <1>; 528 #size-cells = <1>; 529 ranges = <0x0 0xf8034000 0x800>; 530 status = "disabled"; 531 532 uart5: serial@200 { 533 compatible = "atmel,at91sam9260-usart"; 534 reg = <0x200 0x200>; 535 interrupts = <19 IRQ_TYPE_LEVEL_HIGH 7>; 536 clocks = <&pmc PMC_TYPE_PERIPHERAL 19>; 537 clock-names = "usart"; 538 dmas = <&dma0 539 (AT91_XDMAC_DT_MEM_IF(0) | 540 AT91_XDMAC_DT_PER_IF(1) | 541 AT91_XDMAC_DT_PERID(11))>, 542 <&dma0 543 (AT91_XDMAC_DT_MEM_IF(0) | 544 AT91_XDMAC_DT_PER_IF(1) | 545 AT91_XDMAC_DT_PERID(12))>; 546 dma-names = "tx", "rx"; 547 atmel,fifo-size = <32>; 548 status = "disabled"; 549 }; 550 551 spi2: spi@400 { 552 compatible = "atmel,at91rm9200-spi"; 553 reg = <0x400 0x200>; 554 interrupts = <19 IRQ_TYPE_LEVEL_HIGH 7>; 555 #address-cells = <1>; 556 #size-cells = <0>; 557 clocks = <&pmc PMC_TYPE_PERIPHERAL 19>; 558 clock-names = "spi_clk"; 559 dmas = <&dma0 560 (AT91_XDMAC_DT_MEM_IF(0) | 561 AT91_XDMAC_DT_PER_IF(1) | 562 AT91_XDMAC_DT_PERID(11))>, 563 <&dma0 564 (AT91_XDMAC_DT_MEM_IF(0) | 565 AT91_XDMAC_DT_PER_IF(1) | 566 AT91_XDMAC_DT_PERID(12))>; 567 dma-names = "tx", "rx"; 568 atmel,fifo-size = <16>; 569 status = "disabled"; 570 }; 571 572 i2c2: i2c@600 { 573 compatible = "atmel,sama5d2-i2c"; 574 reg = <0x600 0x200>; 575 interrupts = <19 IRQ_TYPE_LEVEL_HIGH 7>; 576 #address-cells = <1>; 577 #size-cells = <0>; 578 clocks = <&pmc PMC_TYPE_PERIPHERAL 19>; 579 dmas = <&dma0 580 (AT91_XDMAC_DT_MEM_IF(0) | 581 AT91_XDMAC_DT_PER_IF(1) | 582 AT91_XDMAC_DT_PERID(11))>, 583 <&dma0 584 (AT91_XDMAC_DT_MEM_IF(0) | 585 AT91_XDMAC_DT_PER_IF(1) | 586 AT91_XDMAC_DT_PERID(12))>; 587 dma-names = "tx", "rx"; 588 atmel,fifo-size = <16>; 589 status = "disabled"; 590 }; 591 }; 592 593 flx1: flexcom@f8038000 { 594 compatible = "atmel,sama5d2-flexcom"; 595 reg = <0xf8038000 0x200>; 596 clocks = <&pmc PMC_TYPE_PERIPHERAL 20>; 597 #address-cells = <1>; 598 #size-cells = <1>; 599 ranges = <0x0 0xf8038000 0x800>; 600 status = "disabled"; 601 602 uart6: serial@200 { 603 compatible = "atmel,at91sam9260-usart"; 604 reg = <0x200 0x200>; 605 interrupts = <20 IRQ_TYPE_LEVEL_HIGH 7>; 606 clocks = <&pmc PMC_TYPE_PERIPHERAL 20>; 607 clock-names = "usart"; 608 dmas = <&dma0 609 (AT91_XDMAC_DT_MEM_IF(0) | 610 AT91_XDMAC_DT_PER_IF(1) | 611 AT91_XDMAC_DT_PERID(13))>, 612 <&dma0 613 (AT91_XDMAC_DT_MEM_IF(0) | 614 AT91_XDMAC_DT_PER_IF(1) | 615 AT91_XDMAC_DT_PERID(14))>; 616 dma-names = "tx", "rx"; 617 atmel,fifo-size = <32>; 618 status = "disabled"; 619 }; 620 621 spi3: spi@400 { 622 compatible = "atmel,at91rm9200-spi"; 623 reg = <0x400 0x200>; 624 interrupts = <20 IRQ_TYPE_LEVEL_HIGH 7>; 625 #address-cells = <1>; 626 #size-cells = <0>; 627 clocks = <&pmc PMC_TYPE_PERIPHERAL 20>; 628 clock-names = "spi_clk"; 629 dmas = <&dma0 630 (AT91_XDMAC_DT_MEM_IF(0) | 631 AT91_XDMAC_DT_PER_IF(1) | 632 AT91_XDMAC_DT_PERID(13))>, 633 <&dma0 634 (AT91_XDMAC_DT_MEM_IF(0) | 635 AT91_XDMAC_DT_PER_IF(1) | 636 AT91_XDMAC_DT_PERID(14))>; 637 dma-names = "tx", "rx"; 638 atmel,fifo-size = <16>; 639 status = "disabled"; 640 }; 641 642 i2c3: i2c@600 { 643 compatible = "atmel,sama5d2-i2c"; 644 reg = <0x600 0x200>; 645 interrupts = <20 IRQ_TYPE_LEVEL_HIGH 7>; 646 #address-cells = <1>; 647 #size-cells = <0>; 648 clocks = <&pmc PMC_TYPE_PERIPHERAL 20>; 649 dmas = <&dma0 650 (AT91_XDMAC_DT_MEM_IF(0) | 651 AT91_XDMAC_DT_PER_IF(1) | 652 AT91_XDMAC_DT_PERID(13))>, 653 <&dma0 654 (AT91_XDMAC_DT_MEM_IF(0) | 655 AT91_XDMAC_DT_PER_IF(1) | 656 AT91_XDMAC_DT_PERID(14))>; 657 dma-names = "tx", "rx"; 658 atmel,fifo-size = <16>; 659 status = "disabled"; 660 }; 661 }; 662 663 securam: sram@f8044000 { 664 compatible = "atmel,sama5d2-securam", "mmio-sram"; 665 reg = <0xf8044000 0x1420>; 666 clocks = <&pmc PMC_TYPE_PERIPHERAL 51>; 667 #address-cells = <1>; 668 #size-cells = <1>; 669 no-memory-wc; 670 ranges = <0 0xf8044000 0x1420>; 671 status = "disabled"; 672 secure-status = "okay"; 673 }; 674 675 reset_controller: rstc@f8048000 { 676 compatible = "atmel,sama5d3-rstc"; 677 reg = <0xf8048000 0x10>; 678 clocks = <&clk32k>; 679 }; 680 681 shutdown_controller: shdwc@f8048010 { 682 compatible = "atmel,sama5d2-shdwc"; 683 reg = <0xf8048010 0x10>; 684 clocks = <&clk32k>; 685 #address-cells = <1>; 686 #size-cells = <0>; 687 atmel,wakeup-rtc-timer; 688 }; 689 690 pit: timer@f8048030 { 691 compatible = "atmel,at91sam9260-pit"; 692 reg = <0xf8048030 0x10>; 693 interrupts = <3 IRQ_TYPE_LEVEL_HIGH 5>; 694 clocks = <&pmc PMC_TYPE_CORE PMC_MCK2>; 695 }; 696 697 watchdog: watchdog@f8048040 { 698 compatible = "atmel,sama5d4-wdt"; 699 reg = <0xf8048040 0x10>; 700 interrupts = <4 IRQ_TYPE_LEVEL_HIGH 7>; 701 clocks = <&clk32k>; 702 status = "disabled"; 703 secure-status = "okay"; 704 }; 705 706 clk32k: sckc@f8048050 { 707 compatible = "atmel,sama5d4-sckc"; 708 reg = <0xf8048050 0x4>; 709 710 clocks = <&slow_xtal>; 711 #clock-cells = <0>; 712 }; 713 714 rtc: rtc@f80480b0 { 715 compatible = "atmel,sama5d2-rtc"; 716 reg = <0xf80480b0 0x30>; 717 interrupts = <74 IRQ_TYPE_LEVEL_HIGH 7>; 718 clocks = <&clk32k>; 719 status = "disabled"; 720 secure-status = "okay"; 721 }; 722 723 i2s0: i2s@f8050000 { 724 compatible = "atmel,sama5d2-i2s"; 725 reg = <0xf8050000 0x100>; 726 interrupts = <54 IRQ_TYPE_LEVEL_HIGH 7>; 727 dmas = <&dma0 728 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 729 AT91_XDMAC_DT_PERID(31))>, 730 <&dma0 731 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 732 AT91_XDMAC_DT_PERID(32))>; 733 dma-names = "tx", "rx"; 734 clocks = <&pmc PMC_TYPE_PERIPHERAL 54>, <&pmc PMC_TYPE_GCK 54>; 735 clock-names = "pclk", "gclk"; 736 assigned-clocks = <&pmc PMC_TYPE_CORE PMC_I2S0_MUX>; 737 assigned-clock-parents = <&pmc PMC_TYPE_GCK 54>; 738 status = "disabled"; 739 }; 740 741 can0: can@f8054000 { 742 compatible = "bosch,m_can"; 743 reg = <0xf8054000 0x4000>, <0x210000 0x1c00>; 744 reg-names = "m_can", "message_ram"; 745 interrupts = <56 IRQ_TYPE_LEVEL_HIGH 7>, 746 <64 IRQ_TYPE_LEVEL_HIGH 7>; 747 interrupt-names = "int0", "int1"; 748 clocks = <&pmc PMC_TYPE_PERIPHERAL 56>, <&pmc PMC_TYPE_GCK 56>; 749 clock-names = "hclk", "cclk"; 750 assigned-clocks = <&pmc PMC_TYPE_GCK 56>; 751 assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_UTMI>; 752 assigned-clock-rates = <40000000>; 753 bosch,mram-cfg = <0x0 0 0 64 0 0 32 32>; 754 status = "disabled"; 755 }; 756 757 spi1: spi@fc000000 { 758 compatible = "atmel,at91rm9200-spi"; 759 reg = <0xfc000000 0x100>; 760 interrupts = <34 IRQ_TYPE_LEVEL_HIGH 7>; 761 dmas = <&dma0 762 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 763 AT91_XDMAC_DT_PERID(8))>, 764 <&dma0 765 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 766 AT91_XDMAC_DT_PERID(9))>; 767 dma-names = "tx", "rx"; 768 clocks = <&pmc PMC_TYPE_PERIPHERAL 34>; 769 clock-names = "spi_clk"; 770 atmel,fifo-size = <16>; 771 #address-cells = <1>; 772 #size-cells = <0>; 773 status = "disabled"; 774 }; 775 776 uart3: serial@fc008000 { 777 compatible = "atmel,at91sam9260-usart"; 778 reg = <0xfc008000 0x100>; 779 interrupts = <27 IRQ_TYPE_LEVEL_HIGH 7>; 780 dmas = <&dma1 781 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 782 AT91_XDMAC_DT_PERID(41))>, 783 <&dma1 784 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 785 AT91_XDMAC_DT_PERID(42))>; 786 dma-names = "tx", "rx"; 787 clocks = <&pmc PMC_TYPE_PERIPHERAL 27>; 788 clock-names = "usart"; 789 status = "disabled"; 790 }; 791 792 uart4: serial@fc00c000 { 793 compatible = "atmel,at91sam9260-usart"; 794 reg = <0xfc00c000 0x100>; 795 dmas = <&dma0 796 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 797 AT91_XDMAC_DT_PERID(43))>, 798 <&dma0 799 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 800 AT91_XDMAC_DT_PERID(44))>; 801 dma-names = "tx", "rx"; 802 interrupts = <28 IRQ_TYPE_LEVEL_HIGH 7>; 803 clocks = <&pmc PMC_TYPE_PERIPHERAL 28>; 804 clock-names = "usart"; 805 status = "disabled"; 806 }; 807 808 flx2: flexcom@fc010000 { 809 compatible = "atmel,sama5d2-flexcom"; 810 reg = <0xfc010000 0x200>; 811 clocks = <&pmc PMC_TYPE_PERIPHERAL 21>; 812 #address-cells = <1>; 813 #size-cells = <1>; 814 ranges = <0x0 0xfc010000 0x800>; 815 status = "disabled"; 816 817 uart7: serial@200 { 818 compatible = "atmel,at91sam9260-usart"; 819 reg = <0x200 0x200>; 820 interrupts = <21 IRQ_TYPE_LEVEL_HIGH 7>; 821 clocks = <&pmc PMC_TYPE_PERIPHERAL 21>; 822 clock-names = "usart"; 823 dmas = <&dma0 824 (AT91_XDMAC_DT_MEM_IF(0) | 825 AT91_XDMAC_DT_PER_IF(1) | 826 AT91_XDMAC_DT_PERID(15))>, 827 <&dma0 828 (AT91_XDMAC_DT_MEM_IF(0) | 829 AT91_XDMAC_DT_PER_IF(1) | 830 AT91_XDMAC_DT_PERID(16))>; 831 dma-names = "tx", "rx"; 832 atmel,fifo-size = <32>; 833 status = "disabled"; 834 }; 835 836 spi4: spi@400 { 837 compatible = "atmel,at91rm9200-spi"; 838 reg = <0x400 0x200>; 839 interrupts = <21 IRQ_TYPE_LEVEL_HIGH 7>; 840 #address-cells = <1>; 841 #size-cells = <0>; 842 clocks = <&pmc PMC_TYPE_PERIPHERAL 21>; 843 clock-names = "spi_clk"; 844 dmas = <&dma0 845 (AT91_XDMAC_DT_MEM_IF(0) | 846 AT91_XDMAC_DT_PER_IF(1) | 847 AT91_XDMAC_DT_PERID(15))>, 848 <&dma0 849 (AT91_XDMAC_DT_MEM_IF(0) | 850 AT91_XDMAC_DT_PER_IF(1) | 851 AT91_XDMAC_DT_PERID(16))>; 852 dma-names = "tx", "rx"; 853 atmel,fifo-size = <16>; 854 status = "disabled"; 855 }; 856 857 i2c4: i2c@600 { 858 compatible = "atmel,sama5d2-i2c"; 859 reg = <0x600 0x200>; 860 interrupts = <21 IRQ_TYPE_LEVEL_HIGH 7>; 861 #address-cells = <1>; 862 #size-cells = <0>; 863 clocks = <&pmc PMC_TYPE_PERIPHERAL 21>; 864 dmas = <&dma0 865 (AT91_XDMAC_DT_MEM_IF(0) | 866 AT91_XDMAC_DT_PER_IF(1) | 867 AT91_XDMAC_DT_PERID(15))>, 868 <&dma0 869 (AT91_XDMAC_DT_MEM_IF(0) | 870 AT91_XDMAC_DT_PER_IF(1) | 871 AT91_XDMAC_DT_PERID(16))>; 872 dma-names = "tx", "rx"; 873 atmel,fifo-size = <16>; 874 status = "disabled"; 875 }; 876 }; 877 878 flx3: flexcom@fc014000 { 879 compatible = "atmel,sama5d2-flexcom"; 880 reg = <0xfc014000 0x200>; 881 clocks = <&pmc PMC_TYPE_PERIPHERAL 22>; 882 #address-cells = <1>; 883 #size-cells = <1>; 884 ranges = <0x0 0xfc014000 0x800>; 885 status = "disabled"; 886 887 uart8: serial@200 { 888 compatible = "atmel,at91sam9260-usart"; 889 reg = <0x200 0x200>; 890 interrupts = <22 IRQ_TYPE_LEVEL_HIGH 7>; 891 clocks = <&pmc PMC_TYPE_PERIPHERAL 22>; 892 clock-names = "usart"; 893 dmas = <&dma0 894 (AT91_XDMAC_DT_MEM_IF(0) | 895 AT91_XDMAC_DT_PER_IF(1) | 896 AT91_XDMAC_DT_PERID(17))>, 897 <&dma0 898 (AT91_XDMAC_DT_MEM_IF(0) | 899 AT91_XDMAC_DT_PER_IF(1) | 900 AT91_XDMAC_DT_PERID(18))>; 901 dma-names = "tx", "rx"; 902 atmel,fifo-size = <32>; 903 status = "disabled"; 904 }; 905 906 spi5: spi@400 { 907 compatible = "atmel,at91rm9200-spi"; 908 reg = <0x400 0x200>; 909 interrupts = <22 IRQ_TYPE_LEVEL_HIGH 7>; 910 #address-cells = <1>; 911 #size-cells = <0>; 912 clocks = <&pmc PMC_TYPE_PERIPHERAL 22>; 913 clock-names = "spi_clk"; 914 dmas = <&dma0 915 (AT91_XDMAC_DT_MEM_IF(0) | 916 AT91_XDMAC_DT_PER_IF(1) | 917 AT91_XDMAC_DT_PERID(17))>, 918 <&dma0 919 (AT91_XDMAC_DT_MEM_IF(0) | 920 AT91_XDMAC_DT_PER_IF(1) | 921 AT91_XDMAC_DT_PERID(18))>; 922 dma-names = "tx", "rx"; 923 atmel,fifo-size = <16>; 924 status = "disabled"; 925 }; 926 927 i2c5: i2c@600 { 928 compatible = "atmel,sama5d2-i2c"; 929 reg = <0x600 0x200>; 930 interrupts = <22 IRQ_TYPE_LEVEL_HIGH 7>; 931 #address-cells = <1>; 932 #size-cells = <0>; 933 clocks = <&pmc PMC_TYPE_PERIPHERAL 22>; 934 dmas = <&dma0 935 (AT91_XDMAC_DT_MEM_IF(0) | 936 AT91_XDMAC_DT_PER_IF(1) | 937 AT91_XDMAC_DT_PERID(17))>, 938 <&dma0 939 (AT91_XDMAC_DT_MEM_IF(0) | 940 AT91_XDMAC_DT_PER_IF(1) | 941 AT91_XDMAC_DT_PERID(18))>; 942 dma-names = "tx", "rx"; 943 atmel,fifo-size = <16>; 944 status = "disabled"; 945 }; 946 947 }; 948 949 flx4: flexcom@fc018000 { 950 compatible = "atmel,sama5d2-flexcom"; 951 reg = <0xfc018000 0x200>; 952 clocks = <&pmc PMC_TYPE_PERIPHERAL 23>; 953 #address-cells = <1>; 954 #size-cells = <1>; 955 ranges = <0x0 0xfc018000 0x800>; 956 status = "disabled"; 957 958 uart9: serial@200 { 959 compatible = "atmel,at91sam9260-usart"; 960 reg = <0x200 0x200>; 961 interrupts = <23 IRQ_TYPE_LEVEL_HIGH 7>; 962 clocks = <&pmc PMC_TYPE_PERIPHERAL 23>; 963 clock-names = "usart"; 964 dmas = <&dma0 965 (AT91_XDMAC_DT_MEM_IF(0) | 966 AT91_XDMAC_DT_PER_IF(1) | 967 AT91_XDMAC_DT_PERID(19))>, 968 <&dma0 969 (AT91_XDMAC_DT_MEM_IF(0) | 970 AT91_XDMAC_DT_PER_IF(1) | 971 AT91_XDMAC_DT_PERID(20))>; 972 dma-names = "tx", "rx"; 973 atmel,fifo-size = <32>; 974 status = "disabled"; 975 }; 976 977 spi6: spi@400 { 978 compatible = "atmel,at91rm9200-spi"; 979 reg = <0x400 0x200>; 980 interrupts = <23 IRQ_TYPE_LEVEL_HIGH 7>; 981 #address-cells = <1>; 982 #size-cells = <0>; 983 clocks = <&pmc PMC_TYPE_PERIPHERAL 23>; 984 clock-names = "spi_clk"; 985 dmas = <&dma0 986 (AT91_XDMAC_DT_MEM_IF(0) | 987 AT91_XDMAC_DT_PER_IF(1) | 988 AT91_XDMAC_DT_PERID(19))>, 989 <&dma0 990 (AT91_XDMAC_DT_MEM_IF(0) | 991 AT91_XDMAC_DT_PER_IF(1) | 992 AT91_XDMAC_DT_PERID(20))>; 993 dma-names = "tx", "rx"; 994 atmel,fifo-size = <16>; 995 status = "disabled"; 996 }; 997 998 i2c6: i2c@600 { 999 compatible = "atmel,sama5d2-i2c"; 1000 reg = <0x600 0x200>; 1001 interrupts = <23 IRQ_TYPE_LEVEL_HIGH 7>; 1002 #address-cells = <1>; 1003 #size-cells = <0>; 1004 clocks = <&pmc PMC_TYPE_PERIPHERAL 23>; 1005 dmas = <&dma0 1006 (AT91_XDMAC_DT_MEM_IF(0) | 1007 AT91_XDMAC_DT_PER_IF(1) | 1008 AT91_XDMAC_DT_PERID(19))>, 1009 <&dma0 1010 (AT91_XDMAC_DT_MEM_IF(0) | 1011 AT91_XDMAC_DT_PER_IF(1) | 1012 AT91_XDMAC_DT_PERID(20))>; 1013 dma-names = "tx", "rx"; 1014 atmel,fifo-size = <16>; 1015 status = "disabled"; 1016 }; 1017 }; 1018 1019 trng@fc01c000 { 1020 compatible = "atmel,at91sam9g45-trng"; 1021 reg = <0xfc01c000 0x100>; 1022 interrupts = <47 IRQ_TYPE_LEVEL_HIGH 0>; 1023 clocks = <&pmc PMC_TYPE_PERIPHERAL 47>; 1024 status = "disabled"; 1025 secure-status = "okay"; 1026 }; 1027 1028 aic: interrupt-controller@fc020000 { 1029 #interrupt-cells = <3>; 1030 compatible = "atmel,sama5d2-aic"; 1031 interrupt-controller; 1032 reg = <0xfc020000 0x200>; 1033 atmel,external-irqs = <49>; 1034 }; 1035 1036 saic: interrupt-controller@f803c000 { 1037 #interrupt-cells = <3>; 1038 compatible = "atmel,sama5d2-saic"; 1039 interrupt-controller; 1040 reg = <0xf803c000 0x200>; 1041 atmel,external-irqs = <49>; 1042 status = "disabled"; 1043 secure-status = "okay"; 1044 }; 1045 1046 i2c1: i2c@fc028000 { 1047 compatible = "atmel,sama5d2-i2c"; 1048 reg = <0xfc028000 0x100>; 1049 interrupts = <30 IRQ_TYPE_LEVEL_HIGH 7>; 1050 dmas = <&dma0 1051 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 1052 AT91_XDMAC_DT_PERID(2))>, 1053 <&dma0 1054 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 1055 AT91_XDMAC_DT_PERID(3))>; 1056 dma-names = "tx", "rx"; 1057 #address-cells = <1>; 1058 #size-cells = <0>; 1059 clocks = <&pmc PMC_TYPE_PERIPHERAL 30>; 1060 atmel,fifo-size = <16>; 1061 status = "disabled"; 1062 }; 1063 1064 adc: adc@fc030000 { 1065 compatible = "atmel,sama5d2-adc"; 1066 reg = <0xfc030000 0x100>; 1067 interrupts = <40 IRQ_TYPE_LEVEL_HIGH 7>; 1068 clocks = <&pmc PMC_TYPE_PERIPHERAL 40>; 1069 clock-names = "adc_clk"; 1070 dmas = <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | AT91_XDMAC_DT_PERID(25))>; 1071 dma-names = "rx"; 1072 atmel,min-sample-rate-hz = <200000>; 1073 atmel,max-sample-rate-hz = <20000000>; 1074 atmel,startup-time-ms = <4>; 1075 atmel,trigger-edge-type = <IRQ_TYPE_EDGE_RISING>; 1076 #io-channel-cells = <1>; 1077 status = "disabled"; 1078 }; 1079 1080 resistive_touch: resistive-touch { 1081 compatible = "resistive-adc-touch"; 1082 io-channels = <&adc AT91_SAMA5D2_ADC_X_CHANNEL>, 1083 <&adc AT91_SAMA5D2_ADC_Y_CHANNEL>, 1084 <&adc AT91_SAMA5D2_ADC_P_CHANNEL>; 1085 io-channel-names = "x", "y", "pressure"; 1086 touchscreen-min-pressure = <50000>; 1087 status = "disabled"; 1088 }; 1089 1090 pioA: pinctrl@fc038000 { 1091 compatible = "atmel,sama5d2-pinctrl"; 1092 reg = <0xfc038000 0x600>; 1093 interrupts = <18 IRQ_TYPE_LEVEL_HIGH 7>, 1094 <68 IRQ_TYPE_LEVEL_HIGH 7>, 1095 <69 IRQ_TYPE_LEVEL_HIGH 7>, 1096 <70 IRQ_TYPE_LEVEL_HIGH 7>; 1097 interrupt-controller; 1098 #interrupt-cells = <2>; 1099 gpio-controller; 1100 #gpio-cells = <2>; 1101 clocks = <&pmc PMC_TYPE_PERIPHERAL 18>; 1102 }; 1103 1104 pioBU: secumod@fc040000 { 1105 compatible = "atmel,sama5d2-secumod", "syscon"; 1106 reg = <0xfc040000 0x100>; 1107 1108 gpio-controller; 1109 #gpio-cells = <2>; 1110 status = "disabled"; 1111 secure-status = "okay"; 1112 }; 1113 1114 tdes@fc044000 { 1115 compatible = "atmel,at91sam9g46-tdes"; 1116 reg = <0xfc044000 0x100>; 1117 interrupts = <11 IRQ_TYPE_LEVEL_HIGH 0>; 1118 dmas = <&dma0 1119 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 1120 AT91_XDMAC_DT_PERID(28))>, 1121 <&dma0 1122 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 1123 AT91_XDMAC_DT_PERID(29))>; 1124 dma-names = "tx", "rx"; 1125 clocks = <&pmc PMC_TYPE_PERIPHERAL 11>; 1126 clock-names = "tdes_clk"; 1127 status = "okay"; 1128 }; 1129 1130 classd: classd@fc048000 { 1131 compatible = "atmel,sama5d2-classd"; 1132 reg = <0xfc048000 0x100>; 1133 interrupts = <59 IRQ_TYPE_LEVEL_HIGH 7>; 1134 dmas = <&dma0 1135 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 1136 AT91_XDMAC_DT_PERID(47))>; 1137 dma-names = "tx"; 1138 clocks = <&pmc PMC_TYPE_PERIPHERAL 59>, <&pmc PMC_TYPE_GCK 59>; 1139 clock-names = "pclk", "gclk"; 1140 status = "disabled"; 1141 }; 1142 1143 i2s1: i2s@fc04c000 { 1144 compatible = "atmel,sama5d2-i2s"; 1145 reg = <0xfc04c000 0x100>; 1146 interrupts = <55 IRQ_TYPE_LEVEL_HIGH 7>; 1147 dmas = <&dma0 1148 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 1149 AT91_XDMAC_DT_PERID(33))>, 1150 <&dma0 1151 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 1152 AT91_XDMAC_DT_PERID(34))>; 1153 dma-names = "tx", "rx"; 1154 clocks = <&pmc PMC_TYPE_PERIPHERAL 55>, <&pmc PMC_TYPE_GCK 55>; 1155 clock-names = "pclk", "gclk"; 1156 assigned-clocks = <&pmc PMC_TYPE_CORE PMC_I2S1_MUX>; 1157 assigned-parrents = <&pmc PMC_TYPE_GCK 55>; 1158 status = "disabled"; 1159 }; 1160 1161 can1: can@fc050000 { 1162 compatible = "bosch,m_can"; 1163 reg = <0xfc050000 0x4000>, <0x210000 0x3800>; 1164 reg-names = "m_can", "message_ram"; 1165 interrupts = <57 IRQ_TYPE_LEVEL_HIGH 7>, 1166 <65 IRQ_TYPE_LEVEL_HIGH 7>; 1167 interrupt-names = "int0", "int1"; 1168 clocks = <&pmc PMC_TYPE_PERIPHERAL 57>, <&pmc PMC_TYPE_GCK 57>; 1169 clock-names = "hclk", "cclk"; 1170 assigned-clocks = <&pmc PMC_TYPE_GCK 57>; 1171 assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_UTMI>; 1172 assigned-clock-rates = <40000000>; 1173 bosch,mram-cfg = <0x1c00 0 0 64 0 0 32 32>; 1174 status = "disabled"; 1175 }; 1176 1177 sfrbu: sfr@fc05c000 { 1178 compatible = "atmel,sama5d2-sfrbu", "syscon"; 1179 reg = <0xfc05c000 0x20>; 1180 }; 1181 1182 chipid@fc069000 { 1183 compatible = "atmel,sama5d2-chipid"; 1184 reg = <0xfc069000 0x8>; 1185 }; 1186 }; 1187 }; 1188}; 1189