1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * sama5d2.dtsi - Device Tree Include file for SAMA5D2 family SoC 4 * 5 * Copyright (C) 2015 Atmel, 6 * 2015 Ludovic Desroches <ludovic.desroches@atmel.com> 7 */ 8 9#include <dt-bindings/dma/at91.h> 10#include <dt-bindings/interrupt-controller/irq.h> 11#include <dt-bindings/clock/at91.h> 12#include <dt-bindings/iio/adc/at91-sama5d2_adc.h> 13 14/ { 15 #address-cells = <1>; 16 #size-cells = <1>; 17 model = "Atmel SAMA5D2 family SoC"; 18 compatible = "atmel,sama5d2"; 19 interrupt-parent = <&aic>; 20 21 aliases { 22 serial0 = &uart1; 23 serial1 = &uart3; 24 }; 25 26 cpus { 27 #address-cells = <1>; 28 #size-cells = <0>; 29 30 cpu@0 { 31 device_type = "cpu"; 32 compatible = "arm,cortex-a5"; 33 reg = <0>; 34 next-level-cache = <&L2>; 35 clocks = <&pmc PMC_TYPE_CORE PMC_MCK_PRES>; 36 clock-names = "cpu"; 37 }; 38 }; 39 40 pmu { 41 compatible = "arm,cortex-a5-pmu"; 42 interrupts = <2 IRQ_TYPE_LEVEL_HIGH 0>; 43 }; 44 45 etb@740000 { 46 compatible = "arm,coresight-etb10", "arm,primecell"; 47 reg = <0x740000 0x1000>; 48 49 clocks = <&pmc PMC_TYPE_CORE PMC_MCK>; 50 clock-names = "apb_pclk"; 51 52 in-ports { 53 port { 54 etb_in: endpoint { 55 remote-endpoint = <&etm_out>; 56 }; 57 }; 58 }; 59 }; 60 61 etm@73c000 { 62 compatible = "arm,coresight-etm3x", "arm,primecell"; 63 reg = <0x73c000 0x1000>; 64 65 clocks = <&pmc PMC_TYPE_CORE PMC_MCK>; 66 clock-names = "apb_pclk"; 67 68 out-ports { 69 port { 70 etm_out: endpoint { 71 remote-endpoint = <&etb_in>; 72 }; 73 }; 74 }; 75 }; 76 77 memory@20000000 { 78 device_type = "memory"; 79 reg = <0x20000000 0x20000000>; 80 }; 81 82 clocks { 83 slow_xtal: slow_xtal { 84 compatible = "fixed-clock"; 85 #clock-cells = <0>; 86 clock-frequency = <0>; 87 }; 88 89 main_xtal: main_xtal { 90 compatible = "fixed-clock"; 91 #clock-cells = <0>; 92 clock-frequency = <0>; 93 }; 94 }; 95 96 ns_sram: sram@200000 { 97 compatible = "atmel,sama5d2-sram", "mmio-sram"; 98 reg = <0x00200000 0x20000>; 99 #address-cells = <1>; 100 #size-cells = <1>; 101 ranges = <0 0x00200000 0x20000>; 102 status = "disabled"; 103 secure-status = "okay"; 104 }; 105 106 ahb { 107 compatible = "simple-bus"; 108 #address-cells = <1>; 109 #size-cells = <1>; 110 ranges; 111 112 nfc_sram: sram@100000 { 113 compatible = "mmio-sram"; 114 no-memory-wc; 115 reg = <0x00100000 0x2400>; 116 #address-cells = <1>; 117 #size-cells = <1>; 118 ranges = <0 0x00100000 0x2400>; 119 120 }; 121 122 usb0: gadget@300000 { 123 compatible = "atmel,sama5d3-udc"; 124 reg = <0x00300000 0x100000 125 0xfc02c000 0x400>; 126 interrupts = <42 IRQ_TYPE_LEVEL_HIGH 2>; 127 clocks = <&pmc PMC_TYPE_PERIPHERAL 42>, <&pmc PMC_TYPE_CORE PMC_UTMI>; 128 clock-names = "pclk", "hclk"; 129 assigned-clocks = <&pmc PMC_TYPE_CORE PMC_USBCK>; 130 assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_UTMI>; 131 assigned-clock-rates = <48000000>; 132 status = "disabled"; 133 }; 134 135 usb1: ohci@400000 { 136 compatible = "atmel,at91rm9200-ohci", "usb-ohci"; 137 reg = <0x00400000 0x100000>; 138 interrupts = <41 IRQ_TYPE_LEVEL_HIGH 2>; 139 clocks = <&pmc PMC_TYPE_PERIPHERAL 41>, <&pmc PMC_TYPE_PERIPHERAL 41>, <&pmc PMC_TYPE_SYSTEM 6>; 140 clock-names = "ohci_clk", "hclk", "uhpck"; 141 assigned-clocks = <&pmc PMC_TYPE_CORE PMC_USBCK>; 142 assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_UTMI>; 143 assigned-clock-rates = <48000000>; 144 status = "disabled"; 145 }; 146 147 usb2: ehci@500000 { 148 compatible = "atmel,at91sam9g45-ehci", "usb-ehci"; 149 reg = <0x00500000 0x100000>; 150 interrupts = <41 IRQ_TYPE_LEVEL_HIGH 2>; 151 clocks = <&pmc PMC_TYPE_CORE PMC_UTMI>, <&pmc PMC_TYPE_PERIPHERAL 41>; 152 clock-names = "usb_clk", "ehci_clk"; 153 assigned-clocks = <&pmc PMC_TYPE_CORE PMC_USBCK>; 154 assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_UTMI>; 155 assigned-clock-rates = <48000000>; 156 status = "disabled"; 157 }; 158 159 L2: cache-controller@a00000 { 160 compatible = "arm,pl310-cache"; 161 reg = <0x00a00000 0x1000>; 162 interrupts = <63 IRQ_TYPE_LEVEL_HIGH 4>; 163 cache-unified; 164 cache-level = <2>; 165 }; 166 167 ebi: ebi@10000000 { 168 compatible = "atmel,sama5d3-ebi"; 169 #address-cells = <2>; 170 #size-cells = <1>; 171 atmel,smc = <&hsmc>; 172 reg = <0x10000000 0x10000000 173 0x60000000 0x30000000>; 174 ranges = <0x0 0x0 0x10000000 0x10000000 175 0x1 0x0 0x60000000 0x10000000 176 0x2 0x0 0x70000000 0x10000000 177 0x3 0x0 0x80000000 0x10000000>; 178 clocks = <&pmc PMC_TYPE_CORE PMC_MCK2>; 179 status = "disabled"; 180 181 nand_controller: nand-controller { 182 compatible = "atmel,sama5d3-nand-controller"; 183 atmel,nfc-sram = <&nfc_sram>; 184 atmel,nfc-io = <&nfc_io>; 185 ecc-engine = <&pmecc>; 186 #address-cells = <2>; 187 #size-cells = <1>; 188 ranges; 189 status = "disabled"; 190 }; 191 }; 192 193 sdmmc0: sdio-host@a0000000 { 194 compatible = "atmel,sama5d2-sdhci"; 195 reg = <0xa0000000 0x300>; 196 interrupts = <31 IRQ_TYPE_LEVEL_HIGH 0>; 197 clocks = <&pmc PMC_TYPE_PERIPHERAL 31>, <&pmc PMC_TYPE_GCK 31>, <&pmc PMC_TYPE_CORE PMC_MAIN>; 198 clock-names = "hclock", "multclk", "baseclk"; 199 assigned-clocks = <&pmc PMC_TYPE_GCK 31>; 200 assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_UTMI>; 201 assigned-clock-rates = <480000000>; 202 status = "disabled"; 203 }; 204 205 sdmmc1: sdio-host@b0000000 { 206 compatible = "atmel,sama5d2-sdhci"; 207 reg = <0xb0000000 0x300>; 208 interrupts = <32 IRQ_TYPE_LEVEL_HIGH 0>; 209 clocks = <&pmc PMC_TYPE_PERIPHERAL 32>, <&pmc PMC_TYPE_GCK 32>, <&pmc PMC_TYPE_CORE PMC_MAIN>; 210 clock-names = "hclock", "multclk", "baseclk"; 211 assigned-clocks = <&pmc PMC_TYPE_GCK 32>; 212 assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_UTMI>; 213 assigned-clock-rates = <480000000>; 214 status = "disabled"; 215 }; 216 217 nfc_io: nfc-io@c0000000 { 218 compatible = "atmel,sama5d3-nfc-io", "syscon"; 219 reg = <0xc0000000 0x8000000>; 220 }; 221 222 apb { 223 compatible = "simple-bus"; 224 #address-cells = <1>; 225 #size-cells = <1>; 226 ranges; 227 228 hlcdc: hlcdc@f0000000 { 229 compatible = "atmel,sama5d2-hlcdc"; 230 reg = <0xf0000000 0x2000>; 231 interrupts = <45 IRQ_TYPE_LEVEL_HIGH 0>; 232 clocks = <&pmc PMC_TYPE_PERIPHERAL 45>, <&pmc PMC_TYPE_SYSTEM 3>, <&clk32k>; 233 clock-names = "periph_clk","sys_clk", "slow_clk"; 234 status = "disabled"; 235 236 hlcdc-display-controller { 237 compatible = "atmel,hlcdc-display-controller"; 238 #address-cells = <1>; 239 #size-cells = <0>; 240 241 port@0 { 242 #address-cells = <1>; 243 #size-cells = <0>; 244 reg = <0>; 245 }; 246 }; 247 248 hlcdc_pwm: hlcdc-pwm { 249 compatible = "atmel,hlcdc-pwm"; 250 #pwm-cells = <3>; 251 }; 252 }; 253 254 isc: isc@f0008000 { 255 compatible = "atmel,sama5d2-isc"; 256 reg = <0xf0008000 0x4000>; 257 interrupts = <46 IRQ_TYPE_LEVEL_HIGH 5>; 258 clocks = <&pmc PMC_TYPE_PERIPHERAL 46>, <&pmc PMC_TYPE_SYSTEM 18>, <&pmc PMC_TYPE_GCK 46>; 259 clock-names = "hclock", "iscck", "gck"; 260 #clock-cells = <0>; 261 clock-output-names = "isc-mck"; 262 status = "disabled"; 263 }; 264 265 ramc0: ramc@f000c000 { 266 compatible = "atmel,sama5d3-ddramc"; 267 reg = <0xf000c000 0x200>; 268 clocks = <&pmc PMC_TYPE_SYSTEM 2>, <&pmc PMC_TYPE_PERIPHERAL 13>; 269 clock-names = "ddrck", "mpddr"; 270 }; 271 272 dma0: dma-controller@f0010000 { 273 compatible = "atmel,sama5d4-dma"; 274 reg = <0xf0010000 0x1000>; 275 interrupts = <6 IRQ_TYPE_LEVEL_HIGH 0>; 276 #dma-cells = <1>; 277 clocks = <&pmc PMC_TYPE_PERIPHERAL 6>; 278 clock-names = "dma_clk"; 279 }; 280 281 /* Place dma1 here despite its address */ 282 dma1: dma-controller@f0004000 { 283 compatible = "atmel,sama5d4-dma"; 284 reg = <0xf0004000 0x1000>; 285 interrupts = <7 IRQ_TYPE_LEVEL_HIGH 0>; 286 #dma-cells = <1>; 287 clocks = <&pmc PMC_TYPE_PERIPHERAL 7>; 288 clock-names = "dma_clk"; 289 }; 290 291 pmc: pmc@f0014000 { 292 compatible = "atmel,sama5d2-pmc", "syscon"; 293 reg = <0xf0014000 0x160>; 294 interrupts = <74 IRQ_TYPE_LEVEL_HIGH 7>; 295 #clock-cells = <2>; 296 clocks = <&clk32k>, <&main_xtal>; 297 clock-names = "slow_clk", "main_xtal"; 298 status = "disabled"; 299 secure-status = "okay"; 300 }; 301 302 qspi0: spi@f0020000 { 303 compatible = "atmel,sama5d2-qspi"; 304 reg = <0xf0020000 0x100>, <0xd0000000 0x08000000>; 305 reg-names = "qspi_base", "qspi_mmap"; 306 interrupts = <52 IRQ_TYPE_LEVEL_HIGH 7>; 307 clocks = <&pmc PMC_TYPE_PERIPHERAL 52>; 308 #address-cells = <1>; 309 #size-cells = <0>; 310 status = "disabled"; 311 }; 312 313 qspi1: spi@f0024000 { 314 compatible = "atmel,sama5d2-qspi"; 315 reg = <0xf0024000 0x100>, <0xd8000000 0x08000000>; 316 reg-names = "qspi_base", "qspi_mmap"; 317 interrupts = <53 IRQ_TYPE_LEVEL_HIGH 7>; 318 clocks = <&pmc PMC_TYPE_PERIPHERAL 53>; 319 #address-cells = <1>; 320 #size-cells = <0>; 321 status = "disabled"; 322 }; 323 324 sha@f0028000 { 325 compatible = "atmel,at91sam9g46-sha"; 326 reg = <0xf0028000 0x100>; 327 interrupts = <12 IRQ_TYPE_LEVEL_HIGH 0>; 328 dmas = <&dma0 329 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 330 AT91_XDMAC_DT_PERID(30))>; 331 dma-names = "tx"; 332 clocks = <&pmc PMC_TYPE_PERIPHERAL 12>; 333 clock-names = "sha_clk"; 334 status = "okay"; 335 }; 336 337 aes@f002c000 { 338 compatible = "atmel,at91sam9g46-aes"; 339 reg = <0xf002c000 0x100>; 340 interrupts = <9 IRQ_TYPE_LEVEL_HIGH 0>; 341 dmas = <&dma0 342 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 343 AT91_XDMAC_DT_PERID(26))>, 344 <&dma0 345 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 346 AT91_XDMAC_DT_PERID(27))>; 347 dma-names = "tx", "rx"; 348 clocks = <&pmc PMC_TYPE_PERIPHERAL 9>; 349 clock-names = "aes_clk"; 350 status = "okay"; 351 }; 352 353 spi0: spi@f8000000 { 354 compatible = "atmel,at91rm9200-spi"; 355 reg = <0xf8000000 0x100>; 356 interrupts = <33 IRQ_TYPE_LEVEL_HIGH 7>; 357 dmas = <&dma0 358 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 359 AT91_XDMAC_DT_PERID(6))>, 360 <&dma0 361 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 362 AT91_XDMAC_DT_PERID(7))>; 363 dma-names = "tx", "rx"; 364 clocks = <&pmc PMC_TYPE_PERIPHERAL 33>; 365 clock-names = "spi_clk"; 366 atmel,fifo-size = <16>; 367 #address-cells = <1>; 368 #size-cells = <0>; 369 status = "disabled"; 370 }; 371 372 ssc0: ssc@f8004000 { 373 compatible = "atmel,at91sam9g45-ssc"; 374 reg = <0xf8004000 0x4000>; 375 interrupts = <43 IRQ_TYPE_LEVEL_HIGH 4>; 376 dmas = <&dma0 377 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 378 AT91_XDMAC_DT_PERID(21))>, 379 <&dma0 380 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 381 AT91_XDMAC_DT_PERID(22))>; 382 dma-names = "tx", "rx"; 383 clocks = <&pmc PMC_TYPE_PERIPHERAL 43>; 384 clock-names = "pclk"; 385 status = "disabled"; 386 }; 387 388 macb0: ethernet@f8008000 { 389 compatible = "atmel,sama5d2-gem"; 390 reg = <0xf8008000 0x1000>; 391 interrupts = <5 IRQ_TYPE_LEVEL_HIGH 3 /* Queue 0 */ 392 66 IRQ_TYPE_LEVEL_HIGH 3 /* Queue 1 */ 393 67 IRQ_TYPE_LEVEL_HIGH 3>; /* Queue 2 */ 394 #address-cells = <1>; 395 #size-cells = <0>; 396 clocks = <&pmc PMC_TYPE_PERIPHERAL 5>, <&pmc PMC_TYPE_PERIPHERAL 5>; 397 clock-names = "hclk", "pclk"; 398 status = "disabled"; 399 }; 400 401 tcb0: timer@f800c000 { 402 compatible = "atmel,sama5d2-tcb", "simple-mfd", "syscon"; 403 #address-cells = <1>; 404 #size-cells = <0>; 405 reg = <0xf800c000 0x100>; 406 interrupts = <35 IRQ_TYPE_LEVEL_HIGH 0>; 407 clocks = <&pmc PMC_TYPE_PERIPHERAL 35>, <&pmc PMC_TYPE_GCK 35>, <&clk32k>; 408 clock-names = "t0_clk", "gclk", "slow_clk"; 409 }; 410 411 tcb1: timer@f8010000 { 412 compatible = "atmel,sama5d2-tcb", "simple-mfd", "syscon"; 413 #address-cells = <1>; 414 #size-cells = <0>; 415 reg = <0xf8010000 0x100>; 416 interrupts = <36 IRQ_TYPE_LEVEL_HIGH 0>; 417 clocks = <&pmc PMC_TYPE_PERIPHERAL 36>, <&pmc PMC_TYPE_GCK 36>, <&clk32k>; 418 clock-names = "t0_clk", "gclk", "slow_clk"; 419 status = "disabled"; 420 secure-status = "okay"; 421 }; 422 423 hsmc: hsmc@f8014000 { 424 compatible = "atmel,sama5d2-smc", "syscon", "simple-mfd"; 425 reg = <0xf8014000 0x1000>; 426 interrupts = <17 IRQ_TYPE_LEVEL_HIGH 6>; 427 clocks = <&pmc PMC_TYPE_PERIPHERAL 17>; 428 #address-cells = <1>; 429 #size-cells = <1>; 430 ranges; 431 432 pmecc: ecc-engine@f8014070 { 433 compatible = "atmel,sama5d2-pmecc"; 434 reg = <0xf8014070 0x490>, 435 <0xf8014500 0x100>; 436 }; 437 }; 438 439 pdmic: pdmic@f8018000 { 440 compatible = "atmel,sama5d2-pdmic"; 441 reg = <0xf8018000 0x124>; 442 interrupts = <48 IRQ_TYPE_LEVEL_HIGH 7>; 443 dmas = <&dma0 444 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) 445 | AT91_XDMAC_DT_PERID(50))>; 446 dma-names = "rx"; 447 clocks = <&pmc PMC_TYPE_PERIPHERAL 48>, <&pmc PMC_TYPE_GCK 48>; 448 clock-names = "pclk", "gclk"; 449 status = "disabled"; 450 }; 451 452 uart0: serial@f801c000 { 453 compatible = "atmel,at91sam9260-usart"; 454 reg = <0xf801c000 0x100>; 455 interrupts = <24 IRQ_TYPE_LEVEL_HIGH 7>; 456 dmas = <&dma0 457 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 458 AT91_XDMAC_DT_PERID(35))>, 459 <&dma0 460 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 461 AT91_XDMAC_DT_PERID(36))>; 462 dma-names = "tx", "rx"; 463 clocks = <&pmc PMC_TYPE_PERIPHERAL 24>; 464 clock-names = "usart"; 465 status = "disabled"; 466 }; 467 468 uart1: serial@f8020000 { 469 compatible = "atmel,at91sam9260-usart"; 470 reg = <0xf8020000 0x100>; 471 interrupts = <25 IRQ_TYPE_LEVEL_HIGH 7>; 472 dmas = <&dma0 473 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 474 AT91_XDMAC_DT_PERID(37))>, 475 <&dma0 476 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 477 AT91_XDMAC_DT_PERID(38))>; 478 dma-names = "tx", "rx"; 479 clocks = <&pmc PMC_TYPE_PERIPHERAL 25>; 480 clock-names = "usart"; 481 status = "disabled"; 482 }; 483 484 uart2: serial@f8024000 { 485 compatible = "atmel,at91sam9260-usart"; 486 reg = <0xf8024000 0x100>; 487 interrupts = <26 IRQ_TYPE_LEVEL_HIGH 7>; 488 dmas = <&dma0 489 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 490 AT91_XDMAC_DT_PERID(39))>, 491 <&dma0 492 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 493 AT91_XDMAC_DT_PERID(40))>; 494 dma-names = "tx", "rx"; 495 clocks = <&pmc PMC_TYPE_PERIPHERAL 26>; 496 clock-names = "usart"; 497 status = "disabled"; 498 }; 499 500 i2c0: i2c@f8028000 { 501 compatible = "atmel,sama5d2-i2c"; 502 reg = <0xf8028000 0x100>; 503 interrupts = <29 IRQ_TYPE_LEVEL_HIGH 7>; 504 dmas = <&dma0 505 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 506 AT91_XDMAC_DT_PERID(0))>, 507 <&dma0 508 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 509 AT91_XDMAC_DT_PERID(1))>; 510 dma-names = "tx", "rx"; 511 #address-cells = <1>; 512 #size-cells = <0>; 513 clocks = <&pmc PMC_TYPE_PERIPHERAL 29>; 514 atmel,fifo-size = <16>; 515 status = "disabled"; 516 }; 517 518 pwm0: pwm@f802c000 { 519 compatible = "atmel,sama5d2-pwm"; 520 reg = <0xf802c000 0x4000>; 521 interrupts = <38 IRQ_TYPE_LEVEL_HIGH 7>; 522 #pwm-cells = <3>; 523 clocks = <&pmc PMC_TYPE_PERIPHERAL 38>; 524 status = "disabled"; 525 }; 526 527 sfr: sfr@f8030000 { 528 compatible = "atmel,sama5d2-sfr", "syscon"; 529 reg = <0xf8030000 0x98>; 530 status = "disabled"; 531 secure-status = "okay"; 532 }; 533 534 flx0: flexcom@f8034000 { 535 compatible = "atmel,sama5d2-flexcom"; 536 reg = <0xf8034000 0x200>; 537 clocks = <&pmc PMC_TYPE_PERIPHERAL 19>; 538 #address-cells = <1>; 539 #size-cells = <1>; 540 ranges = <0x0 0xf8034000 0x800>; 541 status = "disabled"; 542 543 uart5: serial@200 { 544 compatible = "atmel,at91sam9260-usart"; 545 reg = <0x200 0x200>; 546 interrupts = <19 IRQ_TYPE_LEVEL_HIGH 7>; 547 clocks = <&pmc PMC_TYPE_PERIPHERAL 19>; 548 clock-names = "usart"; 549 dmas = <&dma0 550 (AT91_XDMAC_DT_MEM_IF(0) | 551 AT91_XDMAC_DT_PER_IF(1) | 552 AT91_XDMAC_DT_PERID(11))>, 553 <&dma0 554 (AT91_XDMAC_DT_MEM_IF(0) | 555 AT91_XDMAC_DT_PER_IF(1) | 556 AT91_XDMAC_DT_PERID(12))>; 557 dma-names = "tx", "rx"; 558 atmel,fifo-size = <32>; 559 status = "disabled"; 560 }; 561 562 spi2: spi@400 { 563 compatible = "atmel,at91rm9200-spi"; 564 reg = <0x400 0x200>; 565 interrupts = <19 IRQ_TYPE_LEVEL_HIGH 7>; 566 #address-cells = <1>; 567 #size-cells = <0>; 568 clocks = <&pmc PMC_TYPE_PERIPHERAL 19>; 569 clock-names = "spi_clk"; 570 dmas = <&dma0 571 (AT91_XDMAC_DT_MEM_IF(0) | 572 AT91_XDMAC_DT_PER_IF(1) | 573 AT91_XDMAC_DT_PERID(11))>, 574 <&dma0 575 (AT91_XDMAC_DT_MEM_IF(0) | 576 AT91_XDMAC_DT_PER_IF(1) | 577 AT91_XDMAC_DT_PERID(12))>; 578 dma-names = "tx", "rx"; 579 atmel,fifo-size = <16>; 580 status = "disabled"; 581 }; 582 583 i2c2: i2c@600 { 584 compatible = "atmel,sama5d2-i2c"; 585 reg = <0x600 0x200>; 586 interrupts = <19 IRQ_TYPE_LEVEL_HIGH 7>; 587 #address-cells = <1>; 588 #size-cells = <0>; 589 clocks = <&pmc PMC_TYPE_PERIPHERAL 19>; 590 dmas = <&dma0 591 (AT91_XDMAC_DT_MEM_IF(0) | 592 AT91_XDMAC_DT_PER_IF(1) | 593 AT91_XDMAC_DT_PERID(11))>, 594 <&dma0 595 (AT91_XDMAC_DT_MEM_IF(0) | 596 AT91_XDMAC_DT_PER_IF(1) | 597 AT91_XDMAC_DT_PERID(12))>; 598 dma-names = "tx", "rx"; 599 atmel,fifo-size = <16>; 600 status = "disabled"; 601 }; 602 }; 603 604 flx1: flexcom@f8038000 { 605 compatible = "atmel,sama5d2-flexcom"; 606 reg = <0xf8038000 0x200>; 607 clocks = <&pmc PMC_TYPE_PERIPHERAL 20>; 608 #address-cells = <1>; 609 #size-cells = <1>; 610 ranges = <0x0 0xf8038000 0x800>; 611 status = "disabled"; 612 613 uart6: serial@200 { 614 compatible = "atmel,at91sam9260-usart"; 615 reg = <0x200 0x200>; 616 interrupts = <20 IRQ_TYPE_LEVEL_HIGH 7>; 617 clocks = <&pmc PMC_TYPE_PERIPHERAL 20>; 618 clock-names = "usart"; 619 dmas = <&dma0 620 (AT91_XDMAC_DT_MEM_IF(0) | 621 AT91_XDMAC_DT_PER_IF(1) | 622 AT91_XDMAC_DT_PERID(13))>, 623 <&dma0 624 (AT91_XDMAC_DT_MEM_IF(0) | 625 AT91_XDMAC_DT_PER_IF(1) | 626 AT91_XDMAC_DT_PERID(14))>; 627 dma-names = "tx", "rx"; 628 atmel,fifo-size = <32>; 629 status = "disabled"; 630 }; 631 632 spi3: spi@400 { 633 compatible = "atmel,at91rm9200-spi"; 634 reg = <0x400 0x200>; 635 interrupts = <20 IRQ_TYPE_LEVEL_HIGH 7>; 636 #address-cells = <1>; 637 #size-cells = <0>; 638 clocks = <&pmc PMC_TYPE_PERIPHERAL 20>; 639 clock-names = "spi_clk"; 640 dmas = <&dma0 641 (AT91_XDMAC_DT_MEM_IF(0) | 642 AT91_XDMAC_DT_PER_IF(1) | 643 AT91_XDMAC_DT_PERID(13))>, 644 <&dma0 645 (AT91_XDMAC_DT_MEM_IF(0) | 646 AT91_XDMAC_DT_PER_IF(1) | 647 AT91_XDMAC_DT_PERID(14))>; 648 dma-names = "tx", "rx"; 649 atmel,fifo-size = <16>; 650 status = "disabled"; 651 }; 652 653 i2c3: i2c@600 { 654 compatible = "atmel,sama5d2-i2c"; 655 reg = <0x600 0x200>; 656 interrupts = <20 IRQ_TYPE_LEVEL_HIGH 7>; 657 #address-cells = <1>; 658 #size-cells = <0>; 659 clocks = <&pmc PMC_TYPE_PERIPHERAL 20>; 660 dmas = <&dma0 661 (AT91_XDMAC_DT_MEM_IF(0) | 662 AT91_XDMAC_DT_PER_IF(1) | 663 AT91_XDMAC_DT_PERID(13))>, 664 <&dma0 665 (AT91_XDMAC_DT_MEM_IF(0) | 666 AT91_XDMAC_DT_PER_IF(1) | 667 AT91_XDMAC_DT_PERID(14))>; 668 dma-names = "tx", "rx"; 669 atmel,fifo-size = <16>; 670 status = "disabled"; 671 }; 672 }; 673 674 securam: sram@f8044000 { 675 compatible = "atmel,sama5d2-securam", "mmio-sram"; 676 reg = <0xf8044000 0x1420>; 677 clocks = <&pmc PMC_TYPE_PERIPHERAL 51>; 678 #address-cells = <1>; 679 #size-cells = <1>; 680 no-memory-wc; 681 ranges = <0 0xf8044000 0x1420>; 682 status = "disabled"; 683 secure-status = "okay"; 684 }; 685 686 reset_controller: rstc@f8048000 { 687 compatible = "atmel,sama5d3-rstc"; 688 reg = <0xf8048000 0x10>; 689 clocks = <&clk32k>; 690 status = "disabled"; 691 secure-status = "okay"; 692 }; 693 694 shutdown_controller: shdwc@f8048010 { 695 compatible = "atmel,sama5d2-shdwc"; 696 reg = <0xf8048010 0x10>; 697 clocks = <&clk32k>; 698 #address-cells = <1>; 699 #size-cells = <0>; 700 atmel,wakeup-rtc-timer; 701 status = "disabled"; 702 secure-status = "okay"; 703 }; 704 705 pit: timer@f8048030 { 706 compatible = "atmel,at91sam9260-pit"; 707 reg = <0xf8048030 0x10>; 708 interrupts = <3 IRQ_TYPE_LEVEL_HIGH 5>; 709 clocks = <&pmc PMC_TYPE_CORE PMC_MCK2>; 710 }; 711 712 watchdog: watchdog@f8048040 { 713 compatible = "atmel,sama5d4-wdt"; 714 reg = <0xf8048040 0x10>; 715 interrupts = <4 IRQ_TYPE_LEVEL_HIGH 7>; 716 clocks = <&clk32k>; 717 status = "disabled"; 718 secure-status = "okay"; 719 }; 720 721 clk32k: sckc@f8048050 { 722 compatible = "atmel,sama5d4-sckc"; 723 reg = <0xf8048050 0x4>; 724 725 clocks = <&slow_xtal>; 726 #clock-cells = <0>; 727 status = "disabled"; 728 secure-status = "okay"; 729 }; 730 731 rtc: rtc@f80480b0 { 732 compatible = "atmel,sama5d2-rtc"; 733 reg = <0xf80480b0 0x30>; 734 interrupts = <74 IRQ_TYPE_LEVEL_HIGH 7>; 735 clocks = <&clk32k>; 736 status = "disabled"; 737 secure-status = "okay"; 738 }; 739 740 sfc: sfc@f804c000 { 741 compatible = "atmel,sama5d2-sfc"; 742 reg = <0xf804c000 0x64>; 743 read-only; 744 status = "disabled"; 745 secure-status = "okay"; 746 #address-cells = <1>; 747 #size-cells = <1>; 748 749 sfc_dr0: cell@20 { 750 reg = <0x20 0x20>; 751 }; 752 753 sfc_dr1: cell@24 { 754 reg = <0x24 0x20>; 755 }; 756 }; 757 758 die_id: die_id { 759 compatible = "optee,nvmem-die-id"; 760 nvmem-cells = <&sfc_dr0>; 761 nvmem-cell-names = "die_id"; 762 }; 763 764 huk: huk { 765 compatible = "optee,nvmem-huk"; 766 nvmem-cells = <&sfc_dr1>; 767 nvmem-cell-names = "hw_unique_key"; 768 }; 769 770 i2s0: i2s@f8050000 { 771 compatible = "atmel,sama5d2-i2s"; 772 reg = <0xf8050000 0x100>; 773 interrupts = <54 IRQ_TYPE_LEVEL_HIGH 7>; 774 dmas = <&dma0 775 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 776 AT91_XDMAC_DT_PERID(31))>, 777 <&dma0 778 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 779 AT91_XDMAC_DT_PERID(32))>; 780 dma-names = "tx", "rx"; 781 clocks = <&pmc PMC_TYPE_PERIPHERAL 54>, <&pmc PMC_TYPE_GCK 54>; 782 clock-names = "pclk", "gclk"; 783 assigned-clocks = <&pmc PMC_TYPE_CORE PMC_I2S0_MUX>; 784 assigned-clock-parents = <&pmc PMC_TYPE_GCK 54>; 785 status = "disabled"; 786 }; 787 788 can0: can@f8054000 { 789 compatible = "bosch,m_can"; 790 reg = <0xf8054000 0x4000>, <0x210000 0x1c00>; 791 reg-names = "m_can", "message_ram"; 792 interrupts = <56 IRQ_TYPE_LEVEL_HIGH 7>, 793 <64 IRQ_TYPE_LEVEL_HIGH 7>; 794 interrupt-names = "int0", "int1"; 795 clocks = <&pmc PMC_TYPE_PERIPHERAL 56>, <&pmc PMC_TYPE_GCK 56>; 796 clock-names = "hclk", "cclk"; 797 assigned-clocks = <&pmc PMC_TYPE_GCK 56>; 798 assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_UTMI>; 799 assigned-clock-rates = <40000000>; 800 bosch,mram-cfg = <0x0 0 0 64 0 0 32 32>; 801 status = "disabled"; 802 }; 803 804 spi1: spi@fc000000 { 805 compatible = "atmel,at91rm9200-spi"; 806 reg = <0xfc000000 0x100>; 807 interrupts = <34 IRQ_TYPE_LEVEL_HIGH 7>; 808 dmas = <&dma0 809 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 810 AT91_XDMAC_DT_PERID(8))>, 811 <&dma0 812 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 813 AT91_XDMAC_DT_PERID(9))>; 814 dma-names = "tx", "rx"; 815 clocks = <&pmc PMC_TYPE_PERIPHERAL 34>; 816 clock-names = "spi_clk"; 817 atmel,fifo-size = <16>; 818 #address-cells = <1>; 819 #size-cells = <0>; 820 status = "disabled"; 821 }; 822 823 uart3: serial@fc008000 { 824 compatible = "atmel,at91sam9260-usart"; 825 reg = <0xfc008000 0x100>; 826 interrupts = <27 IRQ_TYPE_LEVEL_HIGH 7>; 827 dmas = <&dma1 828 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 829 AT91_XDMAC_DT_PERID(41))>, 830 <&dma1 831 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 832 AT91_XDMAC_DT_PERID(42))>; 833 dma-names = "tx", "rx"; 834 clocks = <&pmc PMC_TYPE_PERIPHERAL 27>; 835 clock-names = "usart"; 836 status = "disabled"; 837 }; 838 839 uart4: serial@fc00c000 { 840 compatible = "atmel,at91sam9260-usart"; 841 reg = <0xfc00c000 0x100>; 842 dmas = <&dma0 843 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 844 AT91_XDMAC_DT_PERID(43))>, 845 <&dma0 846 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 847 AT91_XDMAC_DT_PERID(44))>; 848 dma-names = "tx", "rx"; 849 interrupts = <28 IRQ_TYPE_LEVEL_HIGH 7>; 850 clocks = <&pmc PMC_TYPE_PERIPHERAL 28>; 851 clock-names = "usart"; 852 status = "disabled"; 853 }; 854 855 flx2: flexcom@fc010000 { 856 compatible = "atmel,sama5d2-flexcom"; 857 reg = <0xfc010000 0x200>; 858 clocks = <&pmc PMC_TYPE_PERIPHERAL 21>; 859 #address-cells = <1>; 860 #size-cells = <1>; 861 ranges = <0x0 0xfc010000 0x800>; 862 status = "disabled"; 863 864 uart7: serial@200 { 865 compatible = "atmel,at91sam9260-usart"; 866 reg = <0x200 0x200>; 867 interrupts = <21 IRQ_TYPE_LEVEL_HIGH 7>; 868 clocks = <&pmc PMC_TYPE_PERIPHERAL 21>; 869 clock-names = "usart"; 870 dmas = <&dma0 871 (AT91_XDMAC_DT_MEM_IF(0) | 872 AT91_XDMAC_DT_PER_IF(1) | 873 AT91_XDMAC_DT_PERID(15))>, 874 <&dma0 875 (AT91_XDMAC_DT_MEM_IF(0) | 876 AT91_XDMAC_DT_PER_IF(1) | 877 AT91_XDMAC_DT_PERID(16))>; 878 dma-names = "tx", "rx"; 879 atmel,fifo-size = <32>; 880 status = "disabled"; 881 }; 882 883 spi4: spi@400 { 884 compatible = "atmel,at91rm9200-spi"; 885 reg = <0x400 0x200>; 886 interrupts = <21 IRQ_TYPE_LEVEL_HIGH 7>; 887 #address-cells = <1>; 888 #size-cells = <0>; 889 clocks = <&pmc PMC_TYPE_PERIPHERAL 21>; 890 clock-names = "spi_clk"; 891 dmas = <&dma0 892 (AT91_XDMAC_DT_MEM_IF(0) | 893 AT91_XDMAC_DT_PER_IF(1) | 894 AT91_XDMAC_DT_PERID(15))>, 895 <&dma0 896 (AT91_XDMAC_DT_MEM_IF(0) | 897 AT91_XDMAC_DT_PER_IF(1) | 898 AT91_XDMAC_DT_PERID(16))>; 899 dma-names = "tx", "rx"; 900 atmel,fifo-size = <16>; 901 status = "disabled"; 902 }; 903 904 i2c4: i2c@600 { 905 compatible = "atmel,sama5d2-i2c"; 906 reg = <0x600 0x200>; 907 interrupts = <21 IRQ_TYPE_LEVEL_HIGH 7>; 908 #address-cells = <1>; 909 #size-cells = <0>; 910 clocks = <&pmc PMC_TYPE_PERIPHERAL 21>; 911 dmas = <&dma0 912 (AT91_XDMAC_DT_MEM_IF(0) | 913 AT91_XDMAC_DT_PER_IF(1) | 914 AT91_XDMAC_DT_PERID(15))>, 915 <&dma0 916 (AT91_XDMAC_DT_MEM_IF(0) | 917 AT91_XDMAC_DT_PER_IF(1) | 918 AT91_XDMAC_DT_PERID(16))>; 919 dma-names = "tx", "rx"; 920 atmel,fifo-size = <16>; 921 status = "disabled"; 922 }; 923 }; 924 925 flx3: flexcom@fc014000 { 926 compatible = "atmel,sama5d2-flexcom"; 927 reg = <0xfc014000 0x200>; 928 clocks = <&pmc PMC_TYPE_PERIPHERAL 22>; 929 #address-cells = <1>; 930 #size-cells = <1>; 931 ranges = <0x0 0xfc014000 0x800>; 932 status = "disabled"; 933 934 uart8: serial@200 { 935 compatible = "atmel,at91sam9260-usart"; 936 reg = <0x200 0x200>; 937 interrupts = <22 IRQ_TYPE_LEVEL_HIGH 7>; 938 clocks = <&pmc PMC_TYPE_PERIPHERAL 22>; 939 clock-names = "usart"; 940 dmas = <&dma0 941 (AT91_XDMAC_DT_MEM_IF(0) | 942 AT91_XDMAC_DT_PER_IF(1) | 943 AT91_XDMAC_DT_PERID(17))>, 944 <&dma0 945 (AT91_XDMAC_DT_MEM_IF(0) | 946 AT91_XDMAC_DT_PER_IF(1) | 947 AT91_XDMAC_DT_PERID(18))>; 948 dma-names = "tx", "rx"; 949 atmel,fifo-size = <32>; 950 status = "disabled"; 951 }; 952 953 spi5: spi@400 { 954 compatible = "atmel,at91rm9200-spi"; 955 reg = <0x400 0x200>; 956 interrupts = <22 IRQ_TYPE_LEVEL_HIGH 7>; 957 #address-cells = <1>; 958 #size-cells = <0>; 959 clocks = <&pmc PMC_TYPE_PERIPHERAL 22>; 960 clock-names = "spi_clk"; 961 dmas = <&dma0 962 (AT91_XDMAC_DT_MEM_IF(0) | 963 AT91_XDMAC_DT_PER_IF(1) | 964 AT91_XDMAC_DT_PERID(17))>, 965 <&dma0 966 (AT91_XDMAC_DT_MEM_IF(0) | 967 AT91_XDMAC_DT_PER_IF(1) | 968 AT91_XDMAC_DT_PERID(18))>; 969 dma-names = "tx", "rx"; 970 atmel,fifo-size = <16>; 971 status = "disabled"; 972 }; 973 974 i2c5: i2c@600 { 975 compatible = "atmel,sama5d2-i2c"; 976 reg = <0x600 0x200>; 977 interrupts = <22 IRQ_TYPE_LEVEL_HIGH 7>; 978 #address-cells = <1>; 979 #size-cells = <0>; 980 clocks = <&pmc PMC_TYPE_PERIPHERAL 22>; 981 dmas = <&dma0 982 (AT91_XDMAC_DT_MEM_IF(0) | 983 AT91_XDMAC_DT_PER_IF(1) | 984 AT91_XDMAC_DT_PERID(17))>, 985 <&dma0 986 (AT91_XDMAC_DT_MEM_IF(0) | 987 AT91_XDMAC_DT_PER_IF(1) | 988 AT91_XDMAC_DT_PERID(18))>; 989 dma-names = "tx", "rx"; 990 atmel,fifo-size = <16>; 991 status = "disabled"; 992 }; 993 994 }; 995 996 flx4: flexcom@fc018000 { 997 compatible = "atmel,sama5d2-flexcom"; 998 reg = <0xfc018000 0x200>; 999 clocks = <&pmc PMC_TYPE_PERIPHERAL 23>; 1000 #address-cells = <1>; 1001 #size-cells = <1>; 1002 ranges = <0x0 0xfc018000 0x800>; 1003 status = "disabled"; 1004 1005 uart9: serial@200 { 1006 compatible = "atmel,at91sam9260-usart"; 1007 reg = <0x200 0x200>; 1008 interrupts = <23 IRQ_TYPE_LEVEL_HIGH 7>; 1009 clocks = <&pmc PMC_TYPE_PERIPHERAL 23>; 1010 clock-names = "usart"; 1011 dmas = <&dma0 1012 (AT91_XDMAC_DT_MEM_IF(0) | 1013 AT91_XDMAC_DT_PER_IF(1) | 1014 AT91_XDMAC_DT_PERID(19))>, 1015 <&dma0 1016 (AT91_XDMAC_DT_MEM_IF(0) | 1017 AT91_XDMAC_DT_PER_IF(1) | 1018 AT91_XDMAC_DT_PERID(20))>; 1019 dma-names = "tx", "rx"; 1020 atmel,fifo-size = <32>; 1021 status = "disabled"; 1022 }; 1023 1024 spi6: spi@400 { 1025 compatible = "atmel,at91rm9200-spi"; 1026 reg = <0x400 0x200>; 1027 interrupts = <23 IRQ_TYPE_LEVEL_HIGH 7>; 1028 #address-cells = <1>; 1029 #size-cells = <0>; 1030 clocks = <&pmc PMC_TYPE_PERIPHERAL 23>; 1031 clock-names = "spi_clk"; 1032 dmas = <&dma0 1033 (AT91_XDMAC_DT_MEM_IF(0) | 1034 AT91_XDMAC_DT_PER_IF(1) | 1035 AT91_XDMAC_DT_PERID(19))>, 1036 <&dma0 1037 (AT91_XDMAC_DT_MEM_IF(0) | 1038 AT91_XDMAC_DT_PER_IF(1) | 1039 AT91_XDMAC_DT_PERID(20))>; 1040 dma-names = "tx", "rx"; 1041 atmel,fifo-size = <16>; 1042 status = "disabled"; 1043 }; 1044 1045 i2c6: i2c@600 { 1046 compatible = "atmel,sama5d2-i2c"; 1047 reg = <0x600 0x200>; 1048 interrupts = <23 IRQ_TYPE_LEVEL_HIGH 7>; 1049 #address-cells = <1>; 1050 #size-cells = <0>; 1051 clocks = <&pmc PMC_TYPE_PERIPHERAL 23>; 1052 dmas = <&dma0 1053 (AT91_XDMAC_DT_MEM_IF(0) | 1054 AT91_XDMAC_DT_PER_IF(1) | 1055 AT91_XDMAC_DT_PERID(19))>, 1056 <&dma0 1057 (AT91_XDMAC_DT_MEM_IF(0) | 1058 AT91_XDMAC_DT_PER_IF(1) | 1059 AT91_XDMAC_DT_PERID(20))>; 1060 dma-names = "tx", "rx"; 1061 atmel,fifo-size = <16>; 1062 status = "disabled"; 1063 }; 1064 }; 1065 1066 trng@fc01c000 { 1067 compatible = "atmel,at91sam9g45-trng"; 1068 reg = <0xfc01c000 0x100>; 1069 interrupts = <47 IRQ_TYPE_LEVEL_HIGH 0>; 1070 clocks = <&pmc PMC_TYPE_PERIPHERAL 47>; 1071 status = "disabled"; 1072 secure-status = "okay"; 1073 }; 1074 1075 aic: interrupt-controller@fc020000 { 1076 #interrupt-cells = <3>; 1077 compatible = "atmel,sama5d2-aic"; 1078 interrupt-controller; 1079 reg = <0xfc020000 0x200>; 1080 atmel,external-irqs = <49>; 1081 }; 1082 1083 saic: interrupt-controller@f803c000 { 1084 #interrupt-cells = <3>; 1085 compatible = "atmel,sama5d2-saic"; 1086 interrupt-controller; 1087 reg = <0xf803c000 0x200>; 1088 atmel,external-irqs = <49>; 1089 status = "disabled"; 1090 secure-status = "okay"; 1091 }; 1092 1093 i2c1: i2c@fc028000 { 1094 compatible = "atmel,sama5d2-i2c"; 1095 reg = <0xfc028000 0x100>; 1096 interrupts = <30 IRQ_TYPE_LEVEL_HIGH 7>; 1097 dmas = <&dma0 1098 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 1099 AT91_XDMAC_DT_PERID(2))>, 1100 <&dma0 1101 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 1102 AT91_XDMAC_DT_PERID(3))>; 1103 dma-names = "tx", "rx"; 1104 #address-cells = <1>; 1105 #size-cells = <0>; 1106 clocks = <&pmc PMC_TYPE_PERIPHERAL 30>; 1107 atmel,fifo-size = <16>; 1108 status = "disabled"; 1109 }; 1110 1111 adc: adc@fc030000 { 1112 compatible = "atmel,sama5d2-adc"; 1113 reg = <0xfc030000 0x100>; 1114 interrupts = <40 IRQ_TYPE_LEVEL_HIGH 7>; 1115 clocks = <&pmc PMC_TYPE_PERIPHERAL 40>; 1116 clock-names = "adc_clk"; 1117 dmas = <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | AT91_XDMAC_DT_PERID(25))>; 1118 dma-names = "rx"; 1119 atmel,min-sample-rate-hz = <200000>; 1120 atmel,max-sample-rate-hz = <20000000>; 1121 atmel,startup-time-ms = <4>; 1122 atmel,trigger-edge-type = <IRQ_TYPE_EDGE_RISING>; 1123 #io-channel-cells = <1>; 1124 status = "disabled"; 1125 }; 1126 1127 resistive_touch: resistive-touch { 1128 compatible = "resistive-adc-touch"; 1129 io-channels = <&adc AT91_SAMA5D2_ADC_X_CHANNEL>, 1130 <&adc AT91_SAMA5D2_ADC_Y_CHANNEL>, 1131 <&adc AT91_SAMA5D2_ADC_P_CHANNEL>; 1132 io-channel-names = "x", "y", "pressure"; 1133 touchscreen-min-pressure = <50000>; 1134 status = "disabled"; 1135 }; 1136 1137 pioA: pinctrl@fc039000 { 1138 compatible = "atmel,sama5d2-pinctrl"; 1139 reg = <0xfc039000 0x600>; 1140 interrupts = <18 IRQ_TYPE_LEVEL_HIGH 7>, 1141 <68 IRQ_TYPE_LEVEL_HIGH 7>, 1142 <69 IRQ_TYPE_LEVEL_HIGH 7>, 1143 <70 IRQ_TYPE_LEVEL_HIGH 7>; 1144 interrupt-controller; 1145 #interrupt-cells = <2>; 1146 gpio-controller; 1147 #gpio-cells = <2>; 1148 clocks = <&pmc PMC_TYPE_PERIPHERAL 18>; 1149 status = "disabled"; 1150 secure-status = "okay"; 1151 }; 1152 1153 pioBU: secumod@fc040000 { 1154 compatible = "atmel,sama5d2-secumod", "syscon"; 1155 reg = <0xfc040000 0x100>; 1156 1157 gpio-controller; 1158 #gpio-cells = <2>; 1159 status = "disabled"; 1160 secure-status = "okay"; 1161 }; 1162 1163 tdes@fc044000 { 1164 compatible = "atmel,at91sam9g46-tdes"; 1165 reg = <0xfc044000 0x100>; 1166 interrupts = <11 IRQ_TYPE_LEVEL_HIGH 0>; 1167 dmas = <&dma0 1168 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 1169 AT91_XDMAC_DT_PERID(28))>, 1170 <&dma0 1171 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 1172 AT91_XDMAC_DT_PERID(29))>; 1173 dma-names = "tx", "rx"; 1174 clocks = <&pmc PMC_TYPE_PERIPHERAL 11>; 1175 clock-names = "tdes_clk"; 1176 status = "okay"; 1177 }; 1178 1179 classd: classd@fc048000 { 1180 compatible = "atmel,sama5d2-classd"; 1181 reg = <0xfc048000 0x100>; 1182 interrupts = <59 IRQ_TYPE_LEVEL_HIGH 7>; 1183 dmas = <&dma0 1184 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 1185 AT91_XDMAC_DT_PERID(47))>; 1186 dma-names = "tx"; 1187 clocks = <&pmc PMC_TYPE_PERIPHERAL 59>, <&pmc PMC_TYPE_GCK 59>; 1188 clock-names = "pclk", "gclk"; 1189 status = "disabled"; 1190 }; 1191 1192 i2s1: i2s@fc04c000 { 1193 compatible = "atmel,sama5d2-i2s"; 1194 reg = <0xfc04c000 0x100>; 1195 interrupts = <55 IRQ_TYPE_LEVEL_HIGH 7>; 1196 dmas = <&dma0 1197 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 1198 AT91_XDMAC_DT_PERID(33))>, 1199 <&dma0 1200 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 1201 AT91_XDMAC_DT_PERID(34))>; 1202 dma-names = "tx", "rx"; 1203 clocks = <&pmc PMC_TYPE_PERIPHERAL 55>, <&pmc PMC_TYPE_GCK 55>; 1204 clock-names = "pclk", "gclk"; 1205 assigned-clocks = <&pmc PMC_TYPE_CORE PMC_I2S1_MUX>; 1206 assigned-parrents = <&pmc PMC_TYPE_GCK 55>; 1207 status = "disabled"; 1208 }; 1209 1210 can1: can@fc050000 { 1211 compatible = "bosch,m_can"; 1212 reg = <0xfc050000 0x4000>, <0x210000 0x3800>; 1213 reg-names = "m_can", "message_ram"; 1214 interrupts = <57 IRQ_TYPE_LEVEL_HIGH 7>, 1215 <65 IRQ_TYPE_LEVEL_HIGH 7>; 1216 interrupt-names = "int0", "int1"; 1217 clocks = <&pmc PMC_TYPE_PERIPHERAL 57>, <&pmc PMC_TYPE_GCK 57>; 1218 clock-names = "hclk", "cclk"; 1219 assigned-clocks = <&pmc PMC_TYPE_GCK 57>; 1220 assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_UTMI>; 1221 assigned-clock-rates = <40000000>; 1222 bosch,mram-cfg = <0x1c00 0 0 64 0 0 32 32>; 1223 status = "disabled"; 1224 }; 1225 1226 sfrbu: sfr@fc05c000 { 1227 compatible = "atmel,sama5d2-sfrbu", "syscon"; 1228 reg = <0xfc05c000 0x20>; 1229 }; 1230 1231 chipid@fc069000 { 1232 compatible = "atmel,sama5d2-chipid"; 1233 reg = <0xfc069000 0x8>; 1234 }; 1235 }; 1236 }; 1237}; 1238