1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * sama5d2.dtsi - Device Tree Include file for SAMA5D2 family SoC 4 * 5 * Copyright (C) 2015 Atmel, 6 * 2015 Ludovic Desroches <ludovic.desroches@atmel.com> 7 */ 8 9#include <dt-bindings/dma/at91.h> 10#include <dt-bindings/interrupt-controller/irq.h> 11#include <dt-bindings/clock/at91.h> 12#include <dt-bindings/iio/adc/at91-sama5d2_adc.h> 13 14/ { 15 #address-cells = <1>; 16 #size-cells = <1>; 17 model = "Atmel SAMA5D2 family SoC"; 18 compatible = "atmel,sama5d2"; 19 interrupt-parent = <&aic>; 20 21 aliases { 22 serial0 = &uart1; 23 serial1 = &uart3; 24 }; 25 26 cpus { 27 #address-cells = <1>; 28 #size-cells = <0>; 29 30 cpu@0 { 31 device_type = "cpu"; 32 compatible = "arm,cortex-a5"; 33 reg = <0>; 34 next-level-cache = <&L2>; 35 clocks = <&pmc PMC_TYPE_CORE PMC_MCK_PRES>; 36 clock-names = "cpu"; 37 }; 38 }; 39 40 pmu { 41 compatible = "arm,cortex-a5-pmu"; 42 interrupts = <2 IRQ_TYPE_LEVEL_HIGH 0>; 43 }; 44 45 etb@740000 { 46 compatible = "arm,coresight-etb10", "arm,primecell"; 47 reg = <0x740000 0x1000>; 48 49 clocks = <&pmc PMC_TYPE_CORE PMC_MCK>; 50 clock-names = "apb_pclk"; 51 52 in-ports { 53 port { 54 etb_in: endpoint { 55 remote-endpoint = <&etm_out>; 56 }; 57 }; 58 }; 59 }; 60 61 etm@73c000 { 62 compatible = "arm,coresight-etm3x", "arm,primecell"; 63 reg = <0x73c000 0x1000>; 64 65 clocks = <&pmc PMC_TYPE_CORE PMC_MCK>; 66 clock-names = "apb_pclk"; 67 68 out-ports { 69 port { 70 etm_out: endpoint { 71 remote-endpoint = <&etb_in>; 72 }; 73 }; 74 }; 75 }; 76 77 memory@20000000 { 78 device_type = "memory"; 79 reg = <0x20000000 0x20000000>; 80 }; 81 82 clocks { 83 slow_xtal: slow_xtal { 84 compatible = "fixed-clock"; 85 #clock-cells = <0>; 86 clock-frequency = <0>; 87 }; 88 89 main_xtal: main_xtal { 90 compatible = "fixed-clock"; 91 #clock-cells = <0>; 92 clock-frequency = <0>; 93 }; 94 }; 95 96 ns_sram: sram@200000 { 97 compatible = "atmel,sama5d2-sram", "mmio-sram"; 98 reg = <0x00200000 0x20000>; 99 #address-cells = <1>; 100 #size-cells = <1>; 101 ranges = <0 0x00200000 0x20000>; 102 status = "disabled"; 103 secure-status = "okay"; 104 }; 105 106 ahb { 107 compatible = "simple-bus"; 108 #address-cells = <1>; 109 #size-cells = <1>; 110 ranges; 111 112 nfc_sram: sram@100000 { 113 compatible = "mmio-sram"; 114 no-memory-wc; 115 reg = <0x00100000 0x2400>; 116 #address-cells = <1>; 117 #size-cells = <1>; 118 ranges = <0 0x00100000 0x2400>; 119 120 }; 121 122 usb0: gadget@300000 { 123 compatible = "atmel,sama5d3-udc"; 124 reg = <0x00300000 0x100000 125 0xfc02c000 0x400>; 126 interrupts = <42 IRQ_TYPE_LEVEL_HIGH 2>; 127 clocks = <&pmc PMC_TYPE_PERIPHERAL 42>, <&pmc PMC_TYPE_CORE PMC_UTMI>; 128 clock-names = "pclk", "hclk"; 129 assigned-clocks = <&pmc PMC_TYPE_CORE PMC_USBCK>; 130 assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_UTMI>; 131 assigned-clock-rates = <48000000>; 132 status = "disabled"; 133 }; 134 135 usb1: ohci@400000 { 136 compatible = "atmel,at91rm9200-ohci", "usb-ohci"; 137 reg = <0x00400000 0x100000>; 138 interrupts = <41 IRQ_TYPE_LEVEL_HIGH 2>; 139 clocks = <&pmc PMC_TYPE_PERIPHERAL 41>, <&pmc PMC_TYPE_PERIPHERAL 41>, <&pmc PMC_TYPE_SYSTEM 6>; 140 clock-names = "ohci_clk", "hclk", "uhpck"; 141 assigned-clocks = <&pmc PMC_TYPE_CORE PMC_USBCK>; 142 assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_UTMI>; 143 assigned-clock-rates = <48000000>; 144 status = "disabled"; 145 }; 146 147 usb2: ehci@500000 { 148 compatible = "atmel,at91sam9g45-ehci", "usb-ehci"; 149 reg = <0x00500000 0x100000>; 150 interrupts = <41 IRQ_TYPE_LEVEL_HIGH 2>; 151 clocks = <&pmc PMC_TYPE_CORE PMC_UTMI>, <&pmc PMC_TYPE_PERIPHERAL 41>; 152 clock-names = "usb_clk", "ehci_clk"; 153 assigned-clocks = <&pmc PMC_TYPE_CORE PMC_USBCK>; 154 assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_UTMI>; 155 assigned-clock-rates = <48000000>; 156 status = "disabled"; 157 }; 158 159 L2: cache-controller@a00000 { 160 compatible = "arm,pl310-cache"; 161 reg = <0x00a00000 0x1000>; 162 interrupts = <63 IRQ_TYPE_LEVEL_HIGH 4>; 163 cache-unified; 164 cache-level = <2>; 165 }; 166 167 ebi: ebi@10000000 { 168 compatible = "atmel,sama5d3-ebi"; 169 #address-cells = <2>; 170 #size-cells = <1>; 171 atmel,smc = <&hsmc>; 172 reg = <0x10000000 0x10000000 173 0x60000000 0x30000000>; 174 ranges = <0x0 0x0 0x10000000 0x10000000 175 0x1 0x0 0x60000000 0x10000000 176 0x2 0x0 0x70000000 0x10000000 177 0x3 0x0 0x80000000 0x10000000>; 178 clocks = <&pmc PMC_TYPE_CORE PMC_MCK2>; 179 status = "disabled"; 180 181 nand_controller: nand-controller { 182 compatible = "atmel,sama5d3-nand-controller"; 183 atmel,nfc-sram = <&nfc_sram>; 184 atmel,nfc-io = <&nfc_io>; 185 ecc-engine = <&pmecc>; 186 #address-cells = <2>; 187 #size-cells = <1>; 188 ranges; 189 status = "disabled"; 190 }; 191 }; 192 193 sdmmc0: sdio-host@a0000000 { 194 compatible = "atmel,sama5d2-sdhci"; 195 reg = <0xa0000000 0x300>; 196 interrupts = <31 IRQ_TYPE_LEVEL_HIGH 0>; 197 clocks = <&pmc PMC_TYPE_PERIPHERAL 31>, <&pmc PMC_TYPE_GCK 31>, <&pmc PMC_TYPE_CORE PMC_MAIN>; 198 clock-names = "hclock", "multclk", "baseclk"; 199 assigned-clocks = <&pmc PMC_TYPE_GCK 31>; 200 assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_UTMI>; 201 assigned-clock-rates = <480000000>; 202 status = "disabled"; 203 }; 204 205 sdmmc1: sdio-host@b0000000 { 206 compatible = "atmel,sama5d2-sdhci"; 207 reg = <0xb0000000 0x300>; 208 interrupts = <32 IRQ_TYPE_LEVEL_HIGH 0>; 209 clocks = <&pmc PMC_TYPE_PERIPHERAL 32>, <&pmc PMC_TYPE_GCK 32>, <&pmc PMC_TYPE_CORE PMC_MAIN>; 210 clock-names = "hclock", "multclk", "baseclk"; 211 assigned-clocks = <&pmc PMC_TYPE_GCK 32>; 212 assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_UTMI>; 213 assigned-clock-rates = <480000000>; 214 status = "disabled"; 215 }; 216 217 nfc_io: nfc-io@c0000000 { 218 compatible = "atmel,sama5d3-nfc-io", "syscon"; 219 reg = <0xc0000000 0x8000000>; 220 }; 221 222 apb { 223 compatible = "simple-bus"; 224 #address-cells = <1>; 225 #size-cells = <1>; 226 ranges; 227 228 hlcdc: hlcdc@f0000000 { 229 compatible = "atmel,sama5d2-hlcdc"; 230 reg = <0xf0000000 0x2000>; 231 interrupts = <45 IRQ_TYPE_LEVEL_HIGH 0>; 232 clocks = <&pmc PMC_TYPE_PERIPHERAL 45>, <&pmc PMC_TYPE_SYSTEM 3>, <&clk32k>; 233 clock-names = "periph_clk","sys_clk", "slow_clk"; 234 status = "disabled"; 235 236 hlcdc-display-controller { 237 compatible = "atmel,hlcdc-display-controller"; 238 #address-cells = <1>; 239 #size-cells = <0>; 240 241 port@0 { 242 #address-cells = <1>; 243 #size-cells = <0>; 244 reg = <0>; 245 }; 246 }; 247 248 hlcdc_pwm: hlcdc-pwm { 249 compatible = "atmel,hlcdc-pwm"; 250 #pwm-cells = <3>; 251 }; 252 }; 253 254 isc: isc@f0008000 { 255 compatible = "atmel,sama5d2-isc"; 256 reg = <0xf0008000 0x4000>; 257 interrupts = <46 IRQ_TYPE_LEVEL_HIGH 5>; 258 clocks = <&pmc PMC_TYPE_PERIPHERAL 46>, <&pmc PMC_TYPE_SYSTEM 18>, <&pmc PMC_TYPE_GCK 46>; 259 clock-names = "hclock", "iscck", "gck"; 260 #clock-cells = <0>; 261 clock-output-names = "isc-mck"; 262 status = "disabled"; 263 }; 264 265 ramc0: ramc@f000c000 { 266 compatible = "atmel,sama5d3-ddramc"; 267 reg = <0xf000c000 0x200>; 268 clocks = <&pmc PMC_TYPE_SYSTEM 2>, <&pmc PMC_TYPE_PERIPHERAL 13>; 269 clock-names = "ddrck", "mpddr"; 270 }; 271 272 dma0: dma-controller@f0010000 { 273 compatible = "atmel,sama5d4-dma"; 274 reg = <0xf0010000 0x1000>; 275 interrupts = <6 IRQ_TYPE_LEVEL_HIGH 0>; 276 #dma-cells = <1>; 277 clocks = <&pmc PMC_TYPE_PERIPHERAL 6>; 278 clock-names = "dma_clk"; 279 }; 280 281 /* Place dma1 here despite its address */ 282 dma1: dma-controller@f0004000 { 283 compatible = "atmel,sama5d4-dma"; 284 reg = <0xf0004000 0x1000>; 285 interrupts = <7 IRQ_TYPE_LEVEL_HIGH 0>; 286 #dma-cells = <1>; 287 clocks = <&pmc PMC_TYPE_PERIPHERAL 7>; 288 clock-names = "dma_clk"; 289 }; 290 291 pmc: pmc@f0014000 { 292 compatible = "atmel,sama5d2-pmc", "syscon"; 293 reg = <0xf0014000 0x160>; 294 interrupts = <74 IRQ_TYPE_LEVEL_HIGH 7>; 295 #clock-cells = <2>; 296 clocks = <&clk32k>, <&main_xtal>; 297 clock-names = "slow_clk", "main_xtal"; 298 status = "disabled"; 299 secure-status = "okay"; 300 }; 301 302 qspi0: spi@f0020000 { 303 compatible = "atmel,sama5d2-qspi"; 304 reg = <0xf0020000 0x100>, <0xd0000000 0x08000000>; 305 reg-names = "qspi_base", "qspi_mmap"; 306 interrupts = <52 IRQ_TYPE_LEVEL_HIGH 7>; 307 clocks = <&pmc PMC_TYPE_PERIPHERAL 52>; 308 #address-cells = <1>; 309 #size-cells = <0>; 310 status = "disabled"; 311 }; 312 313 qspi1: spi@f0024000 { 314 compatible = "atmel,sama5d2-qspi"; 315 reg = <0xf0024000 0x100>, <0xd8000000 0x08000000>; 316 reg-names = "qspi_base", "qspi_mmap"; 317 interrupts = <53 IRQ_TYPE_LEVEL_HIGH 7>; 318 clocks = <&pmc PMC_TYPE_PERIPHERAL 53>; 319 #address-cells = <1>; 320 #size-cells = <0>; 321 status = "disabled"; 322 }; 323 324 sha@f0028000 { 325 compatible = "atmel,at91sam9g46-sha"; 326 reg = <0xf0028000 0x100>; 327 interrupts = <12 IRQ_TYPE_LEVEL_HIGH 0>; 328 dmas = <&dma0 329 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 330 AT91_XDMAC_DT_PERID(30))>; 331 dma-names = "tx"; 332 clocks = <&pmc PMC_TYPE_PERIPHERAL 12>; 333 clock-names = "sha_clk"; 334 status = "okay"; 335 }; 336 337 aes@f002c000 { 338 compatible = "atmel,at91sam9g46-aes"; 339 reg = <0xf002c000 0x100>; 340 interrupts = <9 IRQ_TYPE_LEVEL_HIGH 0>; 341 dmas = <&dma0 342 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 343 AT91_XDMAC_DT_PERID(26))>, 344 <&dma0 345 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 346 AT91_XDMAC_DT_PERID(27))>; 347 dma-names = "tx", "rx"; 348 clocks = <&pmc PMC_TYPE_PERIPHERAL 9>; 349 clock-names = "aes_clk"; 350 status = "okay"; 351 }; 352 353 spi0: spi@f8000000 { 354 compatible = "atmel,at91rm9200-spi"; 355 reg = <0xf8000000 0x100>; 356 interrupts = <33 IRQ_TYPE_LEVEL_HIGH 7>; 357 dmas = <&dma0 358 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 359 AT91_XDMAC_DT_PERID(6))>, 360 <&dma0 361 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 362 AT91_XDMAC_DT_PERID(7))>; 363 dma-names = "tx", "rx"; 364 clocks = <&pmc PMC_TYPE_PERIPHERAL 33>; 365 clock-names = "spi_clk"; 366 atmel,fifo-size = <16>; 367 #address-cells = <1>; 368 #size-cells = <0>; 369 status = "disabled"; 370 }; 371 372 ssc0: ssc@f8004000 { 373 compatible = "atmel,at91sam9g45-ssc"; 374 reg = <0xf8004000 0x4000>; 375 interrupts = <43 IRQ_TYPE_LEVEL_HIGH 4>; 376 dmas = <&dma0 377 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 378 AT91_XDMAC_DT_PERID(21))>, 379 <&dma0 380 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 381 AT91_XDMAC_DT_PERID(22))>; 382 dma-names = "tx", "rx"; 383 clocks = <&pmc PMC_TYPE_PERIPHERAL 43>; 384 clock-names = "pclk"; 385 status = "disabled"; 386 }; 387 388 macb0: ethernet@f8008000 { 389 compatible = "atmel,sama5d2-gem"; 390 reg = <0xf8008000 0x1000>; 391 interrupts = <5 IRQ_TYPE_LEVEL_HIGH 3 /* Queue 0 */ 392 66 IRQ_TYPE_LEVEL_HIGH 3 /* Queue 1 */ 393 67 IRQ_TYPE_LEVEL_HIGH 3>; /* Queue 2 */ 394 #address-cells = <1>; 395 #size-cells = <0>; 396 clocks = <&pmc PMC_TYPE_PERIPHERAL 5>, <&pmc PMC_TYPE_PERIPHERAL 5>; 397 clock-names = "hclk", "pclk"; 398 status = "disabled"; 399 }; 400 401 tcb0: timer@f800c000 { 402 compatible = "atmel,sama5d2-tcb", "simple-mfd", "syscon"; 403 #address-cells = <1>; 404 #size-cells = <0>; 405 reg = <0xf800c000 0x100>; 406 interrupts = <35 IRQ_TYPE_LEVEL_HIGH 0>; 407 clocks = <&pmc PMC_TYPE_PERIPHERAL 35>, <&pmc PMC_TYPE_GCK 35>, <&clk32k>; 408 clock-names = "t0_clk", "gclk", "slow_clk"; 409 }; 410 411 tcb1: timer@f8010000 { 412 compatible = "atmel,sama5d2-tcb", "simple-mfd", "syscon"; 413 #address-cells = <1>; 414 #size-cells = <0>; 415 reg = <0xf8010000 0x100>; 416 interrupts = <36 IRQ_TYPE_LEVEL_HIGH 0>; 417 clocks = <&pmc PMC_TYPE_PERIPHERAL 36>, <&pmc PMC_TYPE_GCK 36>, <&clk32k>; 418 clock-names = "t0_clk", "gclk", "slow_clk"; 419 status = "disabled"; 420 secure-status = "okay"; 421 }; 422 423 hsmc: hsmc@f8014000 { 424 compatible = "atmel,sama5d2-smc", "syscon", "simple-mfd"; 425 reg = <0xf8014000 0x1000>; 426 interrupts = <17 IRQ_TYPE_LEVEL_HIGH 6>; 427 clocks = <&pmc PMC_TYPE_PERIPHERAL 17>; 428 #address-cells = <1>; 429 #size-cells = <1>; 430 ranges; 431 432 pmecc: ecc-engine@f8014070 { 433 compatible = "atmel,sama5d2-pmecc"; 434 reg = <0xf8014070 0x490>, 435 <0xf8014500 0x100>; 436 }; 437 }; 438 439 pdmic: pdmic@f8018000 { 440 compatible = "atmel,sama5d2-pdmic"; 441 reg = <0xf8018000 0x124>; 442 interrupts = <48 IRQ_TYPE_LEVEL_HIGH 7>; 443 dmas = <&dma0 444 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) 445 | AT91_XDMAC_DT_PERID(50))>; 446 dma-names = "rx"; 447 clocks = <&pmc PMC_TYPE_PERIPHERAL 48>, <&pmc PMC_TYPE_GCK 48>; 448 clock-names = "pclk", "gclk"; 449 status = "disabled"; 450 }; 451 452 uart0: serial@f801c000 { 453 compatible = "atmel,at91sam9260-usart"; 454 reg = <0xf801c000 0x100>; 455 interrupts = <24 IRQ_TYPE_LEVEL_HIGH 7>; 456 dmas = <&dma0 457 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 458 AT91_XDMAC_DT_PERID(35))>, 459 <&dma0 460 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 461 AT91_XDMAC_DT_PERID(36))>; 462 dma-names = "tx", "rx"; 463 clocks = <&pmc PMC_TYPE_PERIPHERAL 24>; 464 clock-names = "usart"; 465 status = "disabled"; 466 }; 467 468 uart1: serial@f8020000 { 469 compatible = "atmel,at91sam9260-usart"; 470 reg = <0xf8020000 0x100>; 471 interrupts = <25 IRQ_TYPE_LEVEL_HIGH 7>; 472 dmas = <&dma0 473 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 474 AT91_XDMAC_DT_PERID(37))>, 475 <&dma0 476 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 477 AT91_XDMAC_DT_PERID(38))>; 478 dma-names = "tx", "rx"; 479 clocks = <&pmc PMC_TYPE_PERIPHERAL 25>; 480 clock-names = "usart"; 481 status = "disabled"; 482 }; 483 484 uart2: serial@f8024000 { 485 compatible = "atmel,at91sam9260-usart"; 486 reg = <0xf8024000 0x100>; 487 interrupts = <26 IRQ_TYPE_LEVEL_HIGH 7>; 488 dmas = <&dma0 489 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 490 AT91_XDMAC_DT_PERID(39))>, 491 <&dma0 492 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 493 AT91_XDMAC_DT_PERID(40))>; 494 dma-names = "tx", "rx"; 495 clocks = <&pmc PMC_TYPE_PERIPHERAL 26>; 496 clock-names = "usart"; 497 status = "disabled"; 498 }; 499 500 i2c0: i2c@f8028000 { 501 compatible = "atmel,sama5d2-i2c"; 502 reg = <0xf8028000 0x100>; 503 interrupts = <29 IRQ_TYPE_LEVEL_HIGH 7>; 504 dmas = <&dma0 505 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 506 AT91_XDMAC_DT_PERID(0))>, 507 <&dma0 508 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 509 AT91_XDMAC_DT_PERID(1))>; 510 dma-names = "tx", "rx"; 511 #address-cells = <1>; 512 #size-cells = <0>; 513 clocks = <&pmc PMC_TYPE_PERIPHERAL 29>; 514 atmel,fifo-size = <16>; 515 status = "disabled"; 516 }; 517 518 pwm0: pwm@f802c000 { 519 compatible = "atmel,sama5d2-pwm"; 520 reg = <0xf802c000 0x4000>; 521 interrupts = <38 IRQ_TYPE_LEVEL_HIGH 7>; 522 #pwm-cells = <3>; 523 clocks = <&pmc PMC_TYPE_PERIPHERAL 38>; 524 status = "disabled"; 525 }; 526 527 sfr: sfr@f8030000 { 528 compatible = "atmel,sama5d2-sfr", "syscon"; 529 reg = <0xf8030000 0x98>; 530 status = "disabled"; 531 secure-status = "okay"; 532 }; 533 534 flx0: flexcom@f8034000 { 535 compatible = "atmel,sama5d2-flexcom"; 536 reg = <0xf8034000 0x200>; 537 clocks = <&pmc PMC_TYPE_PERIPHERAL 19>; 538 #address-cells = <1>; 539 #size-cells = <1>; 540 ranges = <0x0 0xf8034000 0x800>; 541 status = "disabled"; 542 543 uart5: serial@200 { 544 compatible = "atmel,at91sam9260-usart"; 545 reg = <0x200 0x200>; 546 interrupts = <19 IRQ_TYPE_LEVEL_HIGH 7>; 547 clocks = <&pmc PMC_TYPE_PERIPHERAL 19>; 548 clock-names = "usart"; 549 dmas = <&dma0 550 (AT91_XDMAC_DT_MEM_IF(0) | 551 AT91_XDMAC_DT_PER_IF(1) | 552 AT91_XDMAC_DT_PERID(11))>, 553 <&dma0 554 (AT91_XDMAC_DT_MEM_IF(0) | 555 AT91_XDMAC_DT_PER_IF(1) | 556 AT91_XDMAC_DT_PERID(12))>; 557 dma-names = "tx", "rx"; 558 atmel,fifo-size = <32>; 559 status = "disabled"; 560 }; 561 562 spi2: spi@400 { 563 compatible = "atmel,at91rm9200-spi"; 564 reg = <0x400 0x200>; 565 interrupts = <19 IRQ_TYPE_LEVEL_HIGH 7>; 566 #address-cells = <1>; 567 #size-cells = <0>; 568 clocks = <&pmc PMC_TYPE_PERIPHERAL 19>; 569 clock-names = "spi_clk"; 570 dmas = <&dma0 571 (AT91_XDMAC_DT_MEM_IF(0) | 572 AT91_XDMAC_DT_PER_IF(1) | 573 AT91_XDMAC_DT_PERID(11))>, 574 <&dma0 575 (AT91_XDMAC_DT_MEM_IF(0) | 576 AT91_XDMAC_DT_PER_IF(1) | 577 AT91_XDMAC_DT_PERID(12))>; 578 dma-names = "tx", "rx"; 579 atmel,fifo-size = <16>; 580 status = "disabled"; 581 }; 582 583 i2c2: i2c@600 { 584 compatible = "atmel,sama5d2-i2c"; 585 reg = <0x600 0x200>; 586 interrupts = <19 IRQ_TYPE_LEVEL_HIGH 7>; 587 #address-cells = <1>; 588 #size-cells = <0>; 589 clocks = <&pmc PMC_TYPE_PERIPHERAL 19>; 590 dmas = <&dma0 591 (AT91_XDMAC_DT_MEM_IF(0) | 592 AT91_XDMAC_DT_PER_IF(1) | 593 AT91_XDMAC_DT_PERID(11))>, 594 <&dma0 595 (AT91_XDMAC_DT_MEM_IF(0) | 596 AT91_XDMAC_DT_PER_IF(1) | 597 AT91_XDMAC_DT_PERID(12))>; 598 dma-names = "tx", "rx"; 599 atmel,fifo-size = <16>; 600 status = "disabled"; 601 }; 602 }; 603 604 flx1: flexcom@f8038000 { 605 compatible = "atmel,sama5d2-flexcom"; 606 reg = <0xf8038000 0x200>; 607 clocks = <&pmc PMC_TYPE_PERIPHERAL 20>; 608 #address-cells = <1>; 609 #size-cells = <1>; 610 ranges = <0x0 0xf8038000 0x800>; 611 status = "disabled"; 612 613 uart6: serial@200 { 614 compatible = "atmel,at91sam9260-usart"; 615 reg = <0x200 0x200>; 616 interrupts = <20 IRQ_TYPE_LEVEL_HIGH 7>; 617 clocks = <&pmc PMC_TYPE_PERIPHERAL 20>; 618 clock-names = "usart"; 619 dmas = <&dma0 620 (AT91_XDMAC_DT_MEM_IF(0) | 621 AT91_XDMAC_DT_PER_IF(1) | 622 AT91_XDMAC_DT_PERID(13))>, 623 <&dma0 624 (AT91_XDMAC_DT_MEM_IF(0) | 625 AT91_XDMAC_DT_PER_IF(1) | 626 AT91_XDMAC_DT_PERID(14))>; 627 dma-names = "tx", "rx"; 628 atmel,fifo-size = <32>; 629 status = "disabled"; 630 }; 631 632 spi3: spi@400 { 633 compatible = "atmel,at91rm9200-spi"; 634 reg = <0x400 0x200>; 635 interrupts = <20 IRQ_TYPE_LEVEL_HIGH 7>; 636 #address-cells = <1>; 637 #size-cells = <0>; 638 clocks = <&pmc PMC_TYPE_PERIPHERAL 20>; 639 clock-names = "spi_clk"; 640 dmas = <&dma0 641 (AT91_XDMAC_DT_MEM_IF(0) | 642 AT91_XDMAC_DT_PER_IF(1) | 643 AT91_XDMAC_DT_PERID(13))>, 644 <&dma0 645 (AT91_XDMAC_DT_MEM_IF(0) | 646 AT91_XDMAC_DT_PER_IF(1) | 647 AT91_XDMAC_DT_PERID(14))>; 648 dma-names = "tx", "rx"; 649 atmel,fifo-size = <16>; 650 status = "disabled"; 651 }; 652 653 i2c3: i2c@600 { 654 compatible = "atmel,sama5d2-i2c"; 655 reg = <0x600 0x200>; 656 interrupts = <20 IRQ_TYPE_LEVEL_HIGH 7>; 657 #address-cells = <1>; 658 #size-cells = <0>; 659 clocks = <&pmc PMC_TYPE_PERIPHERAL 20>; 660 dmas = <&dma0 661 (AT91_XDMAC_DT_MEM_IF(0) | 662 AT91_XDMAC_DT_PER_IF(1) | 663 AT91_XDMAC_DT_PERID(13))>, 664 <&dma0 665 (AT91_XDMAC_DT_MEM_IF(0) | 666 AT91_XDMAC_DT_PER_IF(1) | 667 AT91_XDMAC_DT_PERID(14))>; 668 dma-names = "tx", "rx"; 669 atmel,fifo-size = <16>; 670 status = "disabled"; 671 }; 672 }; 673 674 securam: sram@f8044000 { 675 compatible = "atmel,sama5d2-securam", "mmio-sram"; 676 reg = <0xf8044000 0x1420>; 677 clocks = <&pmc PMC_TYPE_PERIPHERAL 51>; 678 #address-cells = <1>; 679 #size-cells = <1>; 680 no-memory-wc; 681 ranges = <0 0xf8044000 0x1420>; 682 status = "disabled"; 683 secure-status = "okay"; 684 }; 685 686 reset_controller: rstc@f8048000 { 687 compatible = "atmel,sama5d3-rstc"; 688 reg = <0xf8048000 0x10>; 689 clocks = <&clk32k>; 690 status = "disabled"; 691 secure-status = "okay"; 692 }; 693 694 shutdown_controller: shdwc@f8048010 { 695 compatible = "atmel,sama5d2-shdwc"; 696 reg = <0xf8048010 0x10>; 697 clocks = <&clk32k>; 698 #address-cells = <1>; 699 #size-cells = <0>; 700 atmel,wakeup-rtc-timer; 701 status = "disabled"; 702 secure-status = "okay"; 703 }; 704 705 pit: timer@f8048030 { 706 compatible = "atmel,at91sam9260-pit"; 707 reg = <0xf8048030 0x10>; 708 interrupts = <3 IRQ_TYPE_LEVEL_HIGH 5>; 709 clocks = <&pmc PMC_TYPE_CORE PMC_MCK2>; 710 }; 711 712 watchdog: watchdog@f8048040 { 713 compatible = "atmel,sama5d4-wdt"; 714 reg = <0xf8048040 0x10>; 715 interrupts = <4 IRQ_TYPE_LEVEL_HIGH 7>; 716 clocks = <&clk32k>; 717 status = "disabled"; 718 secure-status = "okay"; 719 }; 720 721 clk32k: sckc@f8048050 { 722 compatible = "atmel,sama5d4-sckc"; 723 reg = <0xf8048050 0x4>; 724 725 clocks = <&slow_xtal>; 726 #clock-cells = <0>; 727 status = "disabled"; 728 secure-status = "okay"; 729 }; 730 731 rtc: rtc@f80480b0 { 732 compatible = "atmel,sama5d2-rtc"; 733 reg = <0xf80480b0 0x30>; 734 interrupts = <74 IRQ_TYPE_LEVEL_HIGH 7>; 735 clocks = <&clk32k>; 736 status = "disabled"; 737 secure-status = "okay"; 738 }; 739 740 i2s0: i2s@f8050000 { 741 compatible = "atmel,sama5d2-i2s"; 742 reg = <0xf8050000 0x100>; 743 interrupts = <54 IRQ_TYPE_LEVEL_HIGH 7>; 744 dmas = <&dma0 745 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 746 AT91_XDMAC_DT_PERID(31))>, 747 <&dma0 748 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 749 AT91_XDMAC_DT_PERID(32))>; 750 dma-names = "tx", "rx"; 751 clocks = <&pmc PMC_TYPE_PERIPHERAL 54>, <&pmc PMC_TYPE_GCK 54>; 752 clock-names = "pclk", "gclk"; 753 assigned-clocks = <&pmc PMC_TYPE_CORE PMC_I2S0_MUX>; 754 assigned-clock-parents = <&pmc PMC_TYPE_GCK 54>; 755 status = "disabled"; 756 }; 757 758 can0: can@f8054000 { 759 compatible = "bosch,m_can"; 760 reg = <0xf8054000 0x4000>, <0x210000 0x1c00>; 761 reg-names = "m_can", "message_ram"; 762 interrupts = <56 IRQ_TYPE_LEVEL_HIGH 7>, 763 <64 IRQ_TYPE_LEVEL_HIGH 7>; 764 interrupt-names = "int0", "int1"; 765 clocks = <&pmc PMC_TYPE_PERIPHERAL 56>, <&pmc PMC_TYPE_GCK 56>; 766 clock-names = "hclk", "cclk"; 767 assigned-clocks = <&pmc PMC_TYPE_GCK 56>; 768 assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_UTMI>; 769 assigned-clock-rates = <40000000>; 770 bosch,mram-cfg = <0x0 0 0 64 0 0 32 32>; 771 status = "disabled"; 772 }; 773 774 spi1: spi@fc000000 { 775 compatible = "atmel,at91rm9200-spi"; 776 reg = <0xfc000000 0x100>; 777 interrupts = <34 IRQ_TYPE_LEVEL_HIGH 7>; 778 dmas = <&dma0 779 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 780 AT91_XDMAC_DT_PERID(8))>, 781 <&dma0 782 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 783 AT91_XDMAC_DT_PERID(9))>; 784 dma-names = "tx", "rx"; 785 clocks = <&pmc PMC_TYPE_PERIPHERAL 34>; 786 clock-names = "spi_clk"; 787 atmel,fifo-size = <16>; 788 #address-cells = <1>; 789 #size-cells = <0>; 790 status = "disabled"; 791 }; 792 793 uart3: serial@fc008000 { 794 compatible = "atmel,at91sam9260-usart"; 795 reg = <0xfc008000 0x100>; 796 interrupts = <27 IRQ_TYPE_LEVEL_HIGH 7>; 797 dmas = <&dma1 798 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 799 AT91_XDMAC_DT_PERID(41))>, 800 <&dma1 801 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 802 AT91_XDMAC_DT_PERID(42))>; 803 dma-names = "tx", "rx"; 804 clocks = <&pmc PMC_TYPE_PERIPHERAL 27>; 805 clock-names = "usart"; 806 status = "disabled"; 807 }; 808 809 uart4: serial@fc00c000 { 810 compatible = "atmel,at91sam9260-usart"; 811 reg = <0xfc00c000 0x100>; 812 dmas = <&dma0 813 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 814 AT91_XDMAC_DT_PERID(43))>, 815 <&dma0 816 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 817 AT91_XDMAC_DT_PERID(44))>; 818 dma-names = "tx", "rx"; 819 interrupts = <28 IRQ_TYPE_LEVEL_HIGH 7>; 820 clocks = <&pmc PMC_TYPE_PERIPHERAL 28>; 821 clock-names = "usart"; 822 status = "disabled"; 823 }; 824 825 flx2: flexcom@fc010000 { 826 compatible = "atmel,sama5d2-flexcom"; 827 reg = <0xfc010000 0x200>; 828 clocks = <&pmc PMC_TYPE_PERIPHERAL 21>; 829 #address-cells = <1>; 830 #size-cells = <1>; 831 ranges = <0x0 0xfc010000 0x800>; 832 status = "disabled"; 833 834 uart7: serial@200 { 835 compatible = "atmel,at91sam9260-usart"; 836 reg = <0x200 0x200>; 837 interrupts = <21 IRQ_TYPE_LEVEL_HIGH 7>; 838 clocks = <&pmc PMC_TYPE_PERIPHERAL 21>; 839 clock-names = "usart"; 840 dmas = <&dma0 841 (AT91_XDMAC_DT_MEM_IF(0) | 842 AT91_XDMAC_DT_PER_IF(1) | 843 AT91_XDMAC_DT_PERID(15))>, 844 <&dma0 845 (AT91_XDMAC_DT_MEM_IF(0) | 846 AT91_XDMAC_DT_PER_IF(1) | 847 AT91_XDMAC_DT_PERID(16))>; 848 dma-names = "tx", "rx"; 849 atmel,fifo-size = <32>; 850 status = "disabled"; 851 }; 852 853 spi4: spi@400 { 854 compatible = "atmel,at91rm9200-spi"; 855 reg = <0x400 0x200>; 856 interrupts = <21 IRQ_TYPE_LEVEL_HIGH 7>; 857 #address-cells = <1>; 858 #size-cells = <0>; 859 clocks = <&pmc PMC_TYPE_PERIPHERAL 21>; 860 clock-names = "spi_clk"; 861 dmas = <&dma0 862 (AT91_XDMAC_DT_MEM_IF(0) | 863 AT91_XDMAC_DT_PER_IF(1) | 864 AT91_XDMAC_DT_PERID(15))>, 865 <&dma0 866 (AT91_XDMAC_DT_MEM_IF(0) | 867 AT91_XDMAC_DT_PER_IF(1) | 868 AT91_XDMAC_DT_PERID(16))>; 869 dma-names = "tx", "rx"; 870 atmel,fifo-size = <16>; 871 status = "disabled"; 872 }; 873 874 i2c4: i2c@600 { 875 compatible = "atmel,sama5d2-i2c"; 876 reg = <0x600 0x200>; 877 interrupts = <21 IRQ_TYPE_LEVEL_HIGH 7>; 878 #address-cells = <1>; 879 #size-cells = <0>; 880 clocks = <&pmc PMC_TYPE_PERIPHERAL 21>; 881 dmas = <&dma0 882 (AT91_XDMAC_DT_MEM_IF(0) | 883 AT91_XDMAC_DT_PER_IF(1) | 884 AT91_XDMAC_DT_PERID(15))>, 885 <&dma0 886 (AT91_XDMAC_DT_MEM_IF(0) | 887 AT91_XDMAC_DT_PER_IF(1) | 888 AT91_XDMAC_DT_PERID(16))>; 889 dma-names = "tx", "rx"; 890 atmel,fifo-size = <16>; 891 status = "disabled"; 892 }; 893 }; 894 895 flx3: flexcom@fc014000 { 896 compatible = "atmel,sama5d2-flexcom"; 897 reg = <0xfc014000 0x200>; 898 clocks = <&pmc PMC_TYPE_PERIPHERAL 22>; 899 #address-cells = <1>; 900 #size-cells = <1>; 901 ranges = <0x0 0xfc014000 0x800>; 902 status = "disabled"; 903 904 uart8: serial@200 { 905 compatible = "atmel,at91sam9260-usart"; 906 reg = <0x200 0x200>; 907 interrupts = <22 IRQ_TYPE_LEVEL_HIGH 7>; 908 clocks = <&pmc PMC_TYPE_PERIPHERAL 22>; 909 clock-names = "usart"; 910 dmas = <&dma0 911 (AT91_XDMAC_DT_MEM_IF(0) | 912 AT91_XDMAC_DT_PER_IF(1) | 913 AT91_XDMAC_DT_PERID(17))>, 914 <&dma0 915 (AT91_XDMAC_DT_MEM_IF(0) | 916 AT91_XDMAC_DT_PER_IF(1) | 917 AT91_XDMAC_DT_PERID(18))>; 918 dma-names = "tx", "rx"; 919 atmel,fifo-size = <32>; 920 status = "disabled"; 921 }; 922 923 spi5: spi@400 { 924 compatible = "atmel,at91rm9200-spi"; 925 reg = <0x400 0x200>; 926 interrupts = <22 IRQ_TYPE_LEVEL_HIGH 7>; 927 #address-cells = <1>; 928 #size-cells = <0>; 929 clocks = <&pmc PMC_TYPE_PERIPHERAL 22>; 930 clock-names = "spi_clk"; 931 dmas = <&dma0 932 (AT91_XDMAC_DT_MEM_IF(0) | 933 AT91_XDMAC_DT_PER_IF(1) | 934 AT91_XDMAC_DT_PERID(17))>, 935 <&dma0 936 (AT91_XDMAC_DT_MEM_IF(0) | 937 AT91_XDMAC_DT_PER_IF(1) | 938 AT91_XDMAC_DT_PERID(18))>; 939 dma-names = "tx", "rx"; 940 atmel,fifo-size = <16>; 941 status = "disabled"; 942 }; 943 944 i2c5: i2c@600 { 945 compatible = "atmel,sama5d2-i2c"; 946 reg = <0x600 0x200>; 947 interrupts = <22 IRQ_TYPE_LEVEL_HIGH 7>; 948 #address-cells = <1>; 949 #size-cells = <0>; 950 clocks = <&pmc PMC_TYPE_PERIPHERAL 22>; 951 dmas = <&dma0 952 (AT91_XDMAC_DT_MEM_IF(0) | 953 AT91_XDMAC_DT_PER_IF(1) | 954 AT91_XDMAC_DT_PERID(17))>, 955 <&dma0 956 (AT91_XDMAC_DT_MEM_IF(0) | 957 AT91_XDMAC_DT_PER_IF(1) | 958 AT91_XDMAC_DT_PERID(18))>; 959 dma-names = "tx", "rx"; 960 atmel,fifo-size = <16>; 961 status = "disabled"; 962 }; 963 964 }; 965 966 flx4: flexcom@fc018000 { 967 compatible = "atmel,sama5d2-flexcom"; 968 reg = <0xfc018000 0x200>; 969 clocks = <&pmc PMC_TYPE_PERIPHERAL 23>; 970 #address-cells = <1>; 971 #size-cells = <1>; 972 ranges = <0x0 0xfc018000 0x800>; 973 status = "disabled"; 974 975 uart9: serial@200 { 976 compatible = "atmel,at91sam9260-usart"; 977 reg = <0x200 0x200>; 978 interrupts = <23 IRQ_TYPE_LEVEL_HIGH 7>; 979 clocks = <&pmc PMC_TYPE_PERIPHERAL 23>; 980 clock-names = "usart"; 981 dmas = <&dma0 982 (AT91_XDMAC_DT_MEM_IF(0) | 983 AT91_XDMAC_DT_PER_IF(1) | 984 AT91_XDMAC_DT_PERID(19))>, 985 <&dma0 986 (AT91_XDMAC_DT_MEM_IF(0) | 987 AT91_XDMAC_DT_PER_IF(1) | 988 AT91_XDMAC_DT_PERID(20))>; 989 dma-names = "tx", "rx"; 990 atmel,fifo-size = <32>; 991 status = "disabled"; 992 }; 993 994 spi6: spi@400 { 995 compatible = "atmel,at91rm9200-spi"; 996 reg = <0x400 0x200>; 997 interrupts = <23 IRQ_TYPE_LEVEL_HIGH 7>; 998 #address-cells = <1>; 999 #size-cells = <0>; 1000 clocks = <&pmc PMC_TYPE_PERIPHERAL 23>; 1001 clock-names = "spi_clk"; 1002 dmas = <&dma0 1003 (AT91_XDMAC_DT_MEM_IF(0) | 1004 AT91_XDMAC_DT_PER_IF(1) | 1005 AT91_XDMAC_DT_PERID(19))>, 1006 <&dma0 1007 (AT91_XDMAC_DT_MEM_IF(0) | 1008 AT91_XDMAC_DT_PER_IF(1) | 1009 AT91_XDMAC_DT_PERID(20))>; 1010 dma-names = "tx", "rx"; 1011 atmel,fifo-size = <16>; 1012 status = "disabled"; 1013 }; 1014 1015 i2c6: i2c@600 { 1016 compatible = "atmel,sama5d2-i2c"; 1017 reg = <0x600 0x200>; 1018 interrupts = <23 IRQ_TYPE_LEVEL_HIGH 7>; 1019 #address-cells = <1>; 1020 #size-cells = <0>; 1021 clocks = <&pmc PMC_TYPE_PERIPHERAL 23>; 1022 dmas = <&dma0 1023 (AT91_XDMAC_DT_MEM_IF(0) | 1024 AT91_XDMAC_DT_PER_IF(1) | 1025 AT91_XDMAC_DT_PERID(19))>, 1026 <&dma0 1027 (AT91_XDMAC_DT_MEM_IF(0) | 1028 AT91_XDMAC_DT_PER_IF(1) | 1029 AT91_XDMAC_DT_PERID(20))>; 1030 dma-names = "tx", "rx"; 1031 atmel,fifo-size = <16>; 1032 status = "disabled"; 1033 }; 1034 }; 1035 1036 trng@fc01c000 { 1037 compatible = "atmel,at91sam9g45-trng"; 1038 reg = <0xfc01c000 0x100>; 1039 interrupts = <47 IRQ_TYPE_LEVEL_HIGH 0>; 1040 clocks = <&pmc PMC_TYPE_PERIPHERAL 47>; 1041 status = "disabled"; 1042 secure-status = "okay"; 1043 }; 1044 1045 aic: interrupt-controller@fc020000 { 1046 #interrupt-cells = <3>; 1047 compatible = "atmel,sama5d2-aic"; 1048 interrupt-controller; 1049 reg = <0xfc020000 0x200>; 1050 atmel,external-irqs = <49>; 1051 }; 1052 1053 saic: interrupt-controller@f803c000 { 1054 #interrupt-cells = <3>; 1055 compatible = "atmel,sama5d2-saic"; 1056 interrupt-controller; 1057 reg = <0xf803c000 0x200>; 1058 atmel,external-irqs = <49>; 1059 status = "disabled"; 1060 secure-status = "okay"; 1061 }; 1062 1063 i2c1: i2c@fc028000 { 1064 compatible = "atmel,sama5d2-i2c"; 1065 reg = <0xfc028000 0x100>; 1066 interrupts = <30 IRQ_TYPE_LEVEL_HIGH 7>; 1067 dmas = <&dma0 1068 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 1069 AT91_XDMAC_DT_PERID(2))>, 1070 <&dma0 1071 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 1072 AT91_XDMAC_DT_PERID(3))>; 1073 dma-names = "tx", "rx"; 1074 #address-cells = <1>; 1075 #size-cells = <0>; 1076 clocks = <&pmc PMC_TYPE_PERIPHERAL 30>; 1077 atmel,fifo-size = <16>; 1078 status = "disabled"; 1079 }; 1080 1081 adc: adc@fc030000 { 1082 compatible = "atmel,sama5d2-adc"; 1083 reg = <0xfc030000 0x100>; 1084 interrupts = <40 IRQ_TYPE_LEVEL_HIGH 7>; 1085 clocks = <&pmc PMC_TYPE_PERIPHERAL 40>; 1086 clock-names = "adc_clk"; 1087 dmas = <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | AT91_XDMAC_DT_PERID(25))>; 1088 dma-names = "rx"; 1089 atmel,min-sample-rate-hz = <200000>; 1090 atmel,max-sample-rate-hz = <20000000>; 1091 atmel,startup-time-ms = <4>; 1092 atmel,trigger-edge-type = <IRQ_TYPE_EDGE_RISING>; 1093 #io-channel-cells = <1>; 1094 status = "disabled"; 1095 }; 1096 1097 resistive_touch: resistive-touch { 1098 compatible = "resistive-adc-touch"; 1099 io-channels = <&adc AT91_SAMA5D2_ADC_X_CHANNEL>, 1100 <&adc AT91_SAMA5D2_ADC_Y_CHANNEL>, 1101 <&adc AT91_SAMA5D2_ADC_P_CHANNEL>; 1102 io-channel-names = "x", "y", "pressure"; 1103 touchscreen-min-pressure = <50000>; 1104 status = "disabled"; 1105 }; 1106 1107 pioA: pinctrl@fc039000 { 1108 compatible = "atmel,sama5d2-pinctrl"; 1109 reg = <0xfc039000 0x600>; 1110 interrupts = <18 IRQ_TYPE_LEVEL_HIGH 7>, 1111 <68 IRQ_TYPE_LEVEL_HIGH 7>, 1112 <69 IRQ_TYPE_LEVEL_HIGH 7>, 1113 <70 IRQ_TYPE_LEVEL_HIGH 7>; 1114 interrupt-controller; 1115 #interrupt-cells = <2>; 1116 gpio-controller; 1117 #gpio-cells = <2>; 1118 clocks = <&pmc PMC_TYPE_PERIPHERAL 18>; 1119 }; 1120 1121 pioBU: secumod@fc040000 { 1122 compatible = "atmel,sama5d2-secumod", "syscon"; 1123 reg = <0xfc040000 0x100>; 1124 1125 gpio-controller; 1126 #gpio-cells = <2>; 1127 status = "disabled"; 1128 secure-status = "okay"; 1129 }; 1130 1131 tdes@fc044000 { 1132 compatible = "atmel,at91sam9g46-tdes"; 1133 reg = <0xfc044000 0x100>; 1134 interrupts = <11 IRQ_TYPE_LEVEL_HIGH 0>; 1135 dmas = <&dma0 1136 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 1137 AT91_XDMAC_DT_PERID(28))>, 1138 <&dma0 1139 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 1140 AT91_XDMAC_DT_PERID(29))>; 1141 dma-names = "tx", "rx"; 1142 clocks = <&pmc PMC_TYPE_PERIPHERAL 11>; 1143 clock-names = "tdes_clk"; 1144 status = "okay"; 1145 }; 1146 1147 classd: classd@fc048000 { 1148 compatible = "atmel,sama5d2-classd"; 1149 reg = <0xfc048000 0x100>; 1150 interrupts = <59 IRQ_TYPE_LEVEL_HIGH 7>; 1151 dmas = <&dma0 1152 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 1153 AT91_XDMAC_DT_PERID(47))>; 1154 dma-names = "tx"; 1155 clocks = <&pmc PMC_TYPE_PERIPHERAL 59>, <&pmc PMC_TYPE_GCK 59>; 1156 clock-names = "pclk", "gclk"; 1157 status = "disabled"; 1158 }; 1159 1160 i2s1: i2s@fc04c000 { 1161 compatible = "atmel,sama5d2-i2s"; 1162 reg = <0xfc04c000 0x100>; 1163 interrupts = <55 IRQ_TYPE_LEVEL_HIGH 7>; 1164 dmas = <&dma0 1165 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 1166 AT91_XDMAC_DT_PERID(33))>, 1167 <&dma0 1168 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 1169 AT91_XDMAC_DT_PERID(34))>; 1170 dma-names = "tx", "rx"; 1171 clocks = <&pmc PMC_TYPE_PERIPHERAL 55>, <&pmc PMC_TYPE_GCK 55>; 1172 clock-names = "pclk", "gclk"; 1173 assigned-clocks = <&pmc PMC_TYPE_CORE PMC_I2S1_MUX>; 1174 assigned-parrents = <&pmc PMC_TYPE_GCK 55>; 1175 status = "disabled"; 1176 }; 1177 1178 can1: can@fc050000 { 1179 compatible = "bosch,m_can"; 1180 reg = <0xfc050000 0x4000>, <0x210000 0x3800>; 1181 reg-names = "m_can", "message_ram"; 1182 interrupts = <57 IRQ_TYPE_LEVEL_HIGH 7>, 1183 <65 IRQ_TYPE_LEVEL_HIGH 7>; 1184 interrupt-names = "int0", "int1"; 1185 clocks = <&pmc PMC_TYPE_PERIPHERAL 57>, <&pmc PMC_TYPE_GCK 57>; 1186 clock-names = "hclk", "cclk"; 1187 assigned-clocks = <&pmc PMC_TYPE_GCK 57>; 1188 assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_UTMI>; 1189 assigned-clock-rates = <40000000>; 1190 bosch,mram-cfg = <0x1c00 0 0 64 0 0 32 32>; 1191 status = "disabled"; 1192 }; 1193 1194 sfrbu: sfr@fc05c000 { 1195 compatible = "atmel,sama5d2-sfrbu", "syscon"; 1196 reg = <0xfc05c000 0x20>; 1197 }; 1198 1199 chipid@fc069000 { 1200 compatible = "atmel,sama5d2-chipid"; 1201 reg = <0xfc069000 0x8>; 1202 }; 1203 }; 1204 }; 1205}; 1206