1*4882a593SmuzhiyunFrom 91c980d4cf88b0c12fe5971fe16c7b97b5a942af Mon Sep 17 00:00:00 2001 2*4882a593SmuzhiyunFrom: Khem Raj <raj.khem@gmail.com> 3*4882a593SmuzhiyunDate: Tue, 17 Dec 2019 14:57:55 -0800 4*4882a593SmuzhiyunSubject: [PATCH] Disable fpu using code when using clang/mips64 combo 5*4882a593Smuzhiyun 6*4882a593Smuzhiyunit works around clang's inline asm error 7*4882a593Smuzhiyun 8*4882a593Smuzhiyunerror: couldn't allocate output register for constraint 'r' 9*4882a593Smuzhiyun 10*4882a593SmuzhiyunUpstream-Status: Pending 11*4882a593SmuzhiyunSigned-off-by: Khem Raj <raj.khem@gmail.com> 12*4882a593Smuzhiyun--- 13*4882a593Smuzhiyun gst-libs/ext/libav/libavcodec/mips/aacdec_mips.c | 4 ++-- 14*4882a593Smuzhiyun 1 file changed, 2 insertions(+), 2 deletions(-) 15*4882a593Smuzhiyun 16*4882a593Smuzhiyundiff --git a/gst-libs/ext/libav/libavcodec/mips/aacdec_mips.c b/gst-libs/ext/libav/libavcodec/mips/aacdec_mips.c 17*4882a593Smuzhiyunindex 253cdeb..df4f25d 100644 18*4882a593Smuzhiyun--- a/gst-libs/ext/libav/libavcodec/mips/aacdec_mips.c 19*4882a593Smuzhiyun+++ b/gst-libs/ext/libav/libavcodec/mips/aacdec_mips.c 20*4882a593Smuzhiyun@@ -282,7 +282,7 @@ static void apply_ltp_mips(AACContext *ac, SingleChannelElement *sce) 21*4882a593Smuzhiyun } 22*4882a593Smuzhiyun } 23*4882a593Smuzhiyun 24*4882a593Smuzhiyun-#if HAVE_MIPSFPU 25*4882a593Smuzhiyun+#if HAVE_MIPSFPU && !defined(__clang__) 26*4882a593Smuzhiyun static av_always_inline void fmul_and_reverse(float *dst, const float *src0, const float *src1, int count) 27*4882a593Smuzhiyun { 28*4882a593Smuzhiyun /* Multiply 'count' floats in src0 by src1 and store the results in dst in reverse */ 29*4882a593Smuzhiyun@@ -435,7 +435,7 @@ void ff_aacdec_init_mips(AACContext *c) 30*4882a593Smuzhiyun #if HAVE_INLINE_ASM 31*4882a593Smuzhiyun c->imdct_and_windowing = imdct_and_windowing_mips; 32*4882a593Smuzhiyun c->apply_ltp = apply_ltp_mips; 33*4882a593Smuzhiyun-#if HAVE_MIPSFPU 34*4882a593Smuzhiyun+#if HAVE_MIPSFPU && !defined(__clang__) 35*4882a593Smuzhiyun c->update_ltp = update_ltp_mips; 36*4882a593Smuzhiyun #endif /* HAVE_MIPSFPU */ 37*4882a593Smuzhiyun #endif /* HAVE_INLINE_ASM */ 38*4882a593Smuzhiyun-- 39*4882a593Smuzhiyun2.24.1 40*4882a593Smuzhiyun 41