1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0+ */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * (C) Copyright 2019 Rockchip Electronics Co., Ltd 4*4882a593Smuzhiyun */ 5*4882a593Smuzhiyun 6*4882a593Smuzhiyun #ifndef _RV1126_SECURE_OTP_H_ 7*4882a593Smuzhiyun #define _RV1126_SECURE_OTP_H_ 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #define NVM_CEB 0x00 10*4882a593Smuzhiyun #define NVM_RSTB 0x04 11*4882a593Smuzhiyun #define NVM_TCSRST 0x08 12*4882a593Smuzhiyun #define NVM_TCEW 0x0c 13*4882a593Smuzhiyun #define NVM_TRW 0x10 14*4882a593Smuzhiyun #define NVM_TRS 0x14 15*4882a593Smuzhiyun #define NVM_ST 0x18 16*4882a593Smuzhiyun #define NVM_RADDR 0x1c 17*4882a593Smuzhiyun #define NVM_RSTART 0x20 18*4882a593Smuzhiyun #define NVM_RDATA 0x24 19*4882a593Smuzhiyun #define NVM_TRWH 0x28 20*4882a593Smuzhiyun #define NVM_TREW 0x2c 21*4882a593Smuzhiyun #define NVM_READ_ST 0x30 22*4882a593Smuzhiyun #define NVM_PRADDR 0x34 23*4882a593Smuzhiyun #define NVM_PRLEN 0x38 24*4882a593Smuzhiyun #define NVM_PRDATA 0x3c 25*4882a593Smuzhiyun #define NVM_FAILTIME 0x40 26*4882a593Smuzhiyun #define NVM_PRSTART 0x44 27*4882a593Smuzhiyun #define NVM_PRSTATE 0x48 28*4882a593Smuzhiyun #define NVM_PRSUCCESS 0x4c 29*4882a593Smuzhiyun #define NVM_TAS 0x50 30*4882a593Smuzhiyun #define NVM_TWWL 0x54 31*4882a593Smuzhiyun #define NVM_TDLEH 0x58 32*4882a593Smuzhiyun #define NVM_TDPD 0x5c 33*4882a593Smuzhiyun #define NVM_TPES 0x60 34*4882a593Smuzhiyun #define NVM_TCPS 0x64 35*4882a593Smuzhiyun #define NVM_TPW 0x68 36*4882a593Smuzhiyun #define NVM_TCPH 0x6c 37*4882a593Smuzhiyun #define NVM_TPEH 0x70 38*4882a593Smuzhiyun #define NVM_TPTPD 0x74 39*4882a593Smuzhiyun #define NVM_TPGMAS 0x78 40*4882a593Smuzhiyun #define OTPC_INT_ST 0x7c 41*4882a593Smuzhiyun #define NVM_INT_EN 0x80 42*4882a593Smuzhiyun #define OTP_PROG_MASK_BASE 0x0200 43*4882a593Smuzhiyun #define OTP_READ_MASK_BASE 0x0300 44*4882a593Smuzhiyun #define OTP_MASK_BYPASS 0x0400 45*4882a593Smuzhiyun #define OTP_MASK_INT_CON 0x0404 46*4882a593Smuzhiyun #define OTP_MASK_INT_STATUS 0x0408 47*4882a593Smuzhiyun #define OTP_MASK_STATUS 0x040C 48*4882a593Smuzhiyun #define OTP_MASK_PROG_LOCK 0x0410 49*4882a593Smuzhiyun #define OTP_MASK_READ_LOCK 0x0414 50*4882a593Smuzhiyun #define OTP_MASK_BYPASS_LOCK 0x0418 51*4882a593Smuzhiyun #define OTP_SLICE_LOCK 0x041c 52*4882a593Smuzhiyun #define OTP_SLICE 0x0420 53*4882a593Smuzhiyun 54*4882a593Smuzhiyun struct rockchip_otp_platdata { 55*4882a593Smuzhiyun void __iomem *base; 56*4882a593Smuzhiyun unsigned long secure_conf_base; 57*4882a593Smuzhiyun }; 58*4882a593Smuzhiyun 59*4882a593Smuzhiyun #endif 60*4882a593Smuzhiyun 61