1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * (C) Copyright 2019 Rockchip Electronics Co., Ltd 4 */ 5 6 #ifndef _RV1126_SECURE_OTP_H_ 7 #define _RV1126_SECURE_OTP_H_ 8 9 #define NVM_CEB 0x00 10 #define NVM_RSTB 0x04 11 #define NVM_TCSRST 0x08 12 #define NVM_TCEW 0x0c 13 #define NVM_TRW 0x10 14 #define NVM_TRS 0x14 15 #define NVM_ST 0x18 16 #define NVM_RADDR 0x1c 17 #define NVM_RSTART 0x20 18 #define NVM_RDATA 0x24 19 #define NVM_TRWH 0x28 20 #define NVM_TREW 0x2c 21 #define NVM_READ_ST 0x30 22 #define NVM_PRADDR 0x34 23 #define NVM_PRLEN 0x38 24 #define NVM_PRDATA 0x3c 25 #define NVM_FAILTIME 0x40 26 #define NVM_PRSTART 0x44 27 #define NVM_PRSTATE 0x48 28 #define NVM_PRSUCCESS 0x4c 29 #define NVM_TAS 0x50 30 #define NVM_TWWL 0x54 31 #define NVM_TDLEH 0x58 32 #define NVM_TDPD 0x5c 33 #define NVM_TPES 0x60 34 #define NVM_TCPS 0x64 35 #define NVM_TPW 0x68 36 #define NVM_TCPH 0x6c 37 #define NVM_TPEH 0x70 38 #define NVM_TPTPD 0x74 39 #define NVM_TPGMAS 0x78 40 #define OTPC_INT_ST 0x7c 41 #define NVM_INT_EN 0x80 42 #define OTP_PROG_MASK_BASE 0x0200 43 #define OTP_READ_MASK_BASE 0x0300 44 #define OTP_MASK_BYPASS 0x0400 45 #define OTP_MASK_INT_CON 0x0404 46 #define OTP_MASK_INT_STATUS 0x0408 47 #define OTP_MASK_STATUS 0x040C 48 #define OTP_MASK_PROG_LOCK 0x0410 49 #define OTP_MASK_READ_LOCK 0x0414 50 #define OTP_MASK_BYPASS_LOCK 0x0418 51 #define OTP_SLICE_LOCK 0x041c 52 #define OTP_SLICE 0x0420 53 54 struct rockchip_otp_platdata { 55 void __iomem *base; 56 unsigned long secure_conf_base; 57 }; 58 59 #endif 60 61