1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * (C) Copyright 2017 Rockchip Electronics Co., Ltd 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun #ifndef __ROCKCHIP_IR_H__ 7*4882a593Smuzhiyun #define __ROCKCHIP_IR_H__ 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #include <linux/bitops.h> 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun /* Registers */ 12*4882a593Smuzhiyun /* High polarity cycles */ 13*4882a593Smuzhiyun #define PWM_HPR_REG 0x04 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun /* Low polarity cycles */ 16*4882a593Smuzhiyun #define PWM_LPR_REG 0x08 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun /* PWM Control */ 19*4882a593Smuzhiyun #define PWM_CTL_REG 0x0c 20*4882a593Smuzhiyun /* Enable */ 21*4882a593Smuzhiyun #define REG_CTL_EN BIT(0) 22*4882a593Smuzhiyun /* capture mode */ 23*4882a593Smuzhiyun #define REG_CTL_MD BIT(2) 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun /* Interrupt Status */ 26*4882a593Smuzhiyun #define PWM_STA_REG(id) ((4 - (id)) * 0x10) 27*4882a593Smuzhiyun #define PWM_CH_POL(id) BIT(id + 8) 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun /* Interrupt Enable */ 30*4882a593Smuzhiyun #define PWM_INT_REG(id) ((4 - (id)) * 0x14) 31*4882a593Smuzhiyun #define PWM_CH_INT(id) BIT(id) 32*4882a593Smuzhiyun 33*4882a593Smuzhiyun /* NEC IR Pulse/Space protocol */ 34*4882a593Smuzhiyun #define NEC_NBITS 32 35*4882a593Smuzhiyun #define NEC_UNIT 562500 /* ns */ 36*4882a593Smuzhiyun #define NEC_HEADER_PULSE (16 * NEC_UNIT) 37*4882a593Smuzhiyun #define NEC_HEADER_SPACE (8 * NEC_UNIT) 38*4882a593Smuzhiyun #define NEC_BIT_PULSE (1 * NEC_UNIT) 39*4882a593Smuzhiyun #define NEC_BIT_0_SPACE (1 * NEC_UNIT) 40*4882a593Smuzhiyun #define NEC_BIT_1_SPACE (3 * NEC_UNIT) 41*4882a593Smuzhiyun 42*4882a593Smuzhiyun #define TO_US(duration) ((duration) / 1000) 43*4882a593Smuzhiyun #define TO_STR(is_pulse) ((is_pulse) ? "pulse" : "space") 44*4882a593Smuzhiyun 45*4882a593Smuzhiyun #define MAX_NUM_KEYS 60 46*4882a593Smuzhiyun 47*4882a593Smuzhiyun enum nec_state { 48*4882a593Smuzhiyun STATE_INACTIVE, 49*4882a593Smuzhiyun STATE_HEADER_SPACE, 50*4882a593Smuzhiyun STATE_BIT_PULSE, 51*4882a593Smuzhiyun STATE_BIT_SPACE, 52*4882a593Smuzhiyun }; 53*4882a593Smuzhiyun 54*4882a593Smuzhiyun struct rockchip_ir_priv { 55*4882a593Smuzhiyun fdt_addr_t base; 56*4882a593Smuzhiyun ulong freq; 57*4882a593Smuzhiyun ulong period; 58*4882a593Smuzhiyun int id; 59*4882a593Smuzhiyun int num; 60*4882a593Smuzhiyun int keycode; 61*4882a593Smuzhiyun int repeat; 62*4882a593Smuzhiyun }; 63*4882a593Smuzhiyun 64*4882a593Smuzhiyun struct ir_raw_event { 65*4882a593Smuzhiyun u32 duration; 66*4882a593Smuzhiyun unsigned pulse:1; 67*4882a593Smuzhiyun }; 68*4882a593Smuzhiyun 69*4882a593Smuzhiyun struct nec_dec { 70*4882a593Smuzhiyun int state; 71*4882a593Smuzhiyun unsigned count; 72*4882a593Smuzhiyun u32 bits; 73*4882a593Smuzhiyun }; 74*4882a593Smuzhiyun 75*4882a593Smuzhiyun struct rc_map_table { 76*4882a593Smuzhiyun u32 scancode; 77*4882a593Smuzhiyun u32 keycode; 78*4882a593Smuzhiyun }; 79*4882a593Smuzhiyun 80*4882a593Smuzhiyun struct rc_map { 81*4882a593Smuzhiyun u32 usercode; 82*4882a593Smuzhiyun u32 nbuttons; 83*4882a593Smuzhiyun struct rc_map_table scan[MAX_NUM_KEYS]; 84*4882a593Smuzhiyun }; 85*4882a593Smuzhiyun 86*4882a593Smuzhiyun /* macros for IR decoders */ eq_margin(unsigned d1,unsigned d2,unsigned margin)87*4882a593Smuzhiyunstatic inline bool eq_margin(unsigned d1, unsigned d2, unsigned margin) 88*4882a593Smuzhiyun { 89*4882a593Smuzhiyun return ((d1 > (d2 - margin)) && (d1 < (d2 + margin))); 90*4882a593Smuzhiyun } 91*4882a593Smuzhiyun 92*4882a593Smuzhiyun #endif /* __ROCKCHIP_IR_H__ */ 93