1 /* 2 * (C) Copyright 2017 Rockchip Electronics Co., Ltd 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 #ifndef __ROCKCHIP_IR_H__ 7 #define __ROCKCHIP_IR_H__ 8 9 #include <linux/bitops.h> 10 11 /* Registers */ 12 /* High polarity cycles */ 13 #define PWM_HPR_REG 0x04 14 15 /* Low polarity cycles */ 16 #define PWM_LPR_REG 0x08 17 18 /* PWM Control */ 19 #define PWM_CTL_REG 0x0c 20 /* Enable */ 21 #define REG_CTL_EN BIT(0) 22 /* capture mode */ 23 #define REG_CTL_MD BIT(2) 24 25 /* Interrupt Status */ 26 #define PWM_STA_REG(id) ((4 - (id)) * 0x10) 27 #define PWM_CH_POL(id) BIT(id + 8) 28 29 /* Interrupt Enable */ 30 #define PWM_INT_REG(id) ((4 - (id)) * 0x14) 31 #define PWM_CH_INT(id) BIT(id) 32 33 /* NEC IR Pulse/Space protocol */ 34 #define NEC_NBITS 32 35 #define NEC_UNIT 562500 /* ns */ 36 #define NEC_HEADER_PULSE (16 * NEC_UNIT) 37 #define NEC_HEADER_SPACE (8 * NEC_UNIT) 38 #define NEC_BIT_PULSE (1 * NEC_UNIT) 39 #define NEC_BIT_0_SPACE (1 * NEC_UNIT) 40 #define NEC_BIT_1_SPACE (3 * NEC_UNIT) 41 42 #define TO_US(duration) ((duration) / 1000) 43 #define TO_STR(is_pulse) ((is_pulse) ? "pulse" : "space") 44 45 #define MAX_NUM_KEYS 60 46 47 enum nec_state { 48 STATE_INACTIVE, 49 STATE_HEADER_SPACE, 50 STATE_BIT_PULSE, 51 STATE_BIT_SPACE, 52 }; 53 54 struct rockchip_ir_priv { 55 fdt_addr_t base; 56 ulong freq; 57 ulong period; 58 int id; 59 int num; 60 int keycode; 61 int repeat; 62 }; 63 64 struct ir_raw_event { 65 u32 duration; 66 unsigned pulse:1; 67 }; 68 69 struct nec_dec { 70 int state; 71 unsigned count; 72 u32 bits; 73 }; 74 75 struct rc_map_table { 76 u32 scancode; 77 u32 keycode; 78 }; 79 80 struct rc_map { 81 u32 usercode; 82 u32 nbuttons; 83 struct rc_map_table scan[MAX_NUM_KEYS]; 84 }; 85 86 /* macros for IR decoders */ eq_margin(unsigned d1,unsigned d2,unsigned margin)87static inline bool eq_margin(unsigned d1, unsigned d2, unsigned margin) 88 { 89 return ((d1 > (d2 - margin)) && (d1 < (d2 + margin))); 90 } 91 92 #endif /* __ROCKCHIP_IR_H__ */ 93