1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0 IBM-pibs 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * Additions (C) Copyright 2009 Industrie Dial Face S.p.A. 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun /*----------------------------------------------------------------------------+ 7*4882a593Smuzhiyun | 8*4882a593Smuzhiyun | File Name: miiphy.h 9*4882a593Smuzhiyun | 10*4882a593Smuzhiyun | Function: Include file defining PHY registers. 11*4882a593Smuzhiyun | 12*4882a593Smuzhiyun | Author: Mark Wisner 13*4882a593Smuzhiyun | 14*4882a593Smuzhiyun +----------------------------------------------------------------------------*/ 15*4882a593Smuzhiyun #ifndef _miiphy_h_ 16*4882a593Smuzhiyun #define _miiphy_h_ 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun #include <common.h> 19*4882a593Smuzhiyun #include <linux/mii.h> 20*4882a593Smuzhiyun #include <linux/list.h> 21*4882a593Smuzhiyun #include <net.h> 22*4882a593Smuzhiyun #include <phy.h> 23*4882a593Smuzhiyun 24*4882a593Smuzhiyun int miiphy_read(const char *devname, unsigned char addr, unsigned char reg, 25*4882a593Smuzhiyun unsigned short *value); 26*4882a593Smuzhiyun int miiphy_write(const char *devname, unsigned char addr, unsigned char reg, 27*4882a593Smuzhiyun unsigned short value); 28*4882a593Smuzhiyun int miiphy_info(const char *devname, unsigned char addr, unsigned int *oui, 29*4882a593Smuzhiyun unsigned char *model, unsigned char *rev); 30*4882a593Smuzhiyun int miiphy_reset(const char *devname, unsigned char addr); 31*4882a593Smuzhiyun int miiphy_speed(const char *devname, unsigned char addr); 32*4882a593Smuzhiyun int miiphy_duplex(const char *devname, unsigned char addr); 33*4882a593Smuzhiyun int miiphy_is_1000base_x(const char *devname, unsigned char addr); 34*4882a593Smuzhiyun #ifdef CONFIG_SYS_FAULT_ECHO_LINK_DOWN 35*4882a593Smuzhiyun int miiphy_link(const char *devname, unsigned char addr); 36*4882a593Smuzhiyun #endif 37*4882a593Smuzhiyun 38*4882a593Smuzhiyun void miiphy_init(void); 39*4882a593Smuzhiyun 40*4882a593Smuzhiyun int miiphy_set_current_dev(const char *devname); 41*4882a593Smuzhiyun const char *miiphy_get_current_dev(void); 42*4882a593Smuzhiyun struct mii_dev *mdio_get_current_dev(void); 43*4882a593Smuzhiyun struct mii_dev *miiphy_get_dev_by_name(const char *devname); 44*4882a593Smuzhiyun struct phy_device *mdio_phydev_for_ethname(const char *devname); 45*4882a593Smuzhiyun 46*4882a593Smuzhiyun void miiphy_listdev(void); 47*4882a593Smuzhiyun 48*4882a593Smuzhiyun struct mii_dev *mdio_alloc(void); 49*4882a593Smuzhiyun void mdio_free(struct mii_dev *bus); 50*4882a593Smuzhiyun int mdio_register(struct mii_dev *bus); 51*4882a593Smuzhiyun 52*4882a593Smuzhiyun /** 53*4882a593Smuzhiyun * mdio_register_seq - Register mdio bus with sequence number 54*4882a593Smuzhiyun * @bus: mii device structure 55*4882a593Smuzhiyun * @seq: sequence number 56*4882a593Smuzhiyun * 57*4882a593Smuzhiyun * Return: 0 if success, negative value if error 58*4882a593Smuzhiyun */ 59*4882a593Smuzhiyun int mdio_register_seq(struct mii_dev *bus, int seq); 60*4882a593Smuzhiyun int mdio_unregister(struct mii_dev *bus); 61*4882a593Smuzhiyun void mdio_list_devices(void); 62*4882a593Smuzhiyun 63*4882a593Smuzhiyun #ifdef CONFIG_BITBANGMII 64*4882a593Smuzhiyun 65*4882a593Smuzhiyun #define BB_MII_DEVNAME "bb_miiphy" 66*4882a593Smuzhiyun 67*4882a593Smuzhiyun struct bb_miiphy_bus { 68*4882a593Smuzhiyun char name[16]; 69*4882a593Smuzhiyun int (*init)(struct bb_miiphy_bus *bus); 70*4882a593Smuzhiyun int (*mdio_active)(struct bb_miiphy_bus *bus); 71*4882a593Smuzhiyun int (*mdio_tristate)(struct bb_miiphy_bus *bus); 72*4882a593Smuzhiyun int (*set_mdio)(struct bb_miiphy_bus *bus, int v); 73*4882a593Smuzhiyun int (*get_mdio)(struct bb_miiphy_bus *bus, int *v); 74*4882a593Smuzhiyun int (*set_mdc)(struct bb_miiphy_bus *bus, int v); 75*4882a593Smuzhiyun int (*delay)(struct bb_miiphy_bus *bus); 76*4882a593Smuzhiyun #ifdef CONFIG_BITBANGMII_MULTI 77*4882a593Smuzhiyun void *priv; 78*4882a593Smuzhiyun #endif 79*4882a593Smuzhiyun }; 80*4882a593Smuzhiyun 81*4882a593Smuzhiyun extern struct bb_miiphy_bus bb_miiphy_buses[]; 82*4882a593Smuzhiyun extern int bb_miiphy_buses_num; 83*4882a593Smuzhiyun 84*4882a593Smuzhiyun void bb_miiphy_init(void); 85*4882a593Smuzhiyun int bb_miiphy_read(struct mii_dev *miidev, int addr, int devad, int reg); 86*4882a593Smuzhiyun int bb_miiphy_write(struct mii_dev *miidev, int addr, int devad, int reg, 87*4882a593Smuzhiyun u16 value); 88*4882a593Smuzhiyun #endif 89*4882a593Smuzhiyun 90*4882a593Smuzhiyun /* phy seed setup */ 91*4882a593Smuzhiyun #define AUTO 99 92*4882a593Smuzhiyun #define _1000BASET 1000 93*4882a593Smuzhiyun #define _100BASET 100 94*4882a593Smuzhiyun #define _10BASET 10 95*4882a593Smuzhiyun #define HALF 22 96*4882a593Smuzhiyun #define FULL 44 97*4882a593Smuzhiyun 98*4882a593Smuzhiyun /* phy register offsets */ 99*4882a593Smuzhiyun #define MII_MIPSCR 0x11 100*4882a593Smuzhiyun 101*4882a593Smuzhiyun /* MII_LPA */ 102*4882a593Smuzhiyun #define PHY_ANLPAR_PSB_802_3 0x0001 103*4882a593Smuzhiyun #define PHY_ANLPAR_PSB_802_9 0x0002 104*4882a593Smuzhiyun 105*4882a593Smuzhiyun /* MII_CTRL1000 masks */ 106*4882a593Smuzhiyun #define PHY_1000BTCR_1000FD 0x0200 107*4882a593Smuzhiyun #define PHY_1000BTCR_1000HD 0x0100 108*4882a593Smuzhiyun 109*4882a593Smuzhiyun /* MII_STAT1000 masks */ 110*4882a593Smuzhiyun #define PHY_1000BTSR_MSCF 0x8000 111*4882a593Smuzhiyun #define PHY_1000BTSR_MSCR 0x4000 112*4882a593Smuzhiyun #define PHY_1000BTSR_LRS 0x2000 113*4882a593Smuzhiyun #define PHY_1000BTSR_RRS 0x1000 114*4882a593Smuzhiyun #define PHY_1000BTSR_1000FD 0x0800 115*4882a593Smuzhiyun #define PHY_1000BTSR_1000HD 0x0400 116*4882a593Smuzhiyun 117*4882a593Smuzhiyun /* phy EXSR */ 118*4882a593Smuzhiyun #define ESTATUS_1000XF 0x8000 119*4882a593Smuzhiyun #define ESTATUS_1000XH 0x4000 120*4882a593Smuzhiyun 121*4882a593Smuzhiyun #ifdef CONFIG_DM_MDIO 122*4882a593Smuzhiyun 123*4882a593Smuzhiyun /** 124*4882a593Smuzhiyun * struct mdio_perdev_priv - Per-device class data for MDIO DM 125*4882a593Smuzhiyun * 126*4882a593Smuzhiyun * @mii_bus: Supporting MII legacy bus 127*4882a593Smuzhiyun */ 128*4882a593Smuzhiyun struct mdio_perdev_priv { 129*4882a593Smuzhiyun struct mii_dev *mii_bus; 130*4882a593Smuzhiyun }; 131*4882a593Smuzhiyun 132*4882a593Smuzhiyun /** 133*4882a593Smuzhiyun * struct mdio_ops - MDIO bus operations 134*4882a593Smuzhiyun * 135*4882a593Smuzhiyun * @read: Read from a PHY register 136*4882a593Smuzhiyun * @write: Write to a PHY register 137*4882a593Smuzhiyun * @reset: Reset the MDIO bus, NULL if not supported 138*4882a593Smuzhiyun */ 139*4882a593Smuzhiyun struct mdio_ops { 140*4882a593Smuzhiyun int (*read)(struct udevice *mdio_dev, int addr, int devad, int reg); 141*4882a593Smuzhiyun int (*write)(struct udevice *mdio_dev, int addr, int devad, int reg, 142*4882a593Smuzhiyun u16 val); 143*4882a593Smuzhiyun int (*reset)(struct udevice *mdio_dev); 144*4882a593Smuzhiyun }; 145*4882a593Smuzhiyun 146*4882a593Smuzhiyun #define mdio_get_ops(dev) ((struct mdio_ops *)(dev)->driver->ops) 147*4882a593Smuzhiyun 148*4882a593Smuzhiyun /** 149*4882a593Smuzhiyun * dm_mdio_probe_devices - Call probe on all MII devices, currently used for 150*4882a593Smuzhiyun * MDIO console commands. 151*4882a593Smuzhiyun */ 152*4882a593Smuzhiyun void dm_mdio_probe_devices(void); 153*4882a593Smuzhiyun 154*4882a593Smuzhiyun /** 155*4882a593Smuzhiyun * dm_mdio_phy_connect - Wrapper over phy_connect for DM MDIO 156*4882a593Smuzhiyun * 157*4882a593Smuzhiyun * @dev: mdio dev 158*4882a593Smuzhiyun * @addr: PHY address on MDIO bus 159*4882a593Smuzhiyun * @ethdev: ethernet device to connect to the PHY 160*4882a593Smuzhiyun * @interface: MAC-PHY protocol 161*4882a593Smuzhiyun * 162*4882a593Smuzhiyun * @return pointer to phy_device, or 0 on error 163*4882a593Smuzhiyun */ 164*4882a593Smuzhiyun struct phy_device *dm_mdio_phy_connect(struct udevice *dev, int addr, 165*4882a593Smuzhiyun struct udevice *ethdev, 166*4882a593Smuzhiyun phy_interface_t interface); 167*4882a593Smuzhiyun 168*4882a593Smuzhiyun #endif 169*4882a593Smuzhiyun 170*4882a593Smuzhiyun #endif 171