1 /* 2 * (C) Copyright 2008-2017 Fuzhou Rockchip Electronics Co., Ltd 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #ifndef __ROCKCHIP_MIPI_DSI_H__ 8 #define __ROCKCHIP_MIPI_DSI_H__ 9 10 #define BIT(nr) (1UL << (nr)) 11 12 /* request ACK from peripheral */ 13 #define MIPI_DSI_MSG_REQ_ACK BIT(0) 14 /* use Low Power Mode to transmit message */ 15 #define MIPI_DSI_MSG_USE_LPM BIT(1) 16 17 /* DSI mode flags */ 18 19 /* video mode */ 20 #define MIPI_DSI_MODE_VIDEO BIT(0) 21 /* video burst mode */ 22 #define MIPI_DSI_MODE_VIDEO_BURST BIT(1) 23 /* video pulse mode */ 24 #define MIPI_DSI_MODE_VIDEO_SYNC_PULSE BIT(2) 25 /* enable auto vertical count mode */ 26 #define MIPI_DSI_MODE_VIDEO_AUTO_VERT BIT(3) 27 /* enable hsync-end packets in vsync-pulse and v-porch area */ 28 #define MIPI_DSI_MODE_VIDEO_HSE BIT(4) 29 /* disable hfront-porch area */ 30 #define MIPI_DSI_MODE_VIDEO_HFP BIT(5) 31 /* disable hback-porch area */ 32 #define MIPI_DSI_MODE_VIDEO_HBP BIT(6) 33 /* disable hsync-active area */ 34 #define MIPI_DSI_MODE_VIDEO_HSA BIT(7) 35 /* flush display FIFO on vsync pulse */ 36 #define MIPI_DSI_MODE_VSYNC_FLUSH BIT(8) 37 /* disable EoT packets in HS mode */ 38 #define MIPI_DSI_MODE_EOT_PACKET BIT(9) 39 /* device supports non-continuous clock behavior (DSI spec 5.6.1) */ 40 #define MIPI_DSI_CLOCK_NON_CONTINUOUS BIT(10) 41 /* transmit data in low power */ 42 #define MIPI_DSI_MODE_LPM BIT(11) 43 44 #define MIPI_DSI_DCS_POWER_MODE_DISPLAY BIT(2) 45 #define MIPI_DSI_DCS_POWER_MODE_NORMAL BIT(3) 46 #define MIPI_DSI_DCS_POWER_MODE_SLEEP BIT(4) 47 #define MIPI_DSI_DCS_POWER_MODE_PARTIAL BIT(5) 48 #define MIPI_DSI_DCS_POWER_MODE_IDLE BIT(6) 49 50 #define MIPI_DSI_FMT_RGB888 0 51 #define MIPI_DSI_FMT_RGB666 1 52 #define MIPI_DSI_FMT_RGB666_PACKED 2 53 #define MIPI_DSI_FMT_RGB565 3 54 55 #endif /* __ROCKCHIP_MIPI_DSI__ */ 56