xref: /OK3568_Linux_fs/u-boot/include/dt-bindings/clock/rv1106-cru.h (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun  * Copyright (c) 2022 Rockchip Electronics Co. Ltd.
4*4882a593Smuzhiyun  * Author: Elaine Zhang <zhangqing@rock-chips.com>
5*4882a593Smuzhiyun  */
6*4882a593Smuzhiyun 
7*4882a593Smuzhiyun #ifndef _DT_BINDINGS_CLK_ROCKCHIP_RV1106_H
8*4882a593Smuzhiyun #define _DT_BINDINGS_CLK_ROCKCHIP_RV1106_H
9*4882a593Smuzhiyun 
10*4882a593Smuzhiyun /* pll clocks */
11*4882a593Smuzhiyun #define PLL_APLL		1
12*4882a593Smuzhiyun #define PLL_DPLL		2
13*4882a593Smuzhiyun #define PLL_CPLL		3
14*4882a593Smuzhiyun #define PLL_GPLL		4
15*4882a593Smuzhiyun #define ARMCLK			5
16*4882a593Smuzhiyun 
17*4882a593Smuzhiyun /* clk (clocks) */
18*4882a593Smuzhiyun #define PCLK_DDRPHY		11
19*4882a593Smuzhiyun #define PCLK_DDR_ROOT		12
20*4882a593Smuzhiyun #define PCLK_DDRMON		13
21*4882a593Smuzhiyun #define CLK_TIMER_DDRMON	14
22*4882a593Smuzhiyun #define PCLK_DDRC		15
23*4882a593Smuzhiyun #define PCLK_DFICTRL		16
24*4882a593Smuzhiyun #define ACLK_DDR_ROOT		17
25*4882a593Smuzhiyun #define ACLK_SYS_SHRM		18
26*4882a593Smuzhiyun #define HCLK_NPU_ROOT		19
27*4882a593Smuzhiyun #define ACLK_NPU_ROOT		20
28*4882a593Smuzhiyun #define PCLK_NPU_ROOT		21
29*4882a593Smuzhiyun #define HCLK_RKNN		22
30*4882a593Smuzhiyun #define ACLK_RKNN		23
31*4882a593Smuzhiyun #define PCLK_ACODEC		24
32*4882a593Smuzhiyun #define MCLK_ACODEC_TX		25
33*4882a593Smuzhiyun #define MCLK_ACODEC_RX		26
34*4882a593Smuzhiyun #define CLK_CORE_CRYPTO		27
35*4882a593Smuzhiyun #define CLK_PKA_CRYPTO		28
36*4882a593Smuzhiyun #define ACLK_CRYPTO		29
37*4882a593Smuzhiyun #define HCLK_CRYPTO		30
38*4882a593Smuzhiyun #define ACLK_DECOM		31
39*4882a593Smuzhiyun #define PCLK_DECOM		32
40*4882a593Smuzhiyun #define DCLK_DECOM		33
41*4882a593Smuzhiyun #define ACLK_DMAC		34
42*4882a593Smuzhiyun #define PCLK_DSM		35
43*4882a593Smuzhiyun #define MCLK_DSM		36
44*4882a593Smuzhiyun #define CCLK_SRC_EMMC		37
45*4882a593Smuzhiyun #define HCLK_EMMC		38
46*4882a593Smuzhiyun #define PCLK_GPIO4		39
47*4882a593Smuzhiyun #define DBCLK_GPIO4		40
48*4882a593Smuzhiyun #define PCLK_I2C0		41
49*4882a593Smuzhiyun #define CLK_I2C0		42
50*4882a593Smuzhiyun #define PCLK_I2C2		43
51*4882a593Smuzhiyun #define CLK_I2C2		44
52*4882a593Smuzhiyun #define PCLK_I2C3		45
53*4882a593Smuzhiyun #define CLK_I2C3		46
54*4882a593Smuzhiyun #define PCLK_I2C4		47
55*4882a593Smuzhiyun #define CLK_I2C4		48
56*4882a593Smuzhiyun #define HCLK_I2S0		49
57*4882a593Smuzhiyun #define PCLK_DFT2APB		50
58*4882a593Smuzhiyun #define HCLK_IVE		51
59*4882a593Smuzhiyun #define ACLK_IVE		52
60*4882a593Smuzhiyun #define PCLK_PWM0_PERI		53
61*4882a593Smuzhiyun #define CLK_PWM0_PERI		54
62*4882a593Smuzhiyun #define CLK_CAPTURE_PWM0_PERI	55
63*4882a593Smuzhiyun #define PCLK_PERI_ROOT		56
64*4882a593Smuzhiyun #define ACLK_PERI_ROOT		57
65*4882a593Smuzhiyun #define HCLK_PERI_ROOT		58
66*4882a593Smuzhiyun #define CLK_TIMER_ROOT		59
67*4882a593Smuzhiyun #define ACLK_BUS_ROOT		60
68*4882a593Smuzhiyun #define HCLK_SFC		61
69*4882a593Smuzhiyun #define SCLK_SFC		62
70*4882a593Smuzhiyun #define PCLK_UART0		63
71*4882a593Smuzhiyun #define CLK_PVTM_CORE		64
72*4882a593Smuzhiyun #define PCLK_UART1		65
73*4882a593Smuzhiyun #define CLK_CORE_MCU_RTC	66
74*4882a593Smuzhiyun #define PCLK_PWM1_PERI		67
75*4882a593Smuzhiyun #define CLK_PWM1_PERI		68
76*4882a593Smuzhiyun #define CLK_CAPTURE_PWM1_PERI	69
77*4882a593Smuzhiyun #define PCLK_PWM2_PERI		70
78*4882a593Smuzhiyun #define CLK_PWM2_PERI		71
79*4882a593Smuzhiyun #define CLK_CAPTURE_PWM2_PERI	72
80*4882a593Smuzhiyun #define HCLK_BOOTROM		73
81*4882a593Smuzhiyun #define HCLK_SAI		74
82*4882a593Smuzhiyun #define MCLK_SAI		75
83*4882a593Smuzhiyun #define PCLK_SARADC		76
84*4882a593Smuzhiyun #define CLK_SARADC		77
85*4882a593Smuzhiyun #define PCLK_SPI1		78
86*4882a593Smuzhiyun #define CLK_SPI1		79
87*4882a593Smuzhiyun #define PCLK_STIMER		80
88*4882a593Smuzhiyun #define CLK_STIMER0		81
89*4882a593Smuzhiyun #define CLK_STIMER1		82
90*4882a593Smuzhiyun #define PCLK_TIMER		83
91*4882a593Smuzhiyun #define CLK_TIMER0		84
92*4882a593Smuzhiyun #define CLK_TIMER1		85
93*4882a593Smuzhiyun #define CLK_TIMER2		86
94*4882a593Smuzhiyun #define CLK_TIMER3		87
95*4882a593Smuzhiyun #define CLK_TIMER4		88
96*4882a593Smuzhiyun #define CLK_TIMER5		89
97*4882a593Smuzhiyun #define HCLK_TRNG_NS		90
98*4882a593Smuzhiyun #define HCLK_TRNG_S		91
99*4882a593Smuzhiyun #define PCLK_UART2		92
100*4882a593Smuzhiyun #define HCLK_CPU		93
101*4882a593Smuzhiyun #define PCLK_UART3		94
102*4882a593Smuzhiyun #define CLK_CORE_MCU		95
103*4882a593Smuzhiyun #define PCLK_UART4		96
104*4882a593Smuzhiyun #define PCLK_DDR_HWLP		97
105*4882a593Smuzhiyun #define PCLK_UART5		98
106*4882a593Smuzhiyun #define ACLK_USBOTG		100
107*4882a593Smuzhiyun #define CLK_REF_USBOTG		101
108*4882a593Smuzhiyun #define CLK_UTMI_USBOTG		102
109*4882a593Smuzhiyun #define PCLK_USBPHY		103
110*4882a593Smuzhiyun #define CLK_REF_USBPHY		104
111*4882a593Smuzhiyun #define PCLK_WDT_NS		105
112*4882a593Smuzhiyun #define TCLK_WDT_NS		106
113*4882a593Smuzhiyun #define PCLK_WDT_S		107
114*4882a593Smuzhiyun #define TCLK_WDT_S		108
115*4882a593Smuzhiyun #define CLK_DDR_FAIL_SAFE	109
116*4882a593Smuzhiyun #define XIN_OSC0_DIV		110
117*4882a593Smuzhiyun #define CLK_DEEPSLOW		111
118*4882a593Smuzhiyun #define PCLK_PMU_GPIO0		112
119*4882a593Smuzhiyun #define DBCLK_PMU_GPIO0		113
120*4882a593Smuzhiyun #define CLK_PMU			114
121*4882a593Smuzhiyun #define PCLK_PMU		115
122*4882a593Smuzhiyun #define PCLK_PMU_HP_TIMER	116
123*4882a593Smuzhiyun #define CLK_PMU_HP_TIMER	117
124*4882a593Smuzhiyun #define CLK_PMU_32K_HP_TIMER	118
125*4882a593Smuzhiyun #define PCLK_I2C1		119
126*4882a593Smuzhiyun #define CLK_I2C1		120
127*4882a593Smuzhiyun #define PCLK_PMU_IOC		121
128*4882a593Smuzhiyun #define PCLK_PMU_MAILBOX	122
129*4882a593Smuzhiyun #define CLK_PMU_MCU		123
130*4882a593Smuzhiyun #define CLK_PMU_MCU_RTC		124
131*4882a593Smuzhiyun #define CLK_PMU_MCU_JTAG	125
132*4882a593Smuzhiyun #define CLK_PVTM_PMU		126
133*4882a593Smuzhiyun #define PCLK_PVTM_PMU		127
134*4882a593Smuzhiyun #define CLK_REFOUT		128
135*4882a593Smuzhiyun #define CLK_100M_PMU		129
136*4882a593Smuzhiyun #define PCLK_PMU_ROOT		130
137*4882a593Smuzhiyun #define HCLK_PMU_ROOT		131
138*4882a593Smuzhiyun #define HCLK_PMU_SRAM		132
139*4882a593Smuzhiyun #define PCLK_PMU_WDT		133
140*4882a593Smuzhiyun #define TCLK_PMU_WDT		134
141*4882a593Smuzhiyun #define CLK_DFICTRL		135
142*4882a593Smuzhiyun #define CLK_DDRMON		136
143*4882a593Smuzhiyun #define CLK_DDR_PHY		137
144*4882a593Smuzhiyun #define ACLK_DDRC		138
145*4882a593Smuzhiyun #define CLK_CORE_DDRC_SRC	139
146*4882a593Smuzhiyun #define CLK_CORE_DDRC		140
147*4882a593Smuzhiyun #define CLK_50M_SRC		141
148*4882a593Smuzhiyun #define CLK_100M_SRC		142
149*4882a593Smuzhiyun #define CLK_150M_SRC		143
150*4882a593Smuzhiyun #define CLK_200M_SRC		144
151*4882a593Smuzhiyun #define CLK_250M_SRC		145
152*4882a593Smuzhiyun #define CLK_300M_SRC		146
153*4882a593Smuzhiyun #define CLK_339M_SRC		147
154*4882a593Smuzhiyun #define CLK_400M_SRC		148
155*4882a593Smuzhiyun #define CLK_450M_SRC		149
156*4882a593Smuzhiyun #define CLK_500M_SRC		150
157*4882a593Smuzhiyun #define CLK_I2S0_8CH_TX_SRC	151
158*4882a593Smuzhiyun #define CLK_I2S0_8CH_TX_FRAC	152
159*4882a593Smuzhiyun #define CLK_I2S0_8CH_TX		153
160*4882a593Smuzhiyun #define CLK_I2S0_8CH_RX_SRC	154
161*4882a593Smuzhiyun #define CLK_I2S0_8CH_RX_FRAC	155
162*4882a593Smuzhiyun #define CLK_I2S0_8CH_RX		156
163*4882a593Smuzhiyun #define I2S0_8CH_MCLKOUT	157
164*4882a593Smuzhiyun #define MCLK_I2S0_8CH_RX	158
165*4882a593Smuzhiyun #define MCLK_I2S0_8CH_TX	159
166*4882a593Smuzhiyun #define CLK_REF_MIPI0_SRC	160
167*4882a593Smuzhiyun #define CLK_REF_MIPI0_FRAC	161
168*4882a593Smuzhiyun #define CLK_REF_MIPI0_OUT	162
169*4882a593Smuzhiyun #define CLK_REF_MIPI1_SRC	163
170*4882a593Smuzhiyun #define CLK_REF_MIPI1_FRAC	164
171*4882a593Smuzhiyun #define MCLK_REF_MIPI0		165
172*4882a593Smuzhiyun #define MCLK_REF_MIPI1		166
173*4882a593Smuzhiyun #define CLK_REF_MIPI0		167
174*4882a593Smuzhiyun #define CLK_REF_MIPI1		168
175*4882a593Smuzhiyun #define CLK_UART0_SRC		169
176*4882a593Smuzhiyun #define CLK_UART0_FRAC		170
177*4882a593Smuzhiyun #define CLK_UART0		171
178*4882a593Smuzhiyun #define SCLK_UART0		172
179*4882a593Smuzhiyun #define CLK_UART1_SRC		173
180*4882a593Smuzhiyun #define CLK_UART1_FRAC		174
181*4882a593Smuzhiyun #define CLK_UART1		175
182*4882a593Smuzhiyun #define SCLK_UART1		176
183*4882a593Smuzhiyun #define CLK_UART2_SRC		177
184*4882a593Smuzhiyun #define CLK_UART2_FRAC		178
185*4882a593Smuzhiyun #define CLK_UART2		179
186*4882a593Smuzhiyun #define SCLK_UART2		180
187*4882a593Smuzhiyun #define CLK_UART3_SRC		181
188*4882a593Smuzhiyun #define CLK_UART3_FRAC		182
189*4882a593Smuzhiyun #define CLK_UART3		183
190*4882a593Smuzhiyun #define SCLK_UART3		184
191*4882a593Smuzhiyun #define CLK_UART4_SRC		185
192*4882a593Smuzhiyun #define CLK_UART4_FRAC		186
193*4882a593Smuzhiyun #define CLK_UART4		187
194*4882a593Smuzhiyun #define SCLK_UART4		188
195*4882a593Smuzhiyun #define CLK_UART5_SRC		189
196*4882a593Smuzhiyun #define CLK_UART5_FRAC		190
197*4882a593Smuzhiyun #define CLK_UART5		191
198*4882a593Smuzhiyun #define SCLK_UART5		192
199*4882a593Smuzhiyun #define CLK_VICAP_M0_SRC	193
200*4882a593Smuzhiyun #define CLK_VICAP_M0_FRAC	194
201*4882a593Smuzhiyun #define CLK_VICAP_M0		195
202*4882a593Smuzhiyun #define SCLK_VICAP_M0		196
203*4882a593Smuzhiyun #define CLK_VICAP_M1_SRC	197
204*4882a593Smuzhiyun #define CLK_VICAP_M1_FRAC	198
205*4882a593Smuzhiyun #define CLK_VICAP_M1		199
206*4882a593Smuzhiyun #define SCLK_VICAP_M1		200
207*4882a593Smuzhiyun #define DCLK_VOP_SRC		201
208*4882a593Smuzhiyun #define PCLK_CRU		202
209*4882a593Smuzhiyun #define PCLK_TOP_ROOT		203
210*4882a593Smuzhiyun #define PCLK_SPI0		204
211*4882a593Smuzhiyun #define CLK_SPI0		205
212*4882a593Smuzhiyun #define SCLK_IN_SPI0		206
213*4882a593Smuzhiyun #define CLK_UART_DETN_FLT	207
214*4882a593Smuzhiyun #define HCLK_VEPU		208
215*4882a593Smuzhiyun #define ACLK_VEPU		209
216*4882a593Smuzhiyun #define CLK_CORE_VEPU		210
217*4882a593Smuzhiyun #define CLK_CORE_VEPU_DVBM	211
218*4882a593Smuzhiyun #define PCLK_GPIO1		212
219*4882a593Smuzhiyun #define DBCLK_GPIO1		213
220*4882a593Smuzhiyun #define HCLK_VEPU_PP		214
221*4882a593Smuzhiyun #define ACLK_VEPU_PP		215
222*4882a593Smuzhiyun #define HCLK_VEPU_ROOT		216
223*4882a593Smuzhiyun #define ACLK_VEPU_COM_ROOT	217
224*4882a593Smuzhiyun #define ACLK_VEPU_ROOT		218
225*4882a593Smuzhiyun #define PCLK_VEPU_ROOT		219
226*4882a593Smuzhiyun #define PCLK_VICAP_VEPU		220
227*4882a593Smuzhiyun #define PCLK_CSIHOST0		221
228*4882a593Smuzhiyun #define CLK_RXBYTECLKHS_0	222
229*4882a593Smuzhiyun #define PCLK_CSIHOST1		223
230*4882a593Smuzhiyun #define CLK_RXBYTECLKHS_1	224
231*4882a593Smuzhiyun #define PCLK_GPIO3		225
232*4882a593Smuzhiyun #define DBCLK_GPIO3		226
233*4882a593Smuzhiyun #define HCLK_ISP3P2		227
234*4882a593Smuzhiyun #define ACLK_ISP3P2		228
235*4882a593Smuzhiyun #define CLK_CORE_ISP3P2		229
236*4882a593Smuzhiyun #define PCLK_MIPICSIPHY		230
237*4882a593Smuzhiyun #define CCLK_SRC_SDMMC		231
238*4882a593Smuzhiyun #define HCLK_SDMMC		232
239*4882a593Smuzhiyun #define CLK_SDMMC_DETN_FLT	233
240*4882a593Smuzhiyun #define HCLK_VI_ROOT		234
241*4882a593Smuzhiyun #define ACLK_VI_ROOT		235
242*4882a593Smuzhiyun #define PCLK_VI_ROOT		236
243*4882a593Smuzhiyun #define PCLK_VI_RTC_ROOT	237
244*4882a593Smuzhiyun #define PCLK_VI_RTC_TEST	238
245*4882a593Smuzhiyun #define PCLK_VI_RTC_PHY		239
246*4882a593Smuzhiyun #define DCLK_VICAP		240
247*4882a593Smuzhiyun #define PCLK_VICAP		241
248*4882a593Smuzhiyun #define ACLK_VICAP		242
249*4882a593Smuzhiyun #define HCLK_VICAP		243
250*4882a593Smuzhiyun #define I0CLK_VICAP		244
251*4882a593Smuzhiyun #define I1CLK_VICAP		245
252*4882a593Smuzhiyun #define RX0PCLK_VICAP		246
253*4882a593Smuzhiyun #define RX1PCLK_VICAP		247
254*4882a593Smuzhiyun #define ISP0CLK_VICAP		248
255*4882a593Smuzhiyun #define PCLK_GPIO2		249
256*4882a593Smuzhiyun #define DBCLK_GPIO2		250
257*4882a593Smuzhiyun #define ACLK_MAC		251
258*4882a593Smuzhiyun #define PCLK_MAC		252
259*4882a593Smuzhiyun #define CLK_GMAC0_50M_O		253
260*4882a593Smuzhiyun #define CLK_GMAC0_TX_50M_O	254
261*4882a593Smuzhiyun #define CLK_GMAC0_REF_50M	255
262*4882a593Smuzhiyun #define CLK_GMAC0_TX_50M	256
263*4882a593Smuzhiyun #define CLK_GMAC0_RX_50M	257
264*4882a593Smuzhiyun #define ACLK_MAC_ROOT		258
265*4882a593Smuzhiyun #define CLK_MACPHY		259
266*4882a593Smuzhiyun #define CLK_OTPC_ARB		260
267*4882a593Smuzhiyun #define PCLK_OTPC_NS		261
268*4882a593Smuzhiyun #define CLK_SBPI_OTPC_NS	262
269*4882a593Smuzhiyun #define CLK_USER_OTPC_NS	263
270*4882a593Smuzhiyun #define PCLK_OTPC_S		264
271*4882a593Smuzhiyun #define CLK_SBPI_OTPC_S		265
272*4882a593Smuzhiyun #define CLK_USER_OTPC_S		266
273*4882a593Smuzhiyun #define PCLK_OTP_MASK		267
274*4882a593Smuzhiyun #define CLK_PMC_OTP		268
275*4882a593Smuzhiyun #define HCLK_RGA2E		269
276*4882a593Smuzhiyun #define ACLK_RGA2E		270
277*4882a593Smuzhiyun #define CLK_CORE_RGA2E		271
278*4882a593Smuzhiyun #define CCLK_SRC_SDIO		272
279*4882a593Smuzhiyun #define HCLK_SDIO		273
280*4882a593Smuzhiyun #define PCLK_TSADC		274
281*4882a593Smuzhiyun #define CLK_TSADC		275
282*4882a593Smuzhiyun #define CLK_TSADC_TSEN		276
283*4882a593Smuzhiyun #define ACLK_VO_ROOT		277
284*4882a593Smuzhiyun #define HCLK_VO_ROOT		278
285*4882a593Smuzhiyun #define PCLK_VO_ROOT		279
286*4882a593Smuzhiyun #define ACLK_VOP_ROOT		280
287*4882a593Smuzhiyun #define HCLK_VOP		281
288*4882a593Smuzhiyun #define DCLK_VOP		282
289*4882a593Smuzhiyun #define ACLK_VOP		283
290*4882a593Smuzhiyun #define CLK_RTC_32K		284
291*4882a593Smuzhiyun #define PCLK_MAILBOX		291
292*4882a593Smuzhiyun 
293*4882a593Smuzhiyun #define CLK_NR_CLKS		(PCLK_MAILBOX + 1)
294*4882a593Smuzhiyun 
295*4882a593Smuzhiyun #define SCLK_EMMC_DRV		1
296*4882a593Smuzhiyun #define SCLK_EMMC_SAMPLE	2
297*4882a593Smuzhiyun #define SCLK_SDMMC_DRV		3
298*4882a593Smuzhiyun #define SCLK_SDMMC_SAMPLE	4
299*4882a593Smuzhiyun #define SCLK_SDIO_DRV		5
300*4882a593Smuzhiyun #define SCLK_SDIO_SAMPLE	6
301*4882a593Smuzhiyun 
302*4882a593Smuzhiyun #define CLK_NR_GRF_CLKS		(SCLK_SDIO_SAMPLE + 1)
303*4882a593Smuzhiyun 
304*4882a593Smuzhiyun /********Name=PMUSOFTRST_CON00,Offset=0xA00********/
305*4882a593Smuzhiyun #define SRST_P_I2C1		3
306*4882a593Smuzhiyun #define SRST_I2C1		4
307*4882a593Smuzhiyun #define SRST_H_PMU_BIU		6
308*4882a593Smuzhiyun #define SRST_P_PMU_BIU		7
309*4882a593Smuzhiyun #define SRST_H_PMU_SRAM		8
310*4882a593Smuzhiyun #define SRST_PMU_MCU		9
311*4882a593Smuzhiyun #define SRST_PMU_MCU_PWRUP	10
312*4882a593Smuzhiyun #define SRST_PMU_MCU_CPU	11
313*4882a593Smuzhiyun #define SRST_T_PMU_MCU_CPU	12
314*4882a593Smuzhiyun /********Name=PMUSOFTRST_CON01,Offset=0xA04********/
315*4882a593Smuzhiyun #define SRST_P_PMU_GPIO0	18
316*4882a593Smuzhiyun #define SRST_PMU_GPIO0		19
317*4882a593Smuzhiyun #define SRST_PVTM_PMU		20
318*4882a593Smuzhiyun #define SRST_P_PVTM_PMU		21
319*4882a593Smuzhiyun #define SRST_DDR_FAIL_SAFE	31
320*4882a593Smuzhiyun /********Name=PMUSOFTRST_CON02,Offset=0xA08********/
321*4882a593Smuzhiyun #define SRST_P_PMU_HP_TIMER	32
322*4882a593Smuzhiyun #define SRST_PMU_HP_TIMER	33
323*4882a593Smuzhiyun #define SRST_PMU_32K_HP_TIMER	34
324*4882a593Smuzhiyun #define SRST_P_PMU_IOC		35
325*4882a593Smuzhiyun #define SRST_P_PMU_CRU		36
326*4882a593Smuzhiyun #define SRST_P_PMU_GRF		37
327*4882a593Smuzhiyun #define SRST_P_PMU_SGRF		38
328*4882a593Smuzhiyun #define SRST_P_PMU_SGRF_REMAP	39
329*4882a593Smuzhiyun #define SRST_P_PMU_WDT		40
330*4882a593Smuzhiyun #define SRST_T_PMU_WDT		41
331*4882a593Smuzhiyun #define SRST_P_PMU_MAILBOX	42
332*4882a593Smuzhiyun #define SRST_WRITE_ENABLE	48
333*4882a593Smuzhiyun /********Name=SOFTRST_CON02,Offset=0x10A08********/
334*4882a593Smuzhiyun #define SRST_REF_PVTPLL_0	262183
335*4882a593Smuzhiyun #define SRST_REF_PVTPLL_1	262184
336*4882a593Smuzhiyun #define SRST_P_CRU		262186
337*4882a593Smuzhiyun #define SRST_P_CRU_BIU		262187
338*4882a593Smuzhiyun /********Name=PERISOFTRST_CON00,Offset=0x12A00********/
339*4882a593Smuzhiyun #define SRST_P_PERI_BIU		294916
340*4882a593Smuzhiyun #define SRST_A_PERI_BIU		294917
341*4882a593Smuzhiyun #define SRST_H_PERI_BIU		294918
342*4882a593Smuzhiyun #define SRST_H_BOOTROM		294919
343*4882a593Smuzhiyun #define SRST_P_TIMER		294920
344*4882a593Smuzhiyun #define SRST_TIMER0		294921
345*4882a593Smuzhiyun #define SRST_TIMER1		294922
346*4882a593Smuzhiyun #define SRST_TIMER2		294923
347*4882a593Smuzhiyun #define SRST_TIMER3		294924
348*4882a593Smuzhiyun #define SRST_TIMER4		294925
349*4882a593Smuzhiyun #define SRST_TIMER5		294926
350*4882a593Smuzhiyun #define SRST_P_STIMER		294927
351*4882a593Smuzhiyun /********Name=PERISOFTRST_CON01,Offset=0x12A04********/
352*4882a593Smuzhiyun #define SRST_STIMER0		294928
353*4882a593Smuzhiyun #define SRST_STIMER1		294929
354*4882a593Smuzhiyun #define SRST_P_WDT_NS		294930
355*4882a593Smuzhiyun #define SRST_T_WDT_NS		294931
356*4882a593Smuzhiyun #define SRST_P_WDT_S		294932
357*4882a593Smuzhiyun #define SRST_T_WDT_S		294933
358*4882a593Smuzhiyun #define SRST_P_I2C0		294934
359*4882a593Smuzhiyun #define SRST_I2C0		294935
360*4882a593Smuzhiyun #define SRST_P_I2C2		294938
361*4882a593Smuzhiyun #define SRST_I2C2		294939
362*4882a593Smuzhiyun #define SRST_P_I2C3		294940
363*4882a593Smuzhiyun #define SRST_I2C3		294941
364*4882a593Smuzhiyun #define SRST_P_I2C4		294942
365*4882a593Smuzhiyun #define SRST_I2C4		294943
366*4882a593Smuzhiyun /********Name=PERISOFTRST_CON02,Offset=0x12A08********/
367*4882a593Smuzhiyun #define SRST_P_GPIO4		294944
368*4882a593Smuzhiyun #define SRST_GPIO4		294945
369*4882a593Smuzhiyun #define SRST_P_PERI_IOC		294946
370*4882a593Smuzhiyun #define SRST_P_UART2		294947
371*4882a593Smuzhiyun #define SRST_S_UART2		294950
372*4882a593Smuzhiyun #define SRST_P_UART3		294951
373*4882a593Smuzhiyun #define SRST_S_UART3		294954
374*4882a593Smuzhiyun #define SRST_P_UART4		294955
375*4882a593Smuzhiyun #define SRST_S_UART4		294958
376*4882a593Smuzhiyun #define SRST_P_UART5		294959
377*4882a593Smuzhiyun /********Name=PERISOFTRST_CON03,Offset=0x12A0C********/
378*4882a593Smuzhiyun #define SRST_S_UART5		294962
379*4882a593Smuzhiyun #define SRST_P_SARADC		294963
380*4882a593Smuzhiyun #define SRST_SARADC		294964
381*4882a593Smuzhiyun #define SRST_SARADC_PHY		294965
382*4882a593Smuzhiyun #define SRST_P_SPI1		294966
383*4882a593Smuzhiyun #define SRST_SPI1		294967
384*4882a593Smuzhiyun #define SRST_H_TRNG_NS		294969
385*4882a593Smuzhiyun #define SRST_H_TRNG_S		294970
386*4882a593Smuzhiyun #define SRST_CORE_CRYPTO	294971
387*4882a593Smuzhiyun #define SRST_PKA_CRYPTO		294972
388*4882a593Smuzhiyun #define SRST_A_CRYPTO		294973
389*4882a593Smuzhiyun #define SRST_H_CRYPTO		294974
390*4882a593Smuzhiyun #define SRST_P_PWM1_PERI	294975
391*4882a593Smuzhiyun /********Name=PERISOFTRST_CON04,Offset=0x12A10********/
392*4882a593Smuzhiyun #define SRST_PWM1_PERI		294976
393*4882a593Smuzhiyun #define SRST_P_PWM2_PERI	294978
394*4882a593Smuzhiyun #define SRST_PWM2_PERI		294979
395*4882a593Smuzhiyun #define SRST_P_PERI_GRF		294981
396*4882a593Smuzhiyun #define SRST_P_PERI_CRU		294982
397*4882a593Smuzhiyun #define SRST_A_USBOTG		294983
398*4882a593Smuzhiyun #define SRST_A_BUS_BIU		294986
399*4882a593Smuzhiyun #define SRST_H_EMMC		294989
400*4882a593Smuzhiyun #define SRST_H_SFC		294990
401*4882a593Smuzhiyun /********Name=PERISOFTRST_CON05,Offset=0x12A14********/
402*4882a593Smuzhiyun #define SRST_S_SFC		294992
403*4882a593Smuzhiyun #define SRST_P_USBPHY		294993
404*4882a593Smuzhiyun #define SRST_USBPHY_POR		294994
405*4882a593Smuzhiyun #define SRST_USBPHY_OTG		294995
406*4882a593Smuzhiyun #define SRST_A_DMAC		295000
407*4882a593Smuzhiyun #define SRST_A_DECOM		295001
408*4882a593Smuzhiyun #define SRST_P_DECOM		295002
409*4882a593Smuzhiyun #define SRST_D_DECOM		295003
410*4882a593Smuzhiyun #define SRST_P_PERI_SGRF	295004
411*4882a593Smuzhiyun #define SRST_H_SAI		295005
412*4882a593Smuzhiyun #define SRST_M_SAI		295006
413*4882a593Smuzhiyun #define SRST_M_I2S0_8CH_TX	295007
414*4882a593Smuzhiyun /********Name=PERISOFTRST_CON06,Offset=0x12A18********/
415*4882a593Smuzhiyun #define SRST_H_I2S0		295008
416*4882a593Smuzhiyun #define SRST_M_DSM		295009
417*4882a593Smuzhiyun #define SRST_P_DSM		295010
418*4882a593Smuzhiyun #define SRST_P_ACODEC		295011
419*4882a593Smuzhiyun #define SRST_M_I2S0_8CH_RX	295014
420*4882a593Smuzhiyun #define SRST_P_DFT2APB		295015
421*4882a593Smuzhiyun #define SRST_H_IVE		295017
422*4882a593Smuzhiyun #define SRST_A_IVE		295018
423*4882a593Smuzhiyun #define SRST_P_UART0		295019
424*4882a593Smuzhiyun #define SRST_S_UART0		295022
425*4882a593Smuzhiyun #define SRST_P_UART1		295023
426*4882a593Smuzhiyun /********Name=PERISOFTRST_CON07,Offset=0x12A1C********/
427*4882a593Smuzhiyun #define SRST_S_UART1		295026
428*4882a593Smuzhiyun #define SRST_P_PWM0_PERI	295027
429*4882a593Smuzhiyun #define SRST_PWM0_PERI		295028
430*4882a593Smuzhiyun /********Name=VISOFTRST_CON00,Offset=0x14A00********/
431*4882a593Smuzhiyun #define SRST_H_VI_BIU		327684
432*4882a593Smuzhiyun #define SRST_A_VI_BIU		327685
433*4882a593Smuzhiyun #define SRST_P_VI_BIU		327686
434*4882a593Smuzhiyun #define SRST_CORE_ISP3P2	327689
435*4882a593Smuzhiyun #define SRST_D_VICAP		327690
436*4882a593Smuzhiyun #define SRST_P_VICAP		327691
437*4882a593Smuzhiyun #define SRST_A_VICAP		327692
438*4882a593Smuzhiyun #define SRST_H_VICAP		327693
439*4882a593Smuzhiyun #define SRST_VICAP_I0		327694
440*4882a593Smuzhiyun #define SRST_VICAP_I1		327695
441*4882a593Smuzhiyun /********Name=VISOFTRST_CON01,Offset=0x14A04********/
442*4882a593Smuzhiyun #define SRST_VICAP_RX0		327696
443*4882a593Smuzhiyun #define SRST_VICAP_RX1		327697
444*4882a593Smuzhiyun #define SRST_VICAP_ISP0		327698
445*4882a593Smuzhiyun #define SRST_P_CSIHOST0		327700
446*4882a593Smuzhiyun #define SRST_P_CSIHOST1		327702
447*4882a593Smuzhiyun #define SRST_H_SDMMC		327708
448*4882a593Smuzhiyun #define SRST_SDMMC_DETN_FLT	327709
449*4882a593Smuzhiyun #define SRST_P_MIPICSIPHY	327710
450*4882a593Smuzhiyun #define SRST_P_GPIO3		327711
451*4882a593Smuzhiyun /********Name=VISOFTRST_CON02,Offset=0x14A08********/
452*4882a593Smuzhiyun #define SRST_GPIO3		327712
453*4882a593Smuzhiyun #define SRST_P_VI_IOC		327713
454*4882a593Smuzhiyun #define SRST_P_VI_GRF		327714
455*4882a593Smuzhiyun #define SRST_P_VI_SGRF		327715
456*4882a593Smuzhiyun #define SRST_P_VI_CRU		327716
457*4882a593Smuzhiyun #define SRST_P_VI_RTC_TEST	327717
458*4882a593Smuzhiyun #define SRST_P_VI_RTC_NIU	327719
459*4882a593Smuzhiyun /********Name=NPUSOFTRST_CON00,Offset=0x16A00********/
460*4882a593Smuzhiyun #define SRST_H_NPU_BIU		360451
461*4882a593Smuzhiyun #define SRST_A_NPU_BIU		360452
462*4882a593Smuzhiyun #define SRST_P_NPU_BIU		360453
463*4882a593Smuzhiyun #define SRST_P_NPU_CRU		360454
464*4882a593Smuzhiyun #define SRST_P_NPU_SGRF		360455
465*4882a593Smuzhiyun #define SRST_P_NPU_GRF		360456
466*4882a593Smuzhiyun #define SRST_H_RKNN		360457
467*4882a593Smuzhiyun #define SRST_A_RKNN		360458
468*4882a593Smuzhiyun /********Name=CORESOFTRST_CON00,Offset=0x18A00********/
469*4882a593Smuzhiyun #define SRST_NCOREPORESET	393217
470*4882a593Smuzhiyun #define SRST_NCORESET		393218
471*4882a593Smuzhiyun #define SRST_NDBGRESET		393219
472*4882a593Smuzhiyun #define SRST_NL2RESET		393220
473*4882a593Smuzhiyun #define SRST_A_M_CORE_BIU	393221
474*4882a593Smuzhiyun #define SRST_P_DBG		393222
475*4882a593Smuzhiyun #define SRST_POT_DBG		393223
476*4882a593Smuzhiyun #define SRST_NT_DBG		393224
477*4882a593Smuzhiyun #define SRST_P_CORE_GRF		393227
478*4882a593Smuzhiyun #define SRST_H_CPU_BIU		393228
479*4882a593Smuzhiyun #define SRST_P_CPU_BIU		393229
480*4882a593Smuzhiyun #define SRST_PVTM_CORE		393230
481*4882a593Smuzhiyun #define SRST_P_PVTM_CORE	393231
482*4882a593Smuzhiyun /********Name=CORESOFTRST_CON01,Offset=0x18A04********/
483*4882a593Smuzhiyun #define SRST_REF_PVTPLL_CORE	393232
484*4882a593Smuzhiyun #define SRST_CORE_MCU		393233
485*4882a593Smuzhiyun #define SRST_CORE_MCU_PWRUP	393234
486*4882a593Smuzhiyun #define SRST_CORE_MCU_CPU	393235
487*4882a593Smuzhiyun #define SRST_T_CORE_MCU_CPU	393236
488*4882a593Smuzhiyun #define SRST_MCU_BIU		393237
489*4882a593Smuzhiyun #define SRST_P_MAILBOX		393240
490*4882a593Smuzhiyun #define SRST_P_INTMUX		393241
491*4882a593Smuzhiyun #define SRST_P_CORE_CRU		393242
492*4882a593Smuzhiyun #define SRST_P_CORE_SGRF	393243
493*4882a593Smuzhiyun #define SRST_H_CACHE		393244
494*4882a593Smuzhiyun /********Name=VEPUSOFTRST_CON00,Offset=0x1AA00********/
495*4882a593Smuzhiyun #define SRST_H_VEPU_BIU		425988
496*4882a593Smuzhiyun #define SRST_A_VEPU_BIU		425989
497*4882a593Smuzhiyun #define SRST_A_VEPU_COM_BIU	425990
498*4882a593Smuzhiyun #define SRST_P_VEPU_BIU		425991
499*4882a593Smuzhiyun #define SRST_H_VEPU		425992
500*4882a593Smuzhiyun #define SRST_A_VEPU		425993
501*4882a593Smuzhiyun #define SRST_CORE_VEPU		425994
502*4882a593Smuzhiyun #define SRST_H_VEPU_PP		425995
503*4882a593Smuzhiyun #define SRST_A_VEPU_PP		425996
504*4882a593Smuzhiyun #define SRST_CORE_VEPU_DVBM	425997
505*4882a593Smuzhiyun #define SRST_P_VICAP_VEPU	425998
506*4882a593Smuzhiyun #define SRST_P_GPIO1		425999
507*4882a593Smuzhiyun /********Name=VEPUSOFTRST_CON01,Offset=0x1AA04********/
508*4882a593Smuzhiyun #define SRST_GPIO1		426000
509*4882a593Smuzhiyun #define SRST_P_VEPU_IOC		426001
510*4882a593Smuzhiyun #define SRST_P_SPI0		426002
511*4882a593Smuzhiyun #define SRST_SPI0		426003
512*4882a593Smuzhiyun #define SRST_P_VEPU_CRU		426005
513*4882a593Smuzhiyun #define SRST_P_VEPU_SGRF	426006
514*4882a593Smuzhiyun #define SRST_P_VEPU_GRF		426007
515*4882a593Smuzhiyun #define SRST_UART_DETN_FLT	426008
516*4882a593Smuzhiyun /********Name=VOSOFTRST_CON00,Offset=0x1CA00********/
517*4882a593Smuzhiyun #define SRST_A_VO_BIU		458755
518*4882a593Smuzhiyun #define SRST_H_VO_BIU		458756
519*4882a593Smuzhiyun #define SRST_H_RGA2E		458759
520*4882a593Smuzhiyun #define SRST_A_RGA2E		458760
521*4882a593Smuzhiyun #define SRST_CORE_RGA2E		458761
522*4882a593Smuzhiyun #define SRST_P_VO_GRF		458762
523*4882a593Smuzhiyun #define SRST_A_VOP_BIU		458764
524*4882a593Smuzhiyun #define SRST_H_VOP		458765
525*4882a593Smuzhiyun #define SRST_D_VOP		458766
526*4882a593Smuzhiyun #define SRST_A_VOP		458767
527*4882a593Smuzhiyun /********Name=VOSOFTRST_CON01,Offset=0x1CA04********/
528*4882a593Smuzhiyun #define SRST_P_MAC_BIU		458774
529*4882a593Smuzhiyun #define SRST_A_MAC_BIU		458775
530*4882a593Smuzhiyun #define SRST_A_MAC		458776
531*4882a593Smuzhiyun #define SRST_P_VO_SGRF		458780
532*4882a593Smuzhiyun #define SRST_P_VO_CRU		458781
533*4882a593Smuzhiyun #define SRST_H_SDIO		458783
534*4882a593Smuzhiyun /********Name=VOSOFTRST_CON02,Offset=0x1CA08********/
535*4882a593Smuzhiyun #define SRST_P_TSADC		458784
536*4882a593Smuzhiyun #define SRST_TSADC		458785
537*4882a593Smuzhiyun #define SRST_P_OTPC_NS		458787
538*4882a593Smuzhiyun #define SRST_SBPI_OTPC_NS	458789
539*4882a593Smuzhiyun #define SRST_USER_OTPC_NS	458790
540*4882a593Smuzhiyun #define SRST_P_OTPC_S		458791
541*4882a593Smuzhiyun #define SRST_SBPI_OTPC_S	458793
542*4882a593Smuzhiyun #define SRST_USER_OTPC_S	458794
543*4882a593Smuzhiyun #define SRST_OTPC_ARB		458795
544*4882a593Smuzhiyun #define SRST_MACPHY		458797
545*4882a593Smuzhiyun #define SRST_P_OTP_MASK		458798
546*4882a593Smuzhiyun #define SRST_PMC_OTP		458799
547*4882a593Smuzhiyun /********Name=VOSOFTRST_CON03,Offset=0x1CA0C********/
548*4882a593Smuzhiyun #define SRST_P_GPIO2		458800
549*4882a593Smuzhiyun #define SRST_GPIO2		458801
550*4882a593Smuzhiyun #define SRST_P_VO_IOC		458802
551*4882a593Smuzhiyun /********Name=DDRSOFTRST_CON00,Offset=0x1EA00********/
552*4882a593Smuzhiyun #define SRST_P_DDR_BIU		491522
553*4882a593Smuzhiyun #define SRST_P_DDRC		491525
554*4882a593Smuzhiyun #define SRST_P_DDRMON		491527
555*4882a593Smuzhiyun #define SRST_TIMER_DDRMON	491528
556*4882a593Smuzhiyun #define SRST_P_DFICTRL		491531
557*4882a593Smuzhiyun #define SRST_A_SYS_SHRM		491533
558*4882a593Smuzhiyun #define SRST_A_SHRM_NIU		491534
559*4882a593Smuzhiyun #define SRST_P_DDR_GRF		491535
560*4882a593Smuzhiyun /********Name=DDRSOFTRST_CON01,Offset=0x1EA04********/
561*4882a593Smuzhiyun #define SRST_P_DDR_CRU		491536
562*4882a593Smuzhiyun #define SRST_P_DDR_HWLP		491538
563*4882a593Smuzhiyun #define SRST_P_DDRPHY		491539
564*4882a593Smuzhiyun /********Name=SUBDDRSOFTRST_CON00,Offset=0x1FA00********/
565*4882a593Smuzhiyun #define SRST_MSCH_BIU		507904
566*4882a593Smuzhiyun #define SRST_A_DDRC		507905
567*4882a593Smuzhiyun #define SRST_CORE_DDRC		507907
568*4882a593Smuzhiyun #define SRST_DDRMON		507908
569*4882a593Smuzhiyun #define SRST_DFICTRL		507909
570*4882a593Smuzhiyun #define SRST_DDR_PHY		507910
571*4882a593Smuzhiyun 
572*4882a593Smuzhiyun #endif
573