1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Copyright (c) 2022 Rockchip Electronics Co. Ltd. 4 * Author: Elaine Zhang <zhangqing@rock-chips.com> 5 */ 6 7 #ifndef _DT_BINDINGS_CLK_ROCKCHIP_RV1106_H 8 #define _DT_BINDINGS_CLK_ROCKCHIP_RV1106_H 9 10 /* pll clocks */ 11 #define PLL_APLL 1 12 #define PLL_DPLL 2 13 #define PLL_CPLL 3 14 #define PLL_GPLL 4 15 #define ARMCLK 5 16 17 /* clk (clocks) */ 18 #define PCLK_DDRPHY 11 19 #define PCLK_DDR_ROOT 12 20 #define PCLK_DDRMON 13 21 #define CLK_TIMER_DDRMON 14 22 #define PCLK_DDRC 15 23 #define PCLK_DFICTRL 16 24 #define ACLK_DDR_ROOT 17 25 #define ACLK_SYS_SHRM 18 26 #define HCLK_NPU_ROOT 19 27 #define ACLK_NPU_ROOT 20 28 #define PCLK_NPU_ROOT 21 29 #define HCLK_RKNN 22 30 #define ACLK_RKNN 23 31 #define PCLK_ACODEC 24 32 #define MCLK_ACODEC_TX 25 33 #define MCLK_ACODEC_RX 26 34 #define CLK_CORE_CRYPTO 27 35 #define CLK_PKA_CRYPTO 28 36 #define ACLK_CRYPTO 29 37 #define HCLK_CRYPTO 30 38 #define ACLK_DECOM 31 39 #define PCLK_DECOM 32 40 #define DCLK_DECOM 33 41 #define ACLK_DMAC 34 42 #define PCLK_DSM 35 43 #define MCLK_DSM 36 44 #define CCLK_SRC_EMMC 37 45 #define HCLK_EMMC 38 46 #define PCLK_GPIO4 39 47 #define DBCLK_GPIO4 40 48 #define PCLK_I2C0 41 49 #define CLK_I2C0 42 50 #define PCLK_I2C2 43 51 #define CLK_I2C2 44 52 #define PCLK_I2C3 45 53 #define CLK_I2C3 46 54 #define PCLK_I2C4 47 55 #define CLK_I2C4 48 56 #define HCLK_I2S0 49 57 #define PCLK_DFT2APB 50 58 #define HCLK_IVE 51 59 #define ACLK_IVE 52 60 #define PCLK_PWM0_PERI 53 61 #define CLK_PWM0_PERI 54 62 #define CLK_CAPTURE_PWM0_PERI 55 63 #define PCLK_PERI_ROOT 56 64 #define ACLK_PERI_ROOT 57 65 #define HCLK_PERI_ROOT 58 66 #define CLK_TIMER_ROOT 59 67 #define ACLK_BUS_ROOT 60 68 #define HCLK_SFC 61 69 #define SCLK_SFC 62 70 #define PCLK_UART0 63 71 #define CLK_PVTM_CORE 64 72 #define PCLK_UART1 65 73 #define CLK_CORE_MCU_RTC 66 74 #define PCLK_PWM1_PERI 67 75 #define CLK_PWM1_PERI 68 76 #define CLK_CAPTURE_PWM1_PERI 69 77 #define PCLK_PWM2_PERI 70 78 #define CLK_PWM2_PERI 71 79 #define CLK_CAPTURE_PWM2_PERI 72 80 #define HCLK_BOOTROM 73 81 #define HCLK_SAI 74 82 #define MCLK_SAI 75 83 #define PCLK_SARADC 76 84 #define CLK_SARADC 77 85 #define PCLK_SPI1 78 86 #define CLK_SPI1 79 87 #define PCLK_STIMER 80 88 #define CLK_STIMER0 81 89 #define CLK_STIMER1 82 90 #define PCLK_TIMER 83 91 #define CLK_TIMER0 84 92 #define CLK_TIMER1 85 93 #define CLK_TIMER2 86 94 #define CLK_TIMER3 87 95 #define CLK_TIMER4 88 96 #define CLK_TIMER5 89 97 #define HCLK_TRNG_NS 90 98 #define HCLK_TRNG_S 91 99 #define PCLK_UART2 92 100 #define HCLK_CPU 93 101 #define PCLK_UART3 94 102 #define CLK_CORE_MCU 95 103 #define PCLK_UART4 96 104 #define PCLK_DDR_HWLP 97 105 #define PCLK_UART5 98 106 #define ACLK_USBOTG 100 107 #define CLK_REF_USBOTG 101 108 #define CLK_UTMI_USBOTG 102 109 #define PCLK_USBPHY 103 110 #define CLK_REF_USBPHY 104 111 #define PCLK_WDT_NS 105 112 #define TCLK_WDT_NS 106 113 #define PCLK_WDT_S 107 114 #define TCLK_WDT_S 108 115 #define CLK_DDR_FAIL_SAFE 109 116 #define XIN_OSC0_DIV 110 117 #define CLK_DEEPSLOW 111 118 #define PCLK_PMU_GPIO0 112 119 #define DBCLK_PMU_GPIO0 113 120 #define CLK_PMU 114 121 #define PCLK_PMU 115 122 #define PCLK_PMU_HP_TIMER 116 123 #define CLK_PMU_HP_TIMER 117 124 #define CLK_PMU_32K_HP_TIMER 118 125 #define PCLK_I2C1 119 126 #define CLK_I2C1 120 127 #define PCLK_PMU_IOC 121 128 #define PCLK_PMU_MAILBOX 122 129 #define CLK_PMU_MCU 123 130 #define CLK_PMU_MCU_RTC 124 131 #define CLK_PMU_MCU_JTAG 125 132 #define CLK_PVTM_PMU 126 133 #define PCLK_PVTM_PMU 127 134 #define CLK_REFOUT 128 135 #define CLK_100M_PMU 129 136 #define PCLK_PMU_ROOT 130 137 #define HCLK_PMU_ROOT 131 138 #define HCLK_PMU_SRAM 132 139 #define PCLK_PMU_WDT 133 140 #define TCLK_PMU_WDT 134 141 #define CLK_DFICTRL 135 142 #define CLK_DDRMON 136 143 #define CLK_DDR_PHY 137 144 #define ACLK_DDRC 138 145 #define CLK_CORE_DDRC_SRC 139 146 #define CLK_CORE_DDRC 140 147 #define CLK_50M_SRC 141 148 #define CLK_100M_SRC 142 149 #define CLK_150M_SRC 143 150 #define CLK_200M_SRC 144 151 #define CLK_250M_SRC 145 152 #define CLK_300M_SRC 146 153 #define CLK_339M_SRC 147 154 #define CLK_400M_SRC 148 155 #define CLK_450M_SRC 149 156 #define CLK_500M_SRC 150 157 #define CLK_I2S0_8CH_TX_SRC 151 158 #define CLK_I2S0_8CH_TX_FRAC 152 159 #define CLK_I2S0_8CH_TX 153 160 #define CLK_I2S0_8CH_RX_SRC 154 161 #define CLK_I2S0_8CH_RX_FRAC 155 162 #define CLK_I2S0_8CH_RX 156 163 #define I2S0_8CH_MCLKOUT 157 164 #define MCLK_I2S0_8CH_RX 158 165 #define MCLK_I2S0_8CH_TX 159 166 #define CLK_REF_MIPI0_SRC 160 167 #define CLK_REF_MIPI0_FRAC 161 168 #define CLK_REF_MIPI0_OUT 162 169 #define CLK_REF_MIPI1_SRC 163 170 #define CLK_REF_MIPI1_FRAC 164 171 #define MCLK_REF_MIPI0 165 172 #define MCLK_REF_MIPI1 166 173 #define CLK_REF_MIPI0 167 174 #define CLK_REF_MIPI1 168 175 #define CLK_UART0_SRC 169 176 #define CLK_UART0_FRAC 170 177 #define CLK_UART0 171 178 #define SCLK_UART0 172 179 #define CLK_UART1_SRC 173 180 #define CLK_UART1_FRAC 174 181 #define CLK_UART1 175 182 #define SCLK_UART1 176 183 #define CLK_UART2_SRC 177 184 #define CLK_UART2_FRAC 178 185 #define CLK_UART2 179 186 #define SCLK_UART2 180 187 #define CLK_UART3_SRC 181 188 #define CLK_UART3_FRAC 182 189 #define CLK_UART3 183 190 #define SCLK_UART3 184 191 #define CLK_UART4_SRC 185 192 #define CLK_UART4_FRAC 186 193 #define CLK_UART4 187 194 #define SCLK_UART4 188 195 #define CLK_UART5_SRC 189 196 #define CLK_UART5_FRAC 190 197 #define CLK_UART5 191 198 #define SCLK_UART5 192 199 #define CLK_VICAP_M0_SRC 193 200 #define CLK_VICAP_M0_FRAC 194 201 #define CLK_VICAP_M0 195 202 #define SCLK_VICAP_M0 196 203 #define CLK_VICAP_M1_SRC 197 204 #define CLK_VICAP_M1_FRAC 198 205 #define CLK_VICAP_M1 199 206 #define SCLK_VICAP_M1 200 207 #define DCLK_VOP_SRC 201 208 #define PCLK_CRU 202 209 #define PCLK_TOP_ROOT 203 210 #define PCLK_SPI0 204 211 #define CLK_SPI0 205 212 #define SCLK_IN_SPI0 206 213 #define CLK_UART_DETN_FLT 207 214 #define HCLK_VEPU 208 215 #define ACLK_VEPU 209 216 #define CLK_CORE_VEPU 210 217 #define CLK_CORE_VEPU_DVBM 211 218 #define PCLK_GPIO1 212 219 #define DBCLK_GPIO1 213 220 #define HCLK_VEPU_PP 214 221 #define ACLK_VEPU_PP 215 222 #define HCLK_VEPU_ROOT 216 223 #define ACLK_VEPU_COM_ROOT 217 224 #define ACLK_VEPU_ROOT 218 225 #define PCLK_VEPU_ROOT 219 226 #define PCLK_VICAP_VEPU 220 227 #define PCLK_CSIHOST0 221 228 #define CLK_RXBYTECLKHS_0 222 229 #define PCLK_CSIHOST1 223 230 #define CLK_RXBYTECLKHS_1 224 231 #define PCLK_GPIO3 225 232 #define DBCLK_GPIO3 226 233 #define HCLK_ISP3P2 227 234 #define ACLK_ISP3P2 228 235 #define CLK_CORE_ISP3P2 229 236 #define PCLK_MIPICSIPHY 230 237 #define CCLK_SRC_SDMMC 231 238 #define HCLK_SDMMC 232 239 #define CLK_SDMMC_DETN_FLT 233 240 #define HCLK_VI_ROOT 234 241 #define ACLK_VI_ROOT 235 242 #define PCLK_VI_ROOT 236 243 #define PCLK_VI_RTC_ROOT 237 244 #define PCLK_VI_RTC_TEST 238 245 #define PCLK_VI_RTC_PHY 239 246 #define DCLK_VICAP 240 247 #define PCLK_VICAP 241 248 #define ACLK_VICAP 242 249 #define HCLK_VICAP 243 250 #define I0CLK_VICAP 244 251 #define I1CLK_VICAP 245 252 #define RX0PCLK_VICAP 246 253 #define RX1PCLK_VICAP 247 254 #define ISP0CLK_VICAP 248 255 #define PCLK_GPIO2 249 256 #define DBCLK_GPIO2 250 257 #define ACLK_MAC 251 258 #define PCLK_MAC 252 259 #define CLK_GMAC0_50M_O 253 260 #define CLK_GMAC0_TX_50M_O 254 261 #define CLK_GMAC0_REF_50M 255 262 #define CLK_GMAC0_TX_50M 256 263 #define CLK_GMAC0_RX_50M 257 264 #define ACLK_MAC_ROOT 258 265 #define CLK_MACPHY 259 266 #define CLK_OTPC_ARB 260 267 #define PCLK_OTPC_NS 261 268 #define CLK_SBPI_OTPC_NS 262 269 #define CLK_USER_OTPC_NS 263 270 #define PCLK_OTPC_S 264 271 #define CLK_SBPI_OTPC_S 265 272 #define CLK_USER_OTPC_S 266 273 #define PCLK_OTP_MASK 267 274 #define CLK_PMC_OTP 268 275 #define HCLK_RGA2E 269 276 #define ACLK_RGA2E 270 277 #define CLK_CORE_RGA2E 271 278 #define CCLK_SRC_SDIO 272 279 #define HCLK_SDIO 273 280 #define PCLK_TSADC 274 281 #define CLK_TSADC 275 282 #define CLK_TSADC_TSEN 276 283 #define ACLK_VO_ROOT 277 284 #define HCLK_VO_ROOT 278 285 #define PCLK_VO_ROOT 279 286 #define ACLK_VOP_ROOT 280 287 #define HCLK_VOP 281 288 #define DCLK_VOP 282 289 #define ACLK_VOP 283 290 #define CLK_RTC_32K 284 291 #define PCLK_MAILBOX 291 292 293 #define CLK_NR_CLKS (PCLK_MAILBOX + 1) 294 295 #define SCLK_EMMC_DRV 1 296 #define SCLK_EMMC_SAMPLE 2 297 #define SCLK_SDMMC_DRV 3 298 #define SCLK_SDMMC_SAMPLE 4 299 #define SCLK_SDIO_DRV 5 300 #define SCLK_SDIO_SAMPLE 6 301 302 #define CLK_NR_GRF_CLKS (SCLK_SDIO_SAMPLE + 1) 303 304 /********Name=PMUSOFTRST_CON00,Offset=0xA00********/ 305 #define SRST_P_I2C1 3 306 #define SRST_I2C1 4 307 #define SRST_H_PMU_BIU 6 308 #define SRST_P_PMU_BIU 7 309 #define SRST_H_PMU_SRAM 8 310 #define SRST_PMU_MCU 9 311 #define SRST_PMU_MCU_PWRUP 10 312 #define SRST_PMU_MCU_CPU 11 313 #define SRST_T_PMU_MCU_CPU 12 314 /********Name=PMUSOFTRST_CON01,Offset=0xA04********/ 315 #define SRST_P_PMU_GPIO0 18 316 #define SRST_PMU_GPIO0 19 317 #define SRST_PVTM_PMU 20 318 #define SRST_P_PVTM_PMU 21 319 #define SRST_DDR_FAIL_SAFE 31 320 /********Name=PMUSOFTRST_CON02,Offset=0xA08********/ 321 #define SRST_P_PMU_HP_TIMER 32 322 #define SRST_PMU_HP_TIMER 33 323 #define SRST_PMU_32K_HP_TIMER 34 324 #define SRST_P_PMU_IOC 35 325 #define SRST_P_PMU_CRU 36 326 #define SRST_P_PMU_GRF 37 327 #define SRST_P_PMU_SGRF 38 328 #define SRST_P_PMU_SGRF_REMAP 39 329 #define SRST_P_PMU_WDT 40 330 #define SRST_T_PMU_WDT 41 331 #define SRST_P_PMU_MAILBOX 42 332 #define SRST_WRITE_ENABLE 48 333 /********Name=SOFTRST_CON02,Offset=0x10A08********/ 334 #define SRST_REF_PVTPLL_0 262183 335 #define SRST_REF_PVTPLL_1 262184 336 #define SRST_P_CRU 262186 337 #define SRST_P_CRU_BIU 262187 338 /********Name=PERISOFTRST_CON00,Offset=0x12A00********/ 339 #define SRST_P_PERI_BIU 294916 340 #define SRST_A_PERI_BIU 294917 341 #define SRST_H_PERI_BIU 294918 342 #define SRST_H_BOOTROM 294919 343 #define SRST_P_TIMER 294920 344 #define SRST_TIMER0 294921 345 #define SRST_TIMER1 294922 346 #define SRST_TIMER2 294923 347 #define SRST_TIMER3 294924 348 #define SRST_TIMER4 294925 349 #define SRST_TIMER5 294926 350 #define SRST_P_STIMER 294927 351 /********Name=PERISOFTRST_CON01,Offset=0x12A04********/ 352 #define SRST_STIMER0 294928 353 #define SRST_STIMER1 294929 354 #define SRST_P_WDT_NS 294930 355 #define SRST_T_WDT_NS 294931 356 #define SRST_P_WDT_S 294932 357 #define SRST_T_WDT_S 294933 358 #define SRST_P_I2C0 294934 359 #define SRST_I2C0 294935 360 #define SRST_P_I2C2 294938 361 #define SRST_I2C2 294939 362 #define SRST_P_I2C3 294940 363 #define SRST_I2C3 294941 364 #define SRST_P_I2C4 294942 365 #define SRST_I2C4 294943 366 /********Name=PERISOFTRST_CON02,Offset=0x12A08********/ 367 #define SRST_P_GPIO4 294944 368 #define SRST_GPIO4 294945 369 #define SRST_P_PERI_IOC 294946 370 #define SRST_P_UART2 294947 371 #define SRST_S_UART2 294950 372 #define SRST_P_UART3 294951 373 #define SRST_S_UART3 294954 374 #define SRST_P_UART4 294955 375 #define SRST_S_UART4 294958 376 #define SRST_P_UART5 294959 377 /********Name=PERISOFTRST_CON03,Offset=0x12A0C********/ 378 #define SRST_S_UART5 294962 379 #define SRST_P_SARADC 294963 380 #define SRST_SARADC 294964 381 #define SRST_SARADC_PHY 294965 382 #define SRST_P_SPI1 294966 383 #define SRST_SPI1 294967 384 #define SRST_H_TRNG_NS 294969 385 #define SRST_H_TRNG_S 294970 386 #define SRST_CORE_CRYPTO 294971 387 #define SRST_PKA_CRYPTO 294972 388 #define SRST_A_CRYPTO 294973 389 #define SRST_H_CRYPTO 294974 390 #define SRST_P_PWM1_PERI 294975 391 /********Name=PERISOFTRST_CON04,Offset=0x12A10********/ 392 #define SRST_PWM1_PERI 294976 393 #define SRST_P_PWM2_PERI 294978 394 #define SRST_PWM2_PERI 294979 395 #define SRST_P_PERI_GRF 294981 396 #define SRST_P_PERI_CRU 294982 397 #define SRST_A_USBOTG 294983 398 #define SRST_A_BUS_BIU 294986 399 #define SRST_H_EMMC 294989 400 #define SRST_H_SFC 294990 401 /********Name=PERISOFTRST_CON05,Offset=0x12A14********/ 402 #define SRST_S_SFC 294992 403 #define SRST_P_USBPHY 294993 404 #define SRST_USBPHY_POR 294994 405 #define SRST_USBPHY_OTG 294995 406 #define SRST_A_DMAC 295000 407 #define SRST_A_DECOM 295001 408 #define SRST_P_DECOM 295002 409 #define SRST_D_DECOM 295003 410 #define SRST_P_PERI_SGRF 295004 411 #define SRST_H_SAI 295005 412 #define SRST_M_SAI 295006 413 #define SRST_M_I2S0_8CH_TX 295007 414 /********Name=PERISOFTRST_CON06,Offset=0x12A18********/ 415 #define SRST_H_I2S0 295008 416 #define SRST_M_DSM 295009 417 #define SRST_P_DSM 295010 418 #define SRST_P_ACODEC 295011 419 #define SRST_M_I2S0_8CH_RX 295014 420 #define SRST_P_DFT2APB 295015 421 #define SRST_H_IVE 295017 422 #define SRST_A_IVE 295018 423 #define SRST_P_UART0 295019 424 #define SRST_S_UART0 295022 425 #define SRST_P_UART1 295023 426 /********Name=PERISOFTRST_CON07,Offset=0x12A1C********/ 427 #define SRST_S_UART1 295026 428 #define SRST_P_PWM0_PERI 295027 429 #define SRST_PWM0_PERI 295028 430 /********Name=VISOFTRST_CON00,Offset=0x14A00********/ 431 #define SRST_H_VI_BIU 327684 432 #define SRST_A_VI_BIU 327685 433 #define SRST_P_VI_BIU 327686 434 #define SRST_CORE_ISP3P2 327689 435 #define SRST_D_VICAP 327690 436 #define SRST_P_VICAP 327691 437 #define SRST_A_VICAP 327692 438 #define SRST_H_VICAP 327693 439 #define SRST_VICAP_I0 327694 440 #define SRST_VICAP_I1 327695 441 /********Name=VISOFTRST_CON01,Offset=0x14A04********/ 442 #define SRST_VICAP_RX0 327696 443 #define SRST_VICAP_RX1 327697 444 #define SRST_VICAP_ISP0 327698 445 #define SRST_P_CSIHOST0 327700 446 #define SRST_P_CSIHOST1 327702 447 #define SRST_H_SDMMC 327708 448 #define SRST_SDMMC_DETN_FLT 327709 449 #define SRST_P_MIPICSIPHY 327710 450 #define SRST_P_GPIO3 327711 451 /********Name=VISOFTRST_CON02,Offset=0x14A08********/ 452 #define SRST_GPIO3 327712 453 #define SRST_P_VI_IOC 327713 454 #define SRST_P_VI_GRF 327714 455 #define SRST_P_VI_SGRF 327715 456 #define SRST_P_VI_CRU 327716 457 #define SRST_P_VI_RTC_TEST 327717 458 #define SRST_P_VI_RTC_NIU 327719 459 /********Name=NPUSOFTRST_CON00,Offset=0x16A00********/ 460 #define SRST_H_NPU_BIU 360451 461 #define SRST_A_NPU_BIU 360452 462 #define SRST_P_NPU_BIU 360453 463 #define SRST_P_NPU_CRU 360454 464 #define SRST_P_NPU_SGRF 360455 465 #define SRST_P_NPU_GRF 360456 466 #define SRST_H_RKNN 360457 467 #define SRST_A_RKNN 360458 468 /********Name=CORESOFTRST_CON00,Offset=0x18A00********/ 469 #define SRST_NCOREPORESET 393217 470 #define SRST_NCORESET 393218 471 #define SRST_NDBGRESET 393219 472 #define SRST_NL2RESET 393220 473 #define SRST_A_M_CORE_BIU 393221 474 #define SRST_P_DBG 393222 475 #define SRST_POT_DBG 393223 476 #define SRST_NT_DBG 393224 477 #define SRST_P_CORE_GRF 393227 478 #define SRST_H_CPU_BIU 393228 479 #define SRST_P_CPU_BIU 393229 480 #define SRST_PVTM_CORE 393230 481 #define SRST_P_PVTM_CORE 393231 482 /********Name=CORESOFTRST_CON01,Offset=0x18A04********/ 483 #define SRST_REF_PVTPLL_CORE 393232 484 #define SRST_CORE_MCU 393233 485 #define SRST_CORE_MCU_PWRUP 393234 486 #define SRST_CORE_MCU_CPU 393235 487 #define SRST_T_CORE_MCU_CPU 393236 488 #define SRST_MCU_BIU 393237 489 #define SRST_P_MAILBOX 393240 490 #define SRST_P_INTMUX 393241 491 #define SRST_P_CORE_CRU 393242 492 #define SRST_P_CORE_SGRF 393243 493 #define SRST_H_CACHE 393244 494 /********Name=VEPUSOFTRST_CON00,Offset=0x1AA00********/ 495 #define SRST_H_VEPU_BIU 425988 496 #define SRST_A_VEPU_BIU 425989 497 #define SRST_A_VEPU_COM_BIU 425990 498 #define SRST_P_VEPU_BIU 425991 499 #define SRST_H_VEPU 425992 500 #define SRST_A_VEPU 425993 501 #define SRST_CORE_VEPU 425994 502 #define SRST_H_VEPU_PP 425995 503 #define SRST_A_VEPU_PP 425996 504 #define SRST_CORE_VEPU_DVBM 425997 505 #define SRST_P_VICAP_VEPU 425998 506 #define SRST_P_GPIO1 425999 507 /********Name=VEPUSOFTRST_CON01,Offset=0x1AA04********/ 508 #define SRST_GPIO1 426000 509 #define SRST_P_VEPU_IOC 426001 510 #define SRST_P_SPI0 426002 511 #define SRST_SPI0 426003 512 #define SRST_P_VEPU_CRU 426005 513 #define SRST_P_VEPU_SGRF 426006 514 #define SRST_P_VEPU_GRF 426007 515 #define SRST_UART_DETN_FLT 426008 516 /********Name=VOSOFTRST_CON00,Offset=0x1CA00********/ 517 #define SRST_A_VO_BIU 458755 518 #define SRST_H_VO_BIU 458756 519 #define SRST_H_RGA2E 458759 520 #define SRST_A_RGA2E 458760 521 #define SRST_CORE_RGA2E 458761 522 #define SRST_P_VO_GRF 458762 523 #define SRST_A_VOP_BIU 458764 524 #define SRST_H_VOP 458765 525 #define SRST_D_VOP 458766 526 #define SRST_A_VOP 458767 527 /********Name=VOSOFTRST_CON01,Offset=0x1CA04********/ 528 #define SRST_P_MAC_BIU 458774 529 #define SRST_A_MAC_BIU 458775 530 #define SRST_A_MAC 458776 531 #define SRST_P_VO_SGRF 458780 532 #define SRST_P_VO_CRU 458781 533 #define SRST_H_SDIO 458783 534 /********Name=VOSOFTRST_CON02,Offset=0x1CA08********/ 535 #define SRST_P_TSADC 458784 536 #define SRST_TSADC 458785 537 #define SRST_P_OTPC_NS 458787 538 #define SRST_SBPI_OTPC_NS 458789 539 #define SRST_USER_OTPC_NS 458790 540 #define SRST_P_OTPC_S 458791 541 #define SRST_SBPI_OTPC_S 458793 542 #define SRST_USER_OTPC_S 458794 543 #define SRST_OTPC_ARB 458795 544 #define SRST_MACPHY 458797 545 #define SRST_P_OTP_MASK 458798 546 #define SRST_PMC_OTP 458799 547 /********Name=VOSOFTRST_CON03,Offset=0x1CA0C********/ 548 #define SRST_P_GPIO2 458800 549 #define SRST_GPIO2 458801 550 #define SRST_P_VO_IOC 458802 551 /********Name=DDRSOFTRST_CON00,Offset=0x1EA00********/ 552 #define SRST_P_DDR_BIU 491522 553 #define SRST_P_DDRC 491525 554 #define SRST_P_DDRMON 491527 555 #define SRST_TIMER_DDRMON 491528 556 #define SRST_P_DFICTRL 491531 557 #define SRST_A_SYS_SHRM 491533 558 #define SRST_A_SHRM_NIU 491534 559 #define SRST_P_DDR_GRF 491535 560 /********Name=DDRSOFTRST_CON01,Offset=0x1EA04********/ 561 #define SRST_P_DDR_CRU 491536 562 #define SRST_P_DDR_HWLP 491538 563 #define SRST_P_DDRPHY 491539 564 /********Name=SUBDDRSOFTRST_CON00,Offset=0x1FA00********/ 565 #define SRST_MSCH_BIU 507904 566 #define SRST_A_DDRC 507905 567 #define SRST_CORE_DDRC 507907 568 #define SRST_DDRMON 507908 569 #define SRST_DFICTRL 507909 570 #define SRST_DDR_PHY 507910 571 572 #endif 573