xref: /OK3568_Linux_fs/u-boot/include/drm_modes.h (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun  * (C) Copyright 2008-2016 Fuzhou Rockchip Electronics Co., Ltd
3*4882a593Smuzhiyun  *
4*4882a593Smuzhiyun  * SPDX-License-Identifier:	GPL-2.0+
5*4882a593Smuzhiyun  */
6*4882a593Smuzhiyun 
7*4882a593Smuzhiyun #ifndef _DRM_MODES_H
8*4882a593Smuzhiyun #define _DRM_MODES_H
9*4882a593Smuzhiyun 
10*4882a593Smuzhiyun #include "fdtdec.h"
11*4882a593Smuzhiyun 
12*4882a593Smuzhiyun #define DRM_DISPLAY_INFO_LEN	32
13*4882a593Smuzhiyun #define DRM_CONNECTOR_NAME_LEN	32
14*4882a593Smuzhiyun #define DRM_DISPLAY_MODE_LEN	32
15*4882a593Smuzhiyun #define DRM_PROP_NAME_LEN	32
16*4882a593Smuzhiyun 
17*4882a593Smuzhiyun #define DRM_MODE_TYPE_BUILTIN	(1<<0)
18*4882a593Smuzhiyun #define DRM_MODE_TYPE_CLOCK_C	((1<<1) | DRM_MODE_TYPE_BUILTIN)
19*4882a593Smuzhiyun #define DRM_MODE_TYPE_CRTC_C	((1<<2) | DRM_MODE_TYPE_BUILTIN)
20*4882a593Smuzhiyun #define DRM_MODE_TYPE_PREFERRED	(1<<3)
21*4882a593Smuzhiyun #define DRM_MODE_TYPE_DEFAULT	(1<<4)
22*4882a593Smuzhiyun #define DRM_MODE_TYPE_USERDEF	(1<<5)
23*4882a593Smuzhiyun #define DRM_MODE_TYPE_DRIVER	(1<<6)
24*4882a593Smuzhiyun 
25*4882a593Smuzhiyun /* Video mode flags */
26*4882a593Smuzhiyun /* bit compatible with the xorg definitions. */
27*4882a593Smuzhiyun #define DRM_MODE_FLAG_PHSYNC			(1 << 0)
28*4882a593Smuzhiyun #define DRM_MODE_FLAG_NHSYNC			(1 << 1)
29*4882a593Smuzhiyun #define DRM_MODE_FLAG_PVSYNC			(1 << 2)
30*4882a593Smuzhiyun #define DRM_MODE_FLAG_NVSYNC			(1 << 3)
31*4882a593Smuzhiyun #define DRM_MODE_FLAG_INTERLACE			(1 << 4)
32*4882a593Smuzhiyun #define DRM_MODE_FLAG_DBLSCAN			(1 << 5)
33*4882a593Smuzhiyun #define DRM_MODE_FLAG_CSYNC			(1 << 6)
34*4882a593Smuzhiyun #define DRM_MODE_FLAG_PCSYNC			(1 << 7)
35*4882a593Smuzhiyun #define DRM_MODE_FLAG_NCSYNC			(1 << 8)
36*4882a593Smuzhiyun #define DRM_MODE_FLAG_HSKEW			(1 << 9) /* hskew provided */
37*4882a593Smuzhiyun #define DRM_MODE_FLAG_BCAST			(1 << 10)
38*4882a593Smuzhiyun #define DRM_MODE_FLAG_PIXMUX			(1 << 11)
39*4882a593Smuzhiyun #define DRM_MODE_FLAG_DBLCLK			(1 << 12)
40*4882a593Smuzhiyun #define DRM_MODE_FLAG_CLKDIV2			(1 << 13)
41*4882a593Smuzhiyun /*
42*4882a593Smuzhiyun  * When adding a new stereo mode don't forget to adjust DRM_MODE_FLAGS_3D_MAX
43*4882a593Smuzhiyun  * (define not exposed to user space).
44*4882a593Smuzhiyun  */
45*4882a593Smuzhiyun #define DRM_MODE_FLAG_3D_MASK			(0x1f << 14)
46*4882a593Smuzhiyun #define  DRM_MODE_FLAG_3D_NONE			(0 << 14)
47*4882a593Smuzhiyun #define  DRM_MODE_FLAG_3D_FRAME_PACKING		(1 << 14)
48*4882a593Smuzhiyun #define  DRM_MODE_FLAG_3D_FIELD_ALTERNATIVE	(2 << 14)
49*4882a593Smuzhiyun #define  DRM_MODE_FLAG_3D_LINE_ALTERNATIVE	(3 << 14)
50*4882a593Smuzhiyun #define  DRM_MODE_FLAG_3D_SIDE_BY_SIDE_FULL	(4 << 14)
51*4882a593Smuzhiyun #define  DRM_MODE_FLAG_3D_L_DEPTH		(5 << 14)
52*4882a593Smuzhiyun #define  DRM_MODE_FLAG_3D_L_DEPTH_GFX_GFX_DEPTH	(6 << 14)
53*4882a593Smuzhiyun #define  DRM_MODE_FLAG_3D_TOP_AND_BOTTOM	(7 << 14)
54*4882a593Smuzhiyun #define  DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF	(8 << 14)
55*4882a593Smuzhiyun 
56*4882a593Smuzhiyun /* Panel Mirror control */
57*4882a593Smuzhiyun #define DRM_MODE_FLAG_XMIRROR			(1<<28)
58*4882a593Smuzhiyun #define DRM_MODE_FLAG_YMIRROR			(1<<29)
59*4882a593Smuzhiyun #define DRM_MODE_FLAG_XYMIRROR			(DRM_MODE_FLAG_XMIRROR | DRM_MODE_FLAG_YMIRROR)
60*4882a593Smuzhiyun 
61*4882a593Smuzhiyun /* Picture aspect ratio options */
62*4882a593Smuzhiyun #define DRM_MODE_PICTURE_ASPECT_NONE		0
63*4882a593Smuzhiyun #define DRM_MODE_PICTURE_ASPECT_4_3		1
64*4882a593Smuzhiyun #define DRM_MODE_PICTURE_ASPECT_16_9		2
65*4882a593Smuzhiyun #define DRM_MODE_PICTURE_ASPECT_64_27		3
66*4882a593Smuzhiyun #define DRM_MODE_PICTURE_ASPECT_256_135		4
67*4882a593Smuzhiyun 
68*4882a593Smuzhiyun /* Aspect ratio flag bitmask (4 bits 22:19) */
69*4882a593Smuzhiyun #define DRM_MODE_FLAG_PIC_AR_MASK		(0x0F << 19)
70*4882a593Smuzhiyun #define  DRM_MODE_FLAG_PIC_AR_NONE \
71*4882a593Smuzhiyun 			(DRM_MODE_PICTURE_ASPECT_NONE << 19)
72*4882a593Smuzhiyun #define  DRM_MODE_FLAG_PIC_AR_4_3 \
73*4882a593Smuzhiyun 			(DRM_MODE_PICTURE_ASPECT_4_3 << 19)
74*4882a593Smuzhiyun #define  DRM_MODE_FLAG_PIC_AR_16_9 \
75*4882a593Smuzhiyun 			(DRM_MODE_PICTURE_ASPECT_16_9 << 19)
76*4882a593Smuzhiyun #define  DRM_MODE_FLAG_PIC_AR_64_27 \
77*4882a593Smuzhiyun 			(DRM_MODE_PICTURE_ASPECT_64_27 << 19)
78*4882a593Smuzhiyun #define  DRM_MODE_FLAG_PIC_AR_256_135 \
79*4882a593Smuzhiyun 			(DRM_MODE_PICTURE_ASPECT_256_135 << 19)
80*4882a593Smuzhiyun 
81*4882a593Smuzhiyun #define DRM_MODE_CONNECTOR_Unknown	0
82*4882a593Smuzhiyun #define DRM_MODE_CONNECTOR_VGA		1
83*4882a593Smuzhiyun #define DRM_MODE_CONNECTOR_DVII		2
84*4882a593Smuzhiyun #define DRM_MODE_CONNECTOR_DVID		3
85*4882a593Smuzhiyun #define DRM_MODE_CONNECTOR_DVIA		4
86*4882a593Smuzhiyun #define DRM_MODE_CONNECTOR_Composite	5
87*4882a593Smuzhiyun #define DRM_MODE_CONNECTOR_SVIDEO	6
88*4882a593Smuzhiyun #define DRM_MODE_CONNECTOR_LVDS		7
89*4882a593Smuzhiyun #define DRM_MODE_CONNECTOR_Component	8
90*4882a593Smuzhiyun #define DRM_MODE_CONNECTOR_9PinDIN	9
91*4882a593Smuzhiyun #define DRM_MODE_CONNECTOR_DisplayPort	10
92*4882a593Smuzhiyun #define DRM_MODE_CONNECTOR_HDMIA	11
93*4882a593Smuzhiyun #define DRM_MODE_CONNECTOR_HDMIB	12
94*4882a593Smuzhiyun #define DRM_MODE_CONNECTOR_TV		13
95*4882a593Smuzhiyun #define DRM_MODE_CONNECTOR_eDP		14
96*4882a593Smuzhiyun #define DRM_MODE_CONNECTOR_VIRTUAL      15
97*4882a593Smuzhiyun #define DRM_MODE_CONNECTOR_DSI		16
98*4882a593Smuzhiyun #define DRM_MODE_CONNECTOR_DPI		17
99*4882a593Smuzhiyun 
100*4882a593Smuzhiyun #define DRM_EDID_PT_HSYNC_POSITIVE (1 << 1)
101*4882a593Smuzhiyun #define DRM_EDID_PT_VSYNC_POSITIVE (1 << 2)
102*4882a593Smuzhiyun #define DRM_EDID_PT_SEPARATE_SYNC  (3 << 3)
103*4882a593Smuzhiyun #define DRM_EDID_PT_STEREO         (1 << 5)
104*4882a593Smuzhiyun #define DRM_EDID_PT_INTERLACED     (1 << 7)
105*4882a593Smuzhiyun 
106*4882a593Smuzhiyun /* see also http://vektor.theorem.ca/graphics/ycbcr/ */
107*4882a593Smuzhiyun enum v4l2_colorspace {
108*4882a593Smuzhiyun 	/*
109*4882a593Smuzhiyun 	 * Default colorspace, i.e. let the driver figure it out.
110*4882a593Smuzhiyun 	 * Can only be used with video capture.
111*4882a593Smuzhiyun 	 */
112*4882a593Smuzhiyun 	V4L2_COLORSPACE_DEFAULT       = 0,
113*4882a593Smuzhiyun 
114*4882a593Smuzhiyun 	/* SMPTE 170M: used for broadcast NTSC/PAL SDTV */
115*4882a593Smuzhiyun 	V4L2_COLORSPACE_SMPTE170M     = 1,
116*4882a593Smuzhiyun 
117*4882a593Smuzhiyun 	/* Obsolete pre-1998 SMPTE 240M HDTV standard, superseded by Rec 709 */
118*4882a593Smuzhiyun 	V4L2_COLORSPACE_SMPTE240M     = 2,
119*4882a593Smuzhiyun 
120*4882a593Smuzhiyun 	/* Rec.709: used for HDTV */
121*4882a593Smuzhiyun 	V4L2_COLORSPACE_REC709        = 3,
122*4882a593Smuzhiyun 
123*4882a593Smuzhiyun 	/*
124*4882a593Smuzhiyun 	 * Deprecated, do not use. No driver will ever return this. This was
125*4882a593Smuzhiyun 	 * based on a misunderstanding of the bt878 datasheet.
126*4882a593Smuzhiyun 	 */
127*4882a593Smuzhiyun 	V4L2_COLORSPACE_BT878         = 4,
128*4882a593Smuzhiyun 
129*4882a593Smuzhiyun 	/*
130*4882a593Smuzhiyun 	 * NTSC 1953 colorspace. This only makes sense when dealing with
131*4882a593Smuzhiyun 	 * really, really old NTSC recordings. Superseded by SMPTE 170M.
132*4882a593Smuzhiyun 	 */
133*4882a593Smuzhiyun 	V4L2_COLORSPACE_470_SYSTEM_M  = 5,
134*4882a593Smuzhiyun 
135*4882a593Smuzhiyun 	/*
136*4882a593Smuzhiyun 	 * EBU Tech 3213 PAL/SECAM colorspace. This only makes sense when
137*4882a593Smuzhiyun 	 * dealing with really old PAL/SECAM recordings. Superseded by
138*4882a593Smuzhiyun 	 * SMPTE 170M.
139*4882a593Smuzhiyun 	 */
140*4882a593Smuzhiyun 	V4L2_COLORSPACE_470_SYSTEM_BG = 6,
141*4882a593Smuzhiyun 
142*4882a593Smuzhiyun 	/*
143*4882a593Smuzhiyun 	 * Effectively shorthand for V4L2_COLORSPACE_SRGB, V4L2_YCBCR_ENC_601
144*4882a593Smuzhiyun 	 * and V4L2_QUANTIZATION_FULL_RANGE. To be used for (Motion-)JPEG.
145*4882a593Smuzhiyun 	 */
146*4882a593Smuzhiyun 	V4L2_COLORSPACE_JPEG          = 7,
147*4882a593Smuzhiyun 
148*4882a593Smuzhiyun 	/* For RGB colorspaces such as produces by most webcams. */
149*4882a593Smuzhiyun 	V4L2_COLORSPACE_SRGB          = 8,
150*4882a593Smuzhiyun 
151*4882a593Smuzhiyun 	/* AdobeRGB colorspace */
152*4882a593Smuzhiyun 	V4L2_COLORSPACE_ADOBERGB      = 9,
153*4882a593Smuzhiyun 
154*4882a593Smuzhiyun 	/* BT.2020 colorspace, used for UHDTV. */
155*4882a593Smuzhiyun 	V4L2_COLORSPACE_BT2020        = 10,
156*4882a593Smuzhiyun 
157*4882a593Smuzhiyun 	/* Raw colorspace: for RAW unprocessed images */
158*4882a593Smuzhiyun 	V4L2_COLORSPACE_RAW           = 11,
159*4882a593Smuzhiyun 
160*4882a593Smuzhiyun 	/* DCI-P3 colorspace, used by cinema projectors */
161*4882a593Smuzhiyun 	V4L2_COLORSPACE_DCI_P3        = 12,
162*4882a593Smuzhiyun };
163*4882a593Smuzhiyun 
164*4882a593Smuzhiyun #define CRTC_INTERLACE_HALVE_V	(1 << 0) /* halve V values for interlacing */
165*4882a593Smuzhiyun #define CRTC_STEREO_DOUBLE	(1 << 1) /* adjust timings for stereo modes */
166*4882a593Smuzhiyun #define CRTC_NO_DBLSCAN		(1 << 2) /* don't adjust doublescan */
167*4882a593Smuzhiyun #define CRTC_NO_VSCAN		(1 << 3) /* don't adjust doublescan */
168*4882a593Smuzhiyun #define CRTC_STEREO_DOUBLE_ONLY	(CRTC_STEREO_DOUBLE | CRTC_NO_DBLSCAN | \
169*4882a593Smuzhiyun 				 CRTC_NO_VSCAN)
170*4882a593Smuzhiyun 
171*4882a593Smuzhiyun #define DRM_MODE_FLAG_3D_MAX	DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF
172*4882a593Smuzhiyun 
173*4882a593Smuzhiyun #define DRM_MODE_MATCH_TIMINGS		(1 << 0)
174*4882a593Smuzhiyun #define DRM_MODE_MATCH_CLOCK		(1 << 1)
175*4882a593Smuzhiyun #define DRM_MODE_MATCH_FLAGS		(1 << 2)
176*4882a593Smuzhiyun #define DRM_MODE_MATCH_3D_FLAGS		(1 << 3)
177*4882a593Smuzhiyun #define DRM_MODE_MATCH_ASPECT_RATIO	(1 << 4)
178*4882a593Smuzhiyun 
179*4882a593Smuzhiyun struct drm_display_mode {
180*4882a593Smuzhiyun 	/* Proposed mode values */
181*4882a593Smuzhiyun 	int clock;		/* in kHz */
182*4882a593Smuzhiyun 	int hdisplay;
183*4882a593Smuzhiyun 	int hsync_start;
184*4882a593Smuzhiyun 	int hsync_end;
185*4882a593Smuzhiyun 	int htotal;
186*4882a593Smuzhiyun 	int vdisplay;
187*4882a593Smuzhiyun 	int vsync_start;
188*4882a593Smuzhiyun 	int vsync_end;
189*4882a593Smuzhiyun 	int vtotal;
190*4882a593Smuzhiyun 	int vrefresh;
191*4882a593Smuzhiyun 	int vscan;
192*4882a593Smuzhiyun 	unsigned int flags;
193*4882a593Smuzhiyun 	int picture_aspect_ratio;
194*4882a593Smuzhiyun 	int hskew;
195*4882a593Smuzhiyun 	unsigned int type;
196*4882a593Smuzhiyun 	/* Actual mode we give to hw */
197*4882a593Smuzhiyun 	int crtc_clock;         /* in KHz */
198*4882a593Smuzhiyun 	int crtc_hdisplay;
199*4882a593Smuzhiyun 	int crtc_hblank_start;
200*4882a593Smuzhiyun 	int crtc_hblank_end;
201*4882a593Smuzhiyun 	int crtc_hsync_start;
202*4882a593Smuzhiyun 	int crtc_hsync_end;
203*4882a593Smuzhiyun 	int crtc_htotal;
204*4882a593Smuzhiyun 	int crtc_hskew;
205*4882a593Smuzhiyun 	int crtc_vdisplay;
206*4882a593Smuzhiyun 	int crtc_vblank_start;
207*4882a593Smuzhiyun 	int crtc_vblank_end;
208*4882a593Smuzhiyun 	int crtc_vsync_start;
209*4882a593Smuzhiyun 	int crtc_vsync_end;
210*4882a593Smuzhiyun 	int crtc_vtotal;
211*4882a593Smuzhiyun 	bool invalid;
212*4882a593Smuzhiyun };
213*4882a593Smuzhiyun 
214*4882a593Smuzhiyun /**
215*4882a593Smuzhiyun  * enum drm_mode_status - hardware support status of a mode
216*4882a593Smuzhiyun  * @MODE_OK: Mode OK
217*4882a593Smuzhiyun  * @MODE_HSYNC: hsync out of range
218*4882a593Smuzhiyun  * @MODE_VSYNC: vsync out of range
219*4882a593Smuzhiyun  * @MODE_H_ILLEGAL: mode has illegal horizontal timings
220*4882a593Smuzhiyun  * @MODE_V_ILLEGAL: mode has illegal vertical timings
221*4882a593Smuzhiyun  * @MODE_BAD_WIDTH: requires an unsupported linepitch
222*4882a593Smuzhiyun  * @MODE_NOMODE: no mode with a matching name
223*4882a593Smuzhiyun  * @MODE_NO_INTERLACE: interlaced mode not supported
224*4882a593Smuzhiyun  * @MODE_NO_DBLESCAN: doublescan mode not supported
225*4882a593Smuzhiyun  * @MODE_NO_VSCAN: multiscan mode not supported
226*4882a593Smuzhiyun  * @MODE_MEM: insufficient video memory
227*4882a593Smuzhiyun  * @MODE_VIRTUAL_X: mode width too large for specified virtual size
228*4882a593Smuzhiyun  * @MODE_VIRTUAL_Y: mode height too large for specified virtual size
229*4882a593Smuzhiyun  * @MODE_MEM_VIRT: insufficient video memory given virtual size
230*4882a593Smuzhiyun  * @MODE_NOCLOCK: no fixed clock available
231*4882a593Smuzhiyun  * @MODE_CLOCK_HIGH: clock required is too high
232*4882a593Smuzhiyun  * @MODE_CLOCK_LOW: clock required is too low
233*4882a593Smuzhiyun  * @MODE_CLOCK_RANGE: clock/mode isn't in a ClockRange
234*4882a593Smuzhiyun  * @MODE_BAD_HVALUE: horizontal timing was out of range
235*4882a593Smuzhiyun  * @MODE_BAD_VVALUE: vertical timing was out of range
236*4882a593Smuzhiyun  * @MODE_BAD_VSCAN: VScan value out of range
237*4882a593Smuzhiyun  * @MODE_HSYNC_NARROW: horizontal sync too narrow
238*4882a593Smuzhiyun  * @MODE_HSYNC_WIDE: horizontal sync too wide
239*4882a593Smuzhiyun  * @MODE_HBLANK_NARROW: horizontal blanking too narrow
240*4882a593Smuzhiyun  * @MODE_HBLANK_WIDE: horizontal blanking too wide
241*4882a593Smuzhiyun  * @MODE_VSYNC_NARROW: vertical sync too narrow
242*4882a593Smuzhiyun  * @MODE_VSYNC_WIDE: vertical sync too wide
243*4882a593Smuzhiyun  * @MODE_VBLANK_NARROW: vertical blanking too narrow
244*4882a593Smuzhiyun  * @MODE_VBLANK_WIDE: vertical blanking too wide
245*4882a593Smuzhiyun  * @MODE_PANEL: exceeds panel dimensions
246*4882a593Smuzhiyun  * @MODE_INTERLACE_WIDTH: width too large for interlaced mode
247*4882a593Smuzhiyun  * @MODE_ONE_WIDTH: only one width is supported
248*4882a593Smuzhiyun  * @MODE_ONE_HEIGHT: only one height is supported
249*4882a593Smuzhiyun  * @MODE_ONE_SIZE: only one resolution is supported
250*4882a593Smuzhiyun  * @MODE_NO_REDUCED: monitor doesn't accept reduced blanking
251*4882a593Smuzhiyun  * @MODE_NO_STEREO: stereo modes not supported
252*4882a593Smuzhiyun  * @MODE_NO_420: ycbcr 420 modes not supported
253*4882a593Smuzhiyun  * @MODE_STALE: mode has become stale
254*4882a593Smuzhiyun  * @MODE_BAD: unspecified reason
255*4882a593Smuzhiyun  * @MODE_ERROR: error condition
256*4882a593Smuzhiyun  *
257*4882a593Smuzhiyun  * This enum is used to filter out modes not supported by the driver/hardware
258*4882a593Smuzhiyun  * combination.
259*4882a593Smuzhiyun  */
260*4882a593Smuzhiyun enum drm_mode_status {
261*4882a593Smuzhiyun 	MODE_OK = 0,
262*4882a593Smuzhiyun 	MODE_HSYNC,
263*4882a593Smuzhiyun 	MODE_VSYNC,
264*4882a593Smuzhiyun 	MODE_H_ILLEGAL,
265*4882a593Smuzhiyun 	MODE_V_ILLEGAL,
266*4882a593Smuzhiyun 	MODE_BAD_WIDTH,
267*4882a593Smuzhiyun 	MODE_NOMODE,
268*4882a593Smuzhiyun 	MODE_NO_INTERLACE,
269*4882a593Smuzhiyun 	MODE_NO_DBLESCAN,
270*4882a593Smuzhiyun 	MODE_NO_VSCAN,
271*4882a593Smuzhiyun 	MODE_MEM,
272*4882a593Smuzhiyun 	MODE_VIRTUAL_X,
273*4882a593Smuzhiyun 	MODE_VIRTUAL_Y,
274*4882a593Smuzhiyun 	MODE_MEM_VIRT,
275*4882a593Smuzhiyun 	MODE_NOCLOCK,
276*4882a593Smuzhiyun 	MODE_CLOCK_HIGH,
277*4882a593Smuzhiyun 	MODE_CLOCK_LOW,
278*4882a593Smuzhiyun 	MODE_CLOCK_RANGE,
279*4882a593Smuzhiyun 	MODE_BAD_HVALUE,
280*4882a593Smuzhiyun 	MODE_BAD_VVALUE,
281*4882a593Smuzhiyun 	MODE_BAD_VSCAN,
282*4882a593Smuzhiyun 	MODE_HSYNC_NARROW,
283*4882a593Smuzhiyun 	MODE_HSYNC_WIDE,
284*4882a593Smuzhiyun 	MODE_HBLANK_NARROW,
285*4882a593Smuzhiyun 	MODE_HBLANK_WIDE,
286*4882a593Smuzhiyun 	MODE_VSYNC_NARROW,
287*4882a593Smuzhiyun 	MODE_VSYNC_WIDE,
288*4882a593Smuzhiyun 	MODE_VBLANK_NARROW,
289*4882a593Smuzhiyun 	MODE_VBLANK_WIDE,
290*4882a593Smuzhiyun 	MODE_PANEL,
291*4882a593Smuzhiyun 	MODE_INTERLACE_WIDTH,
292*4882a593Smuzhiyun 	MODE_ONE_WIDTH,
293*4882a593Smuzhiyun 	MODE_ONE_HEIGHT,
294*4882a593Smuzhiyun 	MODE_ONE_SIZE,
295*4882a593Smuzhiyun 	MODE_NO_REDUCED,
296*4882a593Smuzhiyun 	MODE_NO_STEREO,
297*4882a593Smuzhiyun 	MODE_NO_420,
298*4882a593Smuzhiyun 	MODE_STALE = -3,
299*4882a593Smuzhiyun 	MODE_BAD = -2,
300*4882a593Smuzhiyun 	MODE_ERROR = -1
301*4882a593Smuzhiyun };
302*4882a593Smuzhiyun 
303*4882a593Smuzhiyun /*
304*4882a593Smuzhiyun  * Subsystem independent description of a videomode.
305*4882a593Smuzhiyun  * Can be generated from struct display_timing.
306*4882a593Smuzhiyun  */
307*4882a593Smuzhiyun struct videomode {
308*4882a593Smuzhiyun 	unsigned long pixelclock;	/* pixelclock in Hz */
309*4882a593Smuzhiyun 
310*4882a593Smuzhiyun 	u32 hactive;
311*4882a593Smuzhiyun 	u32 hfront_porch;
312*4882a593Smuzhiyun 	u32 hback_porch;
313*4882a593Smuzhiyun 	u32 hsync_len;
314*4882a593Smuzhiyun 
315*4882a593Smuzhiyun 	u32 vactive;
316*4882a593Smuzhiyun 	u32 vfront_porch;
317*4882a593Smuzhiyun 	u32 vback_porch;
318*4882a593Smuzhiyun 	u32 vsync_len;
319*4882a593Smuzhiyun 
320*4882a593Smuzhiyun 	enum display_flags flags; /* display flags */
321*4882a593Smuzhiyun };
322*4882a593Smuzhiyun 
323*4882a593Smuzhiyun struct drm_display_mode *drm_mode_create(void);
324*4882a593Smuzhiyun void drm_mode_copy(struct drm_display_mode *dst,
325*4882a593Smuzhiyun 		   const struct drm_display_mode *src);
326*4882a593Smuzhiyun void drm_mode_destroy(struct drm_display_mode *mode);
327*4882a593Smuzhiyun bool drm_mode_match(const struct drm_display_mode *mode1,
328*4882a593Smuzhiyun 		    const struct drm_display_mode *mode2,
329*4882a593Smuzhiyun 		    unsigned int match_flags);
330*4882a593Smuzhiyun bool drm_mode_equal(const struct drm_display_mode *mode1,
331*4882a593Smuzhiyun 		    const struct drm_display_mode *mode2);
332*4882a593Smuzhiyun void drm_display_mode_from_videomode(const struct videomode *vm,
333*4882a593Smuzhiyun 				     struct drm_display_mode *dmode);
334*4882a593Smuzhiyun void drm_display_mode_to_videomode(const struct drm_display_mode *dmode,
335*4882a593Smuzhiyun 				   struct videomode *vm);
336*4882a593Smuzhiyun 
337*4882a593Smuzhiyun #endif
338