1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0+ */
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * MIPI DSI Bus
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Copyright (C) 2012-2013, Samsung Electronics, Co., Ltd.
6*4882a593Smuzhiyun * Andrzej Hajda <a.hajda@samsung.com>
7*4882a593Smuzhiyun */
8*4882a593Smuzhiyun
9*4882a593Smuzhiyun #ifndef __DRM_MIPI_DSI_H__
10*4882a593Smuzhiyun #define __DRM_MIPI_DSI_H__
11*4882a593Smuzhiyun
12*4882a593Smuzhiyun #include <mipi_display.h>
13*4882a593Smuzhiyun #include <drm/drm_dsc.h>
14*4882a593Smuzhiyun #include <dm/device.h>
15*4882a593Smuzhiyun
16*4882a593Smuzhiyun struct mipi_dsi_host;
17*4882a593Smuzhiyun struct mipi_dsi_device;
18*4882a593Smuzhiyun
19*4882a593Smuzhiyun /* request ACK from peripheral */
20*4882a593Smuzhiyun #define MIPI_DSI_MSG_REQ_ACK BIT(0)
21*4882a593Smuzhiyun /* use Low Power Mode to transmit message */
22*4882a593Smuzhiyun #define MIPI_DSI_MSG_USE_LPM BIT(1)
23*4882a593Smuzhiyun
24*4882a593Smuzhiyun /**
25*4882a593Smuzhiyun * struct mipi_dsi_msg - read/write DSI buffer
26*4882a593Smuzhiyun * @channel: virtual channel id
27*4882a593Smuzhiyun * @type: payload data type
28*4882a593Smuzhiyun * @flags: flags controlling this message transmission
29*4882a593Smuzhiyun * @tx_len: length of @tx_buf
30*4882a593Smuzhiyun * @tx_buf: data to be written
31*4882a593Smuzhiyun * @rx_len: length of @rx_buf
32*4882a593Smuzhiyun * @rx_buf: data to be read, or NULL
33*4882a593Smuzhiyun */
34*4882a593Smuzhiyun struct mipi_dsi_msg {
35*4882a593Smuzhiyun u8 channel;
36*4882a593Smuzhiyun u8 type;
37*4882a593Smuzhiyun u16 flags;
38*4882a593Smuzhiyun
39*4882a593Smuzhiyun size_t tx_len;
40*4882a593Smuzhiyun const void *tx_buf;
41*4882a593Smuzhiyun
42*4882a593Smuzhiyun size_t rx_len;
43*4882a593Smuzhiyun void *rx_buf;
44*4882a593Smuzhiyun };
45*4882a593Smuzhiyun
46*4882a593Smuzhiyun bool mipi_dsi_packet_format_is_short(u8 type);
47*4882a593Smuzhiyun bool mipi_dsi_packet_format_is_long(u8 type);
48*4882a593Smuzhiyun
49*4882a593Smuzhiyun /**
50*4882a593Smuzhiyun * struct mipi_dsi_packet - represents a MIPI DSI packet in protocol format
51*4882a593Smuzhiyun * @size: size (in bytes) of the packet
52*4882a593Smuzhiyun * @header: the four bytes that make up the header (Data ID, Word Count or
53*4882a593Smuzhiyun * Packet Data, and ECC)
54*4882a593Smuzhiyun * @payload_length: number of bytes in the payload
55*4882a593Smuzhiyun * @payload: a pointer to a buffer containing the payload, if any
56*4882a593Smuzhiyun */
57*4882a593Smuzhiyun struct mipi_dsi_packet {
58*4882a593Smuzhiyun size_t size;
59*4882a593Smuzhiyun u8 header[4];
60*4882a593Smuzhiyun size_t payload_length;
61*4882a593Smuzhiyun const u8 *payload;
62*4882a593Smuzhiyun };
63*4882a593Smuzhiyun
64*4882a593Smuzhiyun int mipi_dsi_create_packet(struct mipi_dsi_packet *packet,
65*4882a593Smuzhiyun const struct mipi_dsi_msg *msg);
66*4882a593Smuzhiyun
67*4882a593Smuzhiyun /**
68*4882a593Smuzhiyun * struct mipi_dsi_host_ops - DSI bus operations
69*4882a593Smuzhiyun * @attach: attach DSI device to DSI host
70*4882a593Smuzhiyun * @detach: detach DSI device from DSI host
71*4882a593Smuzhiyun * @transfer: transmit a DSI packet
72*4882a593Smuzhiyun *
73*4882a593Smuzhiyun * DSI packets transmitted by .transfer() are passed in as mipi_dsi_msg
74*4882a593Smuzhiyun * structures. This structure contains information about the type of packet
75*4882a593Smuzhiyun * being transmitted as well as the transmit and receive buffers. When an
76*4882a593Smuzhiyun * error is encountered during transmission, this function will return a
77*4882a593Smuzhiyun * negative error code. On success it shall return the number of bytes
78*4882a593Smuzhiyun * transmitted for write packets or the number of bytes received for read
79*4882a593Smuzhiyun * packets.
80*4882a593Smuzhiyun *
81*4882a593Smuzhiyun * Note that typically DSI packet transmission is atomic, so the .transfer()
82*4882a593Smuzhiyun * function will seldomly return anything other than the number of bytes
83*4882a593Smuzhiyun * contained in the transmit buffer on success.
84*4882a593Smuzhiyun */
85*4882a593Smuzhiyun struct mipi_dsi_host_ops {
86*4882a593Smuzhiyun int (*attach)(struct mipi_dsi_host *host,
87*4882a593Smuzhiyun struct mipi_dsi_device *dsi);
88*4882a593Smuzhiyun int (*detach)(struct mipi_dsi_host *host,
89*4882a593Smuzhiyun struct mipi_dsi_device *dsi);
90*4882a593Smuzhiyun ssize_t (*transfer)(struct mipi_dsi_host *host,
91*4882a593Smuzhiyun const struct mipi_dsi_msg *msg);
92*4882a593Smuzhiyun };
93*4882a593Smuzhiyun
94*4882a593Smuzhiyun /**
95*4882a593Smuzhiyun * struct mipi_dsi_host - DSI host device
96*4882a593Smuzhiyun * @dev: driver model device node for this DSI host
97*4882a593Smuzhiyun * @ops: DSI host operations
98*4882a593Smuzhiyun * @list: list management
99*4882a593Smuzhiyun */
100*4882a593Smuzhiyun struct mipi_dsi_host {
101*4882a593Smuzhiyun struct udevice *dev;
102*4882a593Smuzhiyun const struct mipi_dsi_host_ops *ops;
103*4882a593Smuzhiyun };
104*4882a593Smuzhiyun
105*4882a593Smuzhiyun /* DSI mode flags */
106*4882a593Smuzhiyun
107*4882a593Smuzhiyun /* video mode */
108*4882a593Smuzhiyun #define MIPI_DSI_MODE_VIDEO BIT(0)
109*4882a593Smuzhiyun /* video burst mode */
110*4882a593Smuzhiyun #define MIPI_DSI_MODE_VIDEO_BURST BIT(1)
111*4882a593Smuzhiyun /* video pulse mode */
112*4882a593Smuzhiyun #define MIPI_DSI_MODE_VIDEO_SYNC_PULSE BIT(2)
113*4882a593Smuzhiyun /* enable auto vertical count mode */
114*4882a593Smuzhiyun #define MIPI_DSI_MODE_VIDEO_AUTO_VERT BIT(3)
115*4882a593Smuzhiyun /* enable hsync-end packets in vsync-pulse and v-porch area */
116*4882a593Smuzhiyun #define MIPI_DSI_MODE_VIDEO_HSE BIT(4)
117*4882a593Smuzhiyun /* disable hfront-porch area */
118*4882a593Smuzhiyun #define MIPI_DSI_MODE_VIDEO_HFP BIT(5)
119*4882a593Smuzhiyun /* disable hback-porch area */
120*4882a593Smuzhiyun #define MIPI_DSI_MODE_VIDEO_HBP BIT(6)
121*4882a593Smuzhiyun /* disable hsync-active area */
122*4882a593Smuzhiyun #define MIPI_DSI_MODE_VIDEO_HSA BIT(7)
123*4882a593Smuzhiyun /* flush display FIFO on vsync pulse */
124*4882a593Smuzhiyun #define MIPI_DSI_MODE_VSYNC_FLUSH BIT(8)
125*4882a593Smuzhiyun /* disable EoT packets in HS mode */
126*4882a593Smuzhiyun #define MIPI_DSI_MODE_EOT_PACKET BIT(9)
127*4882a593Smuzhiyun /* device supports non-continuous clock behavior (DSI spec 5.6.1) */
128*4882a593Smuzhiyun #define MIPI_DSI_CLOCK_NON_CONTINUOUS BIT(10)
129*4882a593Smuzhiyun /* transmit data in low power */
130*4882a593Smuzhiyun #define MIPI_DSI_MODE_LPM BIT(11)
131*4882a593Smuzhiyun
132*4882a593Smuzhiyun enum mipi_dsi_pixel_format {
133*4882a593Smuzhiyun MIPI_DSI_FMT_RGB888,
134*4882a593Smuzhiyun MIPI_DSI_FMT_RGB666,
135*4882a593Smuzhiyun MIPI_DSI_FMT_RGB666_PACKED,
136*4882a593Smuzhiyun MIPI_DSI_FMT_RGB565,
137*4882a593Smuzhiyun };
138*4882a593Smuzhiyun
139*4882a593Smuzhiyun #define DSI_DEV_NAME_SIZE 20
140*4882a593Smuzhiyun
141*4882a593Smuzhiyun /**
142*4882a593Smuzhiyun * struct mipi_dsi_device - DSI peripheral device
143*4882a593Smuzhiyun * @host: DSI host for this peripheral
144*4882a593Smuzhiyun * @dev: driver model device node for this peripheral
145*4882a593Smuzhiyun * @name: DSI peripheral chip type
146*4882a593Smuzhiyun * @channel: virtual channel assigned to the peripheral
147*4882a593Smuzhiyun * @format: pixel format for video mode
148*4882a593Smuzhiyun * @lanes: number of active data lanes
149*4882a593Smuzhiyun * @mode_flags: DSI operation mode related flags
150*4882a593Smuzhiyun * @hs_rate: maximum lane frequency for high speed mode in hertz, this should
151*4882a593Smuzhiyun * be set to the real limits of the hardware, zero is only accepted for
152*4882a593Smuzhiyun * legacy drivers
153*4882a593Smuzhiyun * @lp_rate: maximum lane frequency for low power mode in hertz, this should
154*4882a593Smuzhiyun * be set to the real limits of the hardware, zero is only accepted for
155*4882a593Smuzhiyun * legacy drivers
156*4882a593Smuzhiyun */
157*4882a593Smuzhiyun struct mipi_dsi_device {
158*4882a593Smuzhiyun struct mipi_dsi_host *host;
159*4882a593Smuzhiyun struct udevice *dev;
160*4882a593Smuzhiyun
161*4882a593Smuzhiyun char name[DSI_DEV_NAME_SIZE];
162*4882a593Smuzhiyun unsigned int channel;
163*4882a593Smuzhiyun unsigned int lanes;
164*4882a593Smuzhiyun enum mipi_dsi_pixel_format format;
165*4882a593Smuzhiyun unsigned long mode_flags;
166*4882a593Smuzhiyun unsigned long hs_rate;
167*4882a593Smuzhiyun unsigned long lp_rate;
168*4882a593Smuzhiyun };
169*4882a593Smuzhiyun
170*4882a593Smuzhiyun /**
171*4882a593Smuzhiyun * mipi_dsi_pixel_format_to_bpp - obtain the number of bits per pixel for any
172*4882a593Smuzhiyun * given pixel format defined by the MIPI DSI
173*4882a593Smuzhiyun * specification
174*4882a593Smuzhiyun * @fmt: MIPI DSI pixel format
175*4882a593Smuzhiyun *
176*4882a593Smuzhiyun * Returns: The number of bits per pixel of the given pixel format.
177*4882a593Smuzhiyun */
mipi_dsi_pixel_format_to_bpp(enum mipi_dsi_pixel_format fmt)178*4882a593Smuzhiyun static inline int mipi_dsi_pixel_format_to_bpp(enum mipi_dsi_pixel_format fmt)
179*4882a593Smuzhiyun {
180*4882a593Smuzhiyun switch (fmt) {
181*4882a593Smuzhiyun case MIPI_DSI_FMT_RGB888:
182*4882a593Smuzhiyun case MIPI_DSI_FMT_RGB666:
183*4882a593Smuzhiyun return 24;
184*4882a593Smuzhiyun
185*4882a593Smuzhiyun case MIPI_DSI_FMT_RGB666_PACKED:
186*4882a593Smuzhiyun return 18;
187*4882a593Smuzhiyun
188*4882a593Smuzhiyun case MIPI_DSI_FMT_RGB565:
189*4882a593Smuzhiyun return 16;
190*4882a593Smuzhiyun }
191*4882a593Smuzhiyun
192*4882a593Smuzhiyun return -EINVAL;
193*4882a593Smuzhiyun }
194*4882a593Smuzhiyun
195*4882a593Smuzhiyun int mipi_dsi_attach(struct mipi_dsi_device *dsi);
196*4882a593Smuzhiyun int mipi_dsi_detach(struct mipi_dsi_device *dsi);
197*4882a593Smuzhiyun int mipi_dsi_shutdown_peripheral(struct mipi_dsi_device *dsi);
198*4882a593Smuzhiyun int mipi_dsi_turn_on_peripheral(struct mipi_dsi_device *dsi);
199*4882a593Smuzhiyun int mipi_dsi_set_maximum_return_packet_size(struct mipi_dsi_device *dsi,
200*4882a593Smuzhiyun u16 value);
201*4882a593Smuzhiyun
202*4882a593Smuzhiyun ssize_t mipi_dsi_compression_mode(struct mipi_dsi_device *dsi, bool enable);
203*4882a593Smuzhiyun ssize_t mipi_dsi_picture_parameter_set(struct mipi_dsi_device *dsi,
204*4882a593Smuzhiyun const struct drm_dsc_picture_parameter_set *pps);
205*4882a593Smuzhiyun
206*4882a593Smuzhiyun ssize_t mipi_dsi_generic_write(struct mipi_dsi_device *dsi, const void *payload,
207*4882a593Smuzhiyun size_t size);
208*4882a593Smuzhiyun ssize_t mipi_dsi_generic_read(struct mipi_dsi_device *dsi, const void *params,
209*4882a593Smuzhiyun size_t num_params, void *data, size_t size);
210*4882a593Smuzhiyun
211*4882a593Smuzhiyun /**
212*4882a593Smuzhiyun * enum mipi_dsi_dcs_tear_mode - Tearing Effect Output Line mode
213*4882a593Smuzhiyun * @MIPI_DSI_DCS_TEAR_MODE_VBLANK: the TE output line consists of V-Blanking
214*4882a593Smuzhiyun * information only
215*4882a593Smuzhiyun * @MIPI_DSI_DCS_TEAR_MODE_VHBLANK : the TE output line consists of both
216*4882a593Smuzhiyun * V-Blanking and H-Blanking information
217*4882a593Smuzhiyun */
218*4882a593Smuzhiyun enum mipi_dsi_dcs_tear_mode {
219*4882a593Smuzhiyun MIPI_DSI_DCS_TEAR_MODE_VBLANK,
220*4882a593Smuzhiyun MIPI_DSI_DCS_TEAR_MODE_VHBLANK,
221*4882a593Smuzhiyun };
222*4882a593Smuzhiyun
223*4882a593Smuzhiyun #define MIPI_DSI_DCS_POWER_MODE_DISPLAY BIT(2)
224*4882a593Smuzhiyun #define MIPI_DSI_DCS_POWER_MODE_NORMAL BIT(3)
225*4882a593Smuzhiyun #define MIPI_DSI_DCS_POWER_MODE_SLEEP BIT(4)
226*4882a593Smuzhiyun #define MIPI_DSI_DCS_POWER_MODE_PARTIAL BIT(5)
227*4882a593Smuzhiyun #define MIPI_DSI_DCS_POWER_MODE_IDLE BIT(6)
228*4882a593Smuzhiyun
229*4882a593Smuzhiyun ssize_t mipi_dsi_dcs_write_buffer(struct mipi_dsi_device *dsi,
230*4882a593Smuzhiyun const void *data, size_t len);
231*4882a593Smuzhiyun ssize_t mipi_dsi_dcs_write(struct mipi_dsi_device *dsi, u8 cmd,
232*4882a593Smuzhiyun const void *data, size_t len);
233*4882a593Smuzhiyun ssize_t mipi_dsi_dcs_read(struct mipi_dsi_device *dsi, u8 cmd, void *data,
234*4882a593Smuzhiyun size_t len);
235*4882a593Smuzhiyun int mipi_dsi_dcs_nop(struct mipi_dsi_device *dsi);
236*4882a593Smuzhiyun int mipi_dsi_dcs_soft_reset(struct mipi_dsi_device *dsi);
237*4882a593Smuzhiyun int mipi_dsi_dcs_get_power_mode(struct mipi_dsi_device *dsi, u8 *mode);
238*4882a593Smuzhiyun int mipi_dsi_dcs_get_pixel_format(struct mipi_dsi_device *dsi, u8 *format);
239*4882a593Smuzhiyun int mipi_dsi_dcs_enter_sleep_mode(struct mipi_dsi_device *dsi);
240*4882a593Smuzhiyun int mipi_dsi_dcs_exit_sleep_mode(struct mipi_dsi_device *dsi);
241*4882a593Smuzhiyun int mipi_dsi_dcs_set_display_off(struct mipi_dsi_device *dsi);
242*4882a593Smuzhiyun int mipi_dsi_dcs_set_display_on(struct mipi_dsi_device *dsi);
243*4882a593Smuzhiyun int mipi_dsi_dcs_set_column_address(struct mipi_dsi_device *dsi, u16 start,
244*4882a593Smuzhiyun u16 end);
245*4882a593Smuzhiyun int mipi_dsi_dcs_set_page_address(struct mipi_dsi_device *dsi, u16 start,
246*4882a593Smuzhiyun u16 end);
247*4882a593Smuzhiyun int mipi_dsi_dcs_set_tear_off(struct mipi_dsi_device *dsi);
248*4882a593Smuzhiyun int mipi_dsi_dcs_set_tear_on(struct mipi_dsi_device *dsi,
249*4882a593Smuzhiyun enum mipi_dsi_dcs_tear_mode mode);
250*4882a593Smuzhiyun int mipi_dsi_dcs_set_pixel_format(struct mipi_dsi_device *dsi, u8 format);
251*4882a593Smuzhiyun int mipi_dsi_dcs_set_tear_scanline(struct mipi_dsi_device *dsi, u16 scanline);
252*4882a593Smuzhiyun int mipi_dsi_dcs_set_display_brightness(struct mipi_dsi_device *dsi,
253*4882a593Smuzhiyun u16 brightness);
254*4882a593Smuzhiyun int mipi_dsi_dcs_get_display_brightness(struct mipi_dsi_device *dsi,
255*4882a593Smuzhiyun u16 *brightness);
256*4882a593Smuzhiyun
257*4882a593Smuzhiyun #endif /* __DRM_MIPI_DSI__ */
258