1 /* 2 * Configuration settings for the TechNexion TAO-3530 SOM 3 * equipped on Thunder baseboard. 4 * 5 * Edward Lin <linuxfae@technexion.com> 6 * Tapani Utriainen <linuxfae@technexion.com> 7 * 8 * Copyright (C) 2013 Stefan Roese <sr@denx.de> 9 * 10 * SPDX-License-Identifier: GPL-2.0+ 11 */ 12 13 #ifndef __CONFIG_H 14 #define __CONFIG_H 15 16 /* 17 * High Level Configuration Options 18 */ 19 20 #define CONFIG_SDRC /* Has an SDRC controller */ 21 22 #include <asm/arch/cpu.h> /* get chip and board defs */ 23 #include <asm/arch/omap.h> 24 25 /* Clock Defines */ 26 #define V_OSCK 26000000 /* Clock output from T2 */ 27 #define V_SCLK (V_OSCK >> 1) 28 29 #define CONFIG_MISC_INIT_R 30 31 #define CONFIG_CMDLINE_TAG 32 #define CONFIG_SETUP_MEMORY_TAGS 33 #define CONFIG_INITRD_TAG 34 #define CONFIG_REVISION_TAG 35 36 /* 37 * Size of malloc() pool 38 */ 39 #define CONFIG_SYS_MALLOC_LEN (4 << 20) 40 #define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB sector */ 41 42 /* 43 * Hardware drivers 44 */ 45 46 /* 47 * NS16550 Configuration 48 */ 49 #define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */ 50 51 #define CONFIG_SYS_NS16550_SERIAL 52 #define CONFIG_SYS_NS16550_REG_SIZE (-4) 53 #define CONFIG_SYS_NS16550_CLK V_NS16550_CLK 54 55 /* 56 * select serial console configuration 57 */ 58 #define CONFIG_CONS_INDEX 3 59 #define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3 60 61 /* allow to overwrite serial and ethaddr */ 62 #define CONFIG_ENV_OVERWRITE 63 64 /* commands to include */ 65 66 #define CONFIG_SYS_I2C 67 #define CONFIG_SYS_OMAP24_I2C_SPEED 100000 68 #define CONFIG_SYS_OMAP24_I2C_SLAVE 1 69 #define CONFIG_I2C_MULTI_BUS 70 71 /* 72 * TWL4030 73 */ 74 #define CONFIG_TWL4030_LED 75 76 /* 77 * Board NAND Info. 78 */ 79 #define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */ 80 /* to access nand */ 81 #define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */ 82 /* to access nand at */ 83 /* CS0 */ 84 85 #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */ 86 /* devices */ 87 /* Environment information */ 88 89 #define CONFIG_EXTRA_ENV_SETTINGS \ 90 "loadaddr=0x82000000\0" \ 91 "console=ttyO2,115200n8\0" \ 92 "mpurate=600\0" \ 93 "dvi_mode=omapfb.mode=dvi:1280x720-24@60\0" \ 94 "tv_mode=omapfb.mode=tv:ntsc\0" \ 95 "video_mode=omapdss.def_disp=lcd vram=6M omapfb.vram=0:2M,1:2M,2:2M\0" \ 96 "lcd_mode=omapfb.mode=lcd:800x480@60 \0" \ 97 "extra_options= \0" \ 98 "mmcdev=0\0" \ 99 "mmcroot=/dev/mmcblk0p2 rw\0" \ 100 "mmcrootfstype=ext3 rootwait\0" \ 101 "nandroot=ubi0:rootfs ubi.mtd=4\0" \ 102 "nandrootfstype=ubifs\0" \ 103 "mmcargs=setenv bootargs console=${console} " \ 104 "mpurate=${mpurate} " \ 105 "${video_mode} " \ 106 "root=${mmcroot} " \ 107 "rootfstype=${mmcrootfstype} " \ 108 "${extra_options}\0" \ 109 "nandargs=setenv bootargs console=${console} " \ 110 "mpurate=${mpurate} " \ 111 "${video_mode} " \ 112 "${network_setting} " \ 113 "root=${nandroot} " \ 114 "rootfstype=${nandrootfstype} "\ 115 "${extra_options}\0" \ 116 "loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \ 117 "bootscript=echo Running bootscript from mmc ...; " \ 118 "source ${loadaddr}\0" \ 119 "loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \ 120 "mmcboot=echo Booting from mmc ...; " \ 121 "run mmcargs; " \ 122 "bootm ${loadaddr}\0" \ 123 "nandboot=echo Booting from nand ...; " \ 124 "run nandargs; " \ 125 "nand read ${loadaddr} 280000 400000; " \ 126 "bootm ${loadaddr}\0" \ 127 128 #define CONFIG_BOOTCOMMAND \ 129 "if mmc rescan ${mmcdev}; then " \ 130 "if run loadbootscript; then " \ 131 "run bootscript; " \ 132 "else " \ 133 "if run loaduimage; then " \ 134 "run mmcboot; " \ 135 "else run nandboot; " \ 136 "fi; " \ 137 "fi; " \ 138 "else run nandboot; fi" 139 140 /* 141 * Miscellaneous configurable options 142 */ 143 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 144 145 /* turn on command-line edit/hist/auto */ 146 #define CONFIG_CMDLINE_EDITING 147 #define CONFIG_AUTO_COMPLETE 148 149 #define CONFIG_SYS_ALT_MEMTEST 1 150 #define CONFIG_SYS_MEMTEST_START (0x82000000) /* memtest */ 151 /* defaults */ 152 #define CONFIG_SYS_MEMTEST_END (0x83FFFFFF) /* 64MB */ 153 #define CONFIG_SYS_MEMTEST_SCRATCH (0x81000000) /* dummy address */ 154 155 #define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default */ 156 /* load address */ 157 #define CONFIG_SYS_TEXT_BASE 0x80008000 158 159 /* 160 * OMAP3 has 12 GP timers, they can be driven by the system clock 161 * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK). 162 * This rate is divided by a local divisor. 163 */ 164 #define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2) 165 #define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ 166 167 /* 168 * Physical Memory Map 169 */ 170 #define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */ 171 #define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0 172 #define PHYS_SDRAM_1_SIZE (32 << 20) /* at least 32 MiB */ 173 #define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1 174 175 /* 176 * FLASH and environment organization 177 */ 178 179 /* **** PISMO SUPPORT *** */ 180 #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */ 181 #define CONFIG_SYS_FLASH_BASE NAND_BASE 182 183 /* Monitor at start of flash */ 184 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE 185 #define CONFIG_SYS_ONENAND_BASE ONENAND_MAP 186 187 #define ONENAND_ENV_OFFSET 0x260000 /* environment starts here */ 188 #define SMNAND_ENV_OFFSET 0x260000 /* environment starts here */ 189 190 #define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) 191 #define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET 192 #define CONFIG_ENV_ADDR CONFIG_ENV_OFFSET 193 194 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 195 #define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800 196 #define CONFIG_SYS_INIT_RAM_SIZE 0x800 197 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ 198 CONFIG_SYS_INIT_RAM_SIZE - \ 199 GENERATED_GBL_DATA_SIZE) 200 201 /* 202 * USB 203 * 204 * Currently only EHCI is enabled, the MUSB OTG controller 205 * is not enabled. 206 */ 207 208 /* USB EHCI */ 209 #define CONFIG_OMAP_EHCI_PHY1_RESET_GPIO 162 210 211 /* Defines for SPL */ 212 #define CONFIG_SPL_FRAMEWORK 213 214 #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 215 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" 216 217 #define CONFIG_SPL_NAND_BASE 218 #define CONFIG_SPL_NAND_DRIVERS 219 #define CONFIG_SPL_NAND_ECC 220 221 /* NAND boot config */ 222 #define CONFIG_SYS_NAND_5_ADDR_CYCLE 223 #define CONFIG_SYS_NAND_PAGE_COUNT 64 224 #define CONFIG_SYS_NAND_PAGE_SIZE 2048 225 #define CONFIG_SYS_NAND_OOBSIZE 64 226 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 227 #define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS 228 /* 229 * Use the ECC/OOB layout from omap_gpmc.h that matches your chip: 230 * SP vs LP, 8bit vs 16bit: GPMC_NAND_HW_ECC_LAYOUT 231 */ 232 #define CONFIG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \ 233 10, 11, 12, 13 } 234 #define CONFIG_SYS_NAND_ECCSIZE 512 235 #define CONFIG_SYS_NAND_ECCBYTES 3 236 #define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_HAM1_CODE_HW 237 238 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE 239 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000 240 241 #define CONFIG_SPL_TEXT_BASE 0x40200800 242 #define CONFIG_SPL_MAX_SIZE (SRAM_SCRATCH_SPACE_ADDR - \ 243 CONFIG_SPL_TEXT_BASE) 244 245 /* 246 * Use 0x80008000 as TEXT_BASE here for compatibility reasons with the 247 * older x-loader implementations. And move the BSS area so that it 248 * doesn't overlap with TEXT_BASE. 249 */ 250 #define CONFIG_SYS_TEXT_BASE 0x80008000 251 #define CONFIG_SPL_BSS_START_ADDR 0x80100000 252 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* 512 KB */ 253 254 #define CONFIG_SYS_SPL_MALLOC_START 0x80208000 255 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 256 257 #endif /* __CONFIG_H */ 258