1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * (C) Copyright 2020 Rockchip Electronics Co., Ltd 4 * 5 */ 6 7 #ifndef __CONFIG_RK3528_COMMON_H 8 #define __CONFIG_RK3528_COMMON_H 9 10 #include "rockchip-common.h" 11 12 #define CONFIG_SPL_FRAMEWORK 13 #define CONFIG_SPL_TEXT_BASE 0x00000000 14 #define CONFIG_SPL_MAX_SIZE 0x00040000 15 #define CONFIG_SPL_BSS_START_ADDR 0x03fe0000 16 #define CONFIG_SPL_BSS_MAX_SIZE 0x00010000 17 #define CONFIG_SPL_STACK 0x03fe0000 18 19 #define CONFIG_SYS_MALLOC_LEN (32 << 20) 20 #define CONFIG_SYS_CBSIZE 1024 21 #define CONFIG_SKIP_LOWLEVEL_INIT 22 23 #ifdef CONFIG_SUPPORT_USBPLUG 24 #define CONFIG_SYS_TEXT_BASE 0x00000000 25 #else 26 #define CONFIG_SYS_TEXT_BASE 0x00200000 27 #endif 28 29 #define CONFIG_SYS_INIT_SP_ADDR 0x00c00000 30 #define CONFIG_SYS_LOAD_ADDR 0x00c00800 31 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* 64M */ 32 #define COUNTER_FREQUENCY 24000000 33 34 #define GICD_BASE 0xfed01000 35 #define GICC_BASE 0xfed02000 36 37 #ifdef CONFIG_SPL_DM_VIDEO 38 #undef CONFIG_SPL_MAX_SIZE 39 #undef CONFIG_SPL_BSS_MAX_SIZE 40 #define CONFIG_SPL_MAX_SIZE 0x00140000 41 #define CONFIG_SPL_BSS_MAX_SIZE 0x00080000 42 #endif 43 44 #ifdef CONFIG_ARM_SMP 45 #define SMP_CPU1 0x1 46 #define SMP_CPU1_STACK 0x04fe0000 47 #define SMP_CPU2 0x2 48 #define SMP_CPU2_STACK 0x05fe0000 49 #endif 50 51 /* secure otp */ 52 #define OTP_UBOOT_ROLLBACK_OFFSET 0x350 53 #define OTP_UBOOT_ROLLBACK_WORDS 2 /* 64 bits, 2 words */ 54 #define OTP_ALL_ONES_NUM_BITS 32 55 #define OTP_SECURE_BOOT_ENABLE_ADDR 0x20 56 #define OTP_SECURE_BOOT_ENABLE_SIZE 1 57 #define OTP_RSA_HASH_ADDR 0x180 58 #define OTP_RSA_HASH_SIZE 32 59 60 /* MMC/SD IP block */ 61 #define CONFIG_BOUNCE_BUFFER 62 63 #define CONFIG_SYS_SDRAM_BASE 0 64 #define SDRAM_MAX_SIZE 0xfc000000 65 #define CONFIG_PREBOOT 66 #define CONFIG_SYS_NONCACHED_MEMORY (1 << 20) /* 1 MiB */ 67 68 #define CONFIG_SPL_LOAD_FIT_ADDRESS 0x2000000 69 70 #ifndef CONFIG_SPL_BUILD 71 /* usb mass storage */ 72 #define CONFIG_USB_FUNCTION_MASS_STORAGE 73 #define CONFIG_ROCKUSB_G_DNL_PID 0x350c 74 75 #ifdef CONFIG_ARM64 76 #define ENV_MEM_LAYOUT_SETTINGS \ 77 "scriptaddr=0x00c00000\0" \ 78 "pxefile_addr_r=0x00e00000\0" \ 79 "fdt_addr_r=0x08300000\0" \ 80 "kernel_addr_r=0x00280000\0" \ 81 "kernel_addr_c=0x04080000\0" \ 82 "ramdisk_addr_r=0x0a200000\0" 83 #else 84 #define ENV_MEM_LAYOUT_SETTINGS \ 85 "scriptaddr=0x00000000\0" \ 86 "pxefile_addr_r=0x00100000\0" \ 87 "fdt_addr_r=0x08300000\0" \ 88 "kernel_addr_c=0x02008000\0" \ 89 "kernel_addr_r=0x00208000\0" \ 90 "ramdisk_addr_r=0x0a200000\0" 91 #endif 92 93 #include <config_distro_bootcmd.h> 94 95 #define CONFIG_EXTRA_ENV_SETTINGS \ 96 ENV_MEM_LAYOUT_SETTINGS \ 97 "partitions=" PARTS_RKIMG \ 98 ROCKCHIP_DEVICE_SETTINGS \ 99 RKIMG_DET_BOOTDEV \ 100 BOOTENV 101 #endif 102 103 /* rockchip ohci host driver */ 104 #define CONFIG_USB_OHCI_NEW 105 #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 1 106 107 #define CONFIG_LIB_HW_RAND 108 109 #endif 110