1 /* 2 * (C) Copyright 2004 3 * Texas Instruments. 4 * Richard Woodruff <r-woodruff2@ti.com> 5 * Kshitij Gupta <kshitij@ti.com> 6 * 7 * Configuration settings for the phyCORE-i.MX31 board. 8 * 9 * SPDX-License-Identifier: GPL-2.0+ 10 */ 11 12 #ifndef __CONFIG_H 13 #define __CONFIG_H 14 15 #include <asm/arch/imx-regs.h> 16 17 /* High Level Configuration Options */ 18 #define CONFIG_MX31 /* This is a mx31 */ 19 #define CONFIG_MX31_CLK32 32000 20 21 #define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ 22 #define CONFIG_SETUP_MEMORY_TAGS 23 #define CONFIG_INITRD_TAG 24 25 /* 26 * Size of malloc() pool 27 */ 28 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 512 * 1024) 29 30 /* 31 * Hardware drivers 32 */ 33 34 #define CONFIG_SYS_I2C 35 #define CONFIG_SYS_I2C_MXC 36 #define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ 37 #define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ 38 #define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ 39 #define CONFIG_SYS_I2C_CLK_OFFSET I2C2_CLK_OFFSET 40 41 #define CONFIG_MXC_UART 42 #define CONFIG_MXC_UART_BASE UART1_BASE 43 44 /* allow to overwrite serial and ethaddr */ 45 #define CONFIG_ENV_OVERWRITE 46 #define CONFIG_CONS_INDEX 1 47 48 /*********************************************************** 49 * Command definition 50 ***********************************************************/ 51 52 53 #define MTDPARTS_DEFAULT "mtdparts=physmap-flash.0:128k(uboot)ro," \ 54 "1536k(kernel),-(root)" 55 56 #define CONFIG_NETMASK 255.255.255.0 57 #define CONFIG_IPADDR 192.168.23.168 58 #define CONFIG_SERVERIP 192.168.23.2 59 60 #define CONFIG_EXTRA_ENV_SETTINGS \ 61 "bootargs_base=setenv bootargs console=ttySMX0,115200\0" \ 62 "bootargs_nfs=setenv bootargs $(bootargs) root=/dev/nfs " \ 63 "ip=dhcp nfsroot=$(serverip):$(nfsrootfs),v3,tcp\0" \ 64 "bootargs_flash=setenv bootargs $(bootargs) " \ 65 "root=/dev/mtdblock2 rootfstype=jffs2\0" \ 66 "bootargs_mtd=setenv bootargs $(bootargs) $(mtdparts)\0" \ 67 "bootcmd=run bootcmd_net\0" \ 68 "bootcmd_net=run bootargs_base bootargs_mtd bootargs_nfs;" \ 69 "tftpboot 0x80000000 $(uimage);bootm\0" \ 70 "bootcmd_flash=run bootargs_base bootargs_mtd bootargs_flash;" \ 71 "bootm 0x80000000\0" \ 72 "unlock=yes\0" \ 73 "mtdparts=" MTDPARTS_DEFAULT "\0" \ 74 "prg_uboot=tftpboot 0x80000000 $(uboot);" \ 75 "protect off 0xa0000000 +0x20000;" \ 76 "erase 0xa0000000 +0x20000;" \ 77 "cp.b 0x80000000 0xa0000000 $(filesize)\0" \ 78 "prg_kernel=tftpboot 0x80000000 $(uimage);" \ 79 "erase 0xa0040000 +0x180000;" \ 80 "cp.b 0x80000000 0xa0040000 $(filesize)\0" \ 81 "prg_jffs2=tftpboot 0x80000000 $(jffs2);" \ 82 "erase 0xa01c0000 0xa1ffffff;" \ 83 "cp.b 0x80000000 0xa01c0000 $(filesize)\0" \ 84 "videomode=video=ctfb:x:240,y:320,depth:16,mode:0," \ 85 "pclk:185925,le:9,ri:17,up:7,lo:10,hs:1,vs:1," \ 86 "sync:1241513985,vmode:0\0" 87 88 #define CONFIG_SMC911X 89 #define CONFIG_SMC911X_BASE 0xa8000000 90 #define CONFIG_SMC911X_32_BIT 91 92 /* 93 * Miscellaneous configurable options 94 */ 95 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 96 97 #define CONFIG_SYS_MEMTEST_START 0 /* memtest works on */ 98 #define CONFIG_SYS_MEMTEST_END 0x10000 99 100 #define CONFIG_SYS_LOAD_ADDR 0 /* default load address */ 101 102 #define CONFIG_CMDLINE_EDITING 103 104 /* 105 * Physical Memory Map 106 */ 107 #define CONFIG_NR_DRAM_BANKS 1 108 #define PHYS_SDRAM_1 0x80000000 109 #define PHYS_SDRAM_1_SIZE (128 * 1024 * 1024) 110 #define CONFIG_SYS_TEXT_BASE 0xA0000000 111 112 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 113 #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR 114 #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE 115 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ 116 GENERATED_GBL_DATA_SIZE) 117 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ 118 CONFIG_SYS_GBL_DATA_OFFSET) 119 120 /* 121 * FLASH and environment organization 122 */ 123 #define CONFIG_SYS_FLASH_BASE 0xa0000000 124 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max # of memory banks */ 125 #define CONFIG_SYS_MAX_FLASH_SECT 259 /* max # of sectors/chip */ 126 /* Monitor at beginning of flash */ 127 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE 128 129 #define CONFIG_ENV_OFFSET 0x00 /* env. starts here */ 130 #define CONFIG_ENV_SIZE 4096 131 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x52 132 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5 /* 5 bits = 32 octets */ 133 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* 10 ms delay */ 134 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 /* byte addr. lenght */ 135 136 /* 137 * CFI FLASH driver setup 138 */ 139 #define CONFIG_SYS_FLASH_CFI /* Flash memory is CFI compliant */ 140 #define CONFIG_FLASH_CFI_DRIVER /* Use drivers/mtd/cfi_flash.c */ 141 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE /* buffered writes (~10x faster) */ 142 #define CONFIG_SYS_FLASH_PROTECTION /* Use hardware sector protection */ 143 144 /* 145 * Timeout for Flash Erase and Flash Write 146 * timeout values are in ticks 147 */ 148 #define CONFIG_SYS_FLASH_ERASE_TOUT (100*CONFIG_SYS_HZ) 149 #define CONFIG_SYS_FLASH_WRITE_TOUT (100*CONFIG_SYS_HZ) 150 151 /* 152 * JFFS2 partitions 153 */ 154 #define CONFIG_JFFS2_DEV "nor0" 155 156 /* EET platform additions */ 157 #ifdef CONFIG_TARGET_IMX31_PHYCORE_EET 158 #define CONFIG_MXC_GPIO 159 160 #define CONFIG_HARD_SPI 161 #define CONFIG_MXC_SPI 162 163 #define CONFIG_S6E63D6 164 165 #define CONFIG_VIDEO_MX3 166 #define CONFIG_VIDEO_LOGO 167 #define CONFIG_SPLASH_SCREEN 168 #define CONFIG_BMP_16BPP 169 #endif 170 171 #endif /* __CONFIG_H */ 172