1 /* 2 * (C) Copyright 2013 3 * Texas Instruments Incorporated. 4 * Lokesh Vutla <lokeshvutla@ti.com> 5 * 6 * Configuration settings for the TI DRA7XX board. 7 * See ti_omap5_common.h for omap5 common settings. 8 * 9 * SPDX-License-Identifier: GPL-2.0+ 10 */ 11 12 #ifndef __CONFIG_DRA7XX_EVM_H 13 #define __CONFIG_DRA7XX_EVM_H 14 15 #include <environment/ti/dfu.h> 16 17 #ifdef CONFIG_SPL_BUILD 18 #define CONFIG_IODELAY_RECALIBRATION 19 #endif 20 21 #define CONFIG_VERY_BIG_RAM 22 #define CONFIG_NR_DRAM_BANKS 2 23 #define CONFIG_MAX_MEM_MAPPED 0x80000000 24 25 #ifndef CONFIG_QSPI_BOOT 26 /* MMC ENV related defines */ 27 #define CONFIG_SYS_MMC_ENV_DEV 1 /* SLOT2: eMMC(1) */ 28 #define CONFIG_ENV_SIZE (128 << 10) 29 #define CONFIG_ENV_OFFSET 0x260000 30 #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE) 31 #define CONFIG_SYS_REDUNDAND_ENVIRONMENT 32 #endif 33 34 #if (CONFIG_CONS_INDEX == 1) 35 #define CONSOLEDEV "ttyO0" 36 #elif (CONFIG_CONS_INDEX == 3) 37 #define CONSOLEDEV "ttyO2" 38 #endif 39 #define CONFIG_SYS_NS16550_COM1 UART1_BASE /* Base EVM has UART0 */ 40 #define CONFIG_SYS_NS16550_COM2 UART2_BASE /* UART2 */ 41 #define CONFIG_SYS_NS16550_COM3 UART3_BASE /* UART3 */ 42 43 #define CONFIG_ENV_EEPROM_IS_ON_I2C 44 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* Main EEPROM */ 45 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 46 47 #define CONFIG_SYS_OMAP_ABE_SYSCK 48 49 #ifndef CONFIG_SPL_BUILD 50 /* Define the default GPT table for eMMC */ 51 #define PARTS_DEFAULT \ 52 /* Linux partitions */ \ 53 "uuid_disk=${uuid_gpt_disk};" \ 54 "name=rootfs,start=2MiB,size=-,uuid=${uuid_gpt_rootfs}\0" \ 55 /* Android partitions */ \ 56 "partitions_android=" \ 57 "uuid_disk=${uuid_gpt_disk};" \ 58 "name=xloader,start=128K,size=256K,uuid=${uuid_gpt_xloader};" \ 59 "name=bootloader,size=1792K,uuid=${uuid_gpt_bootloader};" \ 60 "name=environment,size=128K,uuid=${uuid_gpt_environment};" \ 61 "name=misc,size=128K,uuid=${uuid_gpt_misc};" \ 62 "name=reserved,size=256K,uuid=${uuid_gpt_reserved};" \ 63 "name=efs,size=16M,uuid=${uuid_gpt_efs};" \ 64 "name=crypto,size=16K,uuid=${uuid_gpt_crypto};" \ 65 "name=recovery,size=10M,uuid=${uuid_gpt_recovery};" \ 66 "name=boot,size=10M,uuid=${uuid_gpt_boot};" \ 67 "name=system,size=768M,uuid=${uuid_gpt_system};" \ 68 "name=cache,size=256M,uuid=${uuid_gpt_cache};" \ 69 "name=ipu1,size=1M,uuid=${uuid_gpt_ipu1};" \ 70 "name=ipu2,size=1M,uuid=${uuid_gpt_ipu2};" \ 71 "name=userdata,size=-,uuid=${uuid_gpt_userdata}" 72 73 #define DFUARGS \ 74 "dfu_bufsiz=0x10000\0" \ 75 DFU_ALT_INFO_MMC \ 76 DFU_ALT_INFO_EMMC \ 77 DFU_ALT_INFO_RAM \ 78 DFU_ALT_INFO_QSPI 79 #endif 80 81 #ifdef CONFIG_SPL_BUILD 82 #undef CONFIG_CMD_BOOTD 83 #ifdef CONFIG_SPL_DFU 84 #define CONFIG_SPL_LOAD_FIT_ADDRESS 0x80200000 85 #define DFUARGS \ 86 "dfu_bufsiz=0x10000\0" \ 87 DFU_ALT_INFO_RAM 88 #endif 89 #endif 90 91 #include <configs/ti_omap5_common.h> 92 93 /* Enhance our eMMC support / experience. */ 94 #define CONFIG_HSMMC2_8BIT 95 96 /* CPSW Ethernet */ 97 #define CONFIG_BOOTP_DNS /* Configurable parts of CMD_DHCP */ 98 #define CONFIG_BOOTP_DNS2 99 #define CONFIG_BOOTP_SEND_HOSTNAME 100 #define CONFIG_BOOTP_GATEWAY 101 #define CONFIG_BOOTP_SUBNETMASK 102 #define CONFIG_NET_RETRY_COUNT 10 103 #define CONFIG_DRIVER_TI_CPSW /* Driver for IP block */ 104 #define CONFIG_MII /* Required in net/eth.c */ 105 #define CONFIG_PHY_TI 106 107 /* SPI */ 108 #define CONFIG_TI_SPI_MMAP 109 #define CONFIG_SF_DEFAULT_SPEED 76800000 110 #define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 111 #define CONFIG_QSPI_QUAD_SUPPORT 112 113 /* 114 * Default to using SPI for environment, etc. 115 * 0x000000 - 0x040000 : QSPI.SPL (256KiB) 116 * 0x040000 - 0x140000 : QSPI.u-boot (1MiB) 117 * 0x140000 - 0x1C0000 : QSPI.u-boot-spl-os (512KiB) 118 * 0x1C0000 - 0x1D0000 : QSPI.u-boot-env (64KiB) 119 * 0x1D0000 - 0x1E0000 : QSPI.u-boot-env.backup1 (64KiB) 120 * 0x1E0000 - 0x9E0000 : QSPI.kernel (8MiB) 121 * 0x9E0000 - 0x2000000 : USERLAND 122 */ 123 #define CONFIG_SYS_SPI_KERNEL_OFFS 0x1E0000 124 #define CONFIG_SYS_SPI_ARGS_OFFS 0x140000 125 #define CONFIG_SYS_SPI_ARGS_SIZE 0x80000 126 #if defined(CONFIG_QSPI_BOOT) 127 #define CONFIG_SYS_REDUNDAND_ENVIRONMENT 128 #define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED 129 #define CONFIG_ENV_SIZE (64 << 10) 130 #define CONFIG_ENV_SECT_SIZE (64 << 10) /* 64 KB sectors */ 131 #define CONFIG_ENV_OFFSET 0x1C0000 132 #define CONFIG_ENV_OFFSET_REDUND 0x1D0000 133 #endif 134 135 /* SPI SPL */ 136 #define CONFIG_TI_EDMA3 137 #define CONFIG_SPL_SPI_LOAD 138 #define CONFIG_SYS_SPI_U_BOOT_OFFS 0x40000 139 140 #define CONFIG_SUPPORT_EMMC_BOOT 141 142 /* USB xHCI HOST */ 143 #define CONFIG_USB_XHCI_OMAP 144 145 #define CONFIG_OMAP_USB_PHY 146 #define CONFIG_OMAP_USB2PHY2_HOST 147 148 /* SATA */ 149 #define CONFIG_LIBATA 150 #define CONFIG_SCSI_AHCI 151 #define CONFIG_SCSI_AHCI_PLAT 152 #define CONFIG_SYS_SCSI_MAX_SCSI_ID 1 153 #define CONFIG_SYS_SCSI_MAX_LUN 1 154 #define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \ 155 CONFIG_SYS_SCSI_MAX_LUN) 156 157 /* NAND support */ 158 #ifdef CONFIG_NAND 159 /* NAND: device related configs */ 160 #define CONFIG_SYS_NAND_PAGE_SIZE 2048 161 #define CONFIG_SYS_NAND_OOBSIZE 64 162 #define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024) 163 #define CONFIG_SYS_NAND_PAGE_COUNT (CONFIG_SYS_NAND_BLOCK_SIZE / \ 164 CONFIG_SYS_NAND_PAGE_SIZE) 165 #define CONFIG_SYS_NAND_5_ADDR_CYCLE 166 /* NAND: driver related configs */ 167 #define CONFIG_SYS_NAND_ONFI_DETECTION 168 #define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_BCH8_CODE_HW 169 #define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS 170 #define CONFIG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \ 171 10, 11, 12, 13, 14, 15, 16, 17, \ 172 18, 19, 20, 21, 22, 23, 24, 25, \ 173 26, 27, 28, 29, 30, 31, 32, 33, \ 174 34, 35, 36, 37, 38, 39, 40, 41, \ 175 42, 43, 44, 45, 46, 47, 48, 49, \ 176 50, 51, 52, 53, 54, 55, 56, 57, } 177 #define CONFIG_SYS_NAND_ECCSIZE 512 178 #define CONFIG_SYS_NAND_ECCBYTES 14 179 #define MTDIDS_DEFAULT "nand0=nand.0" 180 #define MTDPARTS_DEFAULT "mtdparts=nand.0:" \ 181 "128k(NAND.SPL)," \ 182 "128k(NAND.SPL.backup1)," \ 183 "128k(NAND.SPL.backup2)," \ 184 "128k(NAND.SPL.backup3)," \ 185 "256k(NAND.u-boot-spl-os)," \ 186 "1m(NAND.u-boot)," \ 187 "128k(NAND.u-boot-env)," \ 188 "128k(NAND.u-boot-env.backup1)," \ 189 "8m(NAND.kernel)," \ 190 "-(NAND.file-system)" 191 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x000c0000 192 /* NAND: SPL related configs */ 193 /* NAND: SPL falcon mode configs */ 194 #ifdef CONFIG_SPL_OS_BOOT 195 #define CONFIG_SYS_NAND_SPL_KERNEL_OFFS 0x00200000 /* kernel offset */ 196 #endif 197 #endif /* !CONFIG_NAND */ 198 199 /* Parallel NOR Support */ 200 #if defined(CONFIG_NOR) 201 /* NOR: device related configs */ 202 #define CONFIG_SYS_MAX_FLASH_SECT 512 203 #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT 204 #define CONFIG_SYS_FLASH_SIZE (64 * 1024 * 1024) /* 64 MB */ 205 /* #define CONFIG_INIT_IGNORE_ERROR */ 206 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 207 #define CONFIG_SYS_FLASH_PROTECTION 208 #define CONFIG_SYS_FLASH_CFI 209 #define CONFIG_FLASH_CFI_DRIVER 210 #define CONFIG_FLASH_CFI_MTD 211 #define CONFIG_SYS_MAX_FLASH_BANKS 1 212 #define CONFIG_SYS_FLASH_BASE (0x08000000) 213 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE 214 /* Reduce SPL size by removing unlikey targets */ 215 #ifdef CONFIG_NOR_BOOT 216 #define CONFIG_ENV_SECT_SIZE (128 * 1024) /* 128 KiB */ 217 #define MTDIDS_DEFAULT "nor0=physmap-flash.0" 218 #define MTDPARTS_DEFAULT "mtdparts=physmap-flash.0:" \ 219 "128k(NOR.SPL)," \ 220 "128k(NOR.SPL.backup1)," \ 221 "128k(NOR.SPL.backup2)," \ 222 "128k(NOR.SPL.backup3)," \ 223 "256k(NOR.u-boot-spl-os)," \ 224 "1m(NOR.u-boot)," \ 225 "128k(NOR.u-boot-env)," \ 226 "128k(NOR.u-boot-env.backup1)," \ 227 "8m(NOR.kernel)," \ 228 "-(NOR.rootfs)" 229 #define CONFIG_ENV_OFFSET 0x001c0000 230 #define CONFIG_ENV_OFFSET_REDUND 0x001e0000 231 #endif 232 #endif /* NOR support */ 233 234 #endif /* __CONFIG_DRA7XX_EVM_H */ 235