1 /* 2 * (C) Copyright 2011 CompuLab, Ltd. 3 * Mike Rapoport <mike@compulab.co.il> 4 * Igor Grinberg <grinberg@compulab.co.il> 5 * 6 * Based on omap3_beagle.h 7 * (C) Copyright 2006-2008 8 * Texas Instruments. 9 * Richard Woodruff <r-woodruff2@ti.com> 10 * Syed Mohammed Khasim <x0khasim@ti.com> 11 * 12 * Configuration settings for the CompuLab CM-T35 and CM-T3730 boards 13 * 14 * SPDX-License-Identifier: GPL-2.0+ 15 */ 16 17 #ifndef __CONFIG_H 18 #define __CONFIG_H 19 20 #define CONFIG_SYS_CACHELINE_SIZE 64 21 22 /* 23 * High Level Configuration Options 24 */ 25 #define CONFIG_CM_T3X /* working with CM-T35 and CM-T3730 */ 26 27 #define CONFIG_SDRC /* The chip has SDRC controller */ 28 29 #include <asm/arch/cpu.h> /* get chip and board defs */ 30 #include <asm/arch/omap.h> 31 32 /* Clock Defines */ 33 #define V_OSCK 26000000 /* Clock output from T2 */ 34 #define V_SCLK (V_OSCK >> 1) 35 36 #define CONFIG_MISC_INIT_R 37 38 #define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ 39 #define CONFIG_SETUP_MEMORY_TAGS 40 #define CONFIG_INITRD_TAG 41 #define CONFIG_REVISION_TAG 42 #define CONFIG_SERIAL_TAG 43 44 /* 45 * Size of malloc() pool 46 */ 47 #define CONFIG_ENV_SIZE (16 << 10) /* 16 KiB */ 48 /* Sector */ 49 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10)) 50 51 /* 52 * Hardware drivers 53 */ 54 55 /* 56 * NS16550 Configuration 57 */ 58 #define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */ 59 60 #define CONFIG_SYS_NS16550_SERIAL 61 #define CONFIG_SYS_NS16550_REG_SIZE (-4) 62 #define CONFIG_SYS_NS16550_CLK V_NS16550_CLK 63 64 /* 65 * select serial console configuration 66 */ 67 #define CONFIG_CONS_INDEX 3 68 #define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3 69 #define CONFIG_SERIAL3 3 /* UART3 */ 70 71 /* allow to overwrite serial and ethaddr */ 72 #define CONFIG_ENV_OVERWRITE 73 #define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\ 74 115200} 75 76 /* USB */ 77 #define CONFIG_USB_OMAP3 78 #define CONFIG_USB_MUSB_UDC 79 #define CONFIG_TWL4030_USB 80 81 /* USB device configuration */ 82 #define CONFIG_USB_DEVICE 83 #define CONFIG_USB_TTY 84 85 /* commands to include */ 86 87 #define CONFIG_SYS_I2C 88 #define CONFIG_SYS_OMAP24_I2C_SPEED 100000 89 #define CONFIG_SYS_OMAP24_I2C_SLAVE 1 90 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 91 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 92 #define CONFIG_SYS_I2C_EEPROM_BUS 0 93 #define CONFIG_I2C_MULTI_BUS 94 95 /* 96 * TWL4030 97 */ 98 #define CONFIG_TWL4030_LED 99 100 /* 101 * Board NAND Info. 102 */ 103 #define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */ 104 /* to access nand */ 105 #define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */ 106 /* to access nand at */ 107 /* CS0 */ 108 #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */ 109 /* devices */ 110 111 /* Environment information */ 112 #define CONFIG_EXTRA_ENV_SETTINGS \ 113 "loadaddr=0x82000000\0" \ 114 "usbtty=cdc_acm\0" \ 115 "console=ttyO2,115200n8\0" \ 116 "mpurate=500\0" \ 117 "vram=12M\0" \ 118 "dvimode=1024x768MR-16@60\0" \ 119 "defaultdisplay=dvi\0" \ 120 "mmcdev=0\0" \ 121 "mmcroot=/dev/mmcblk0p2 rw\0" \ 122 "mmcrootfstype=ext4 rootwait\0" \ 123 "nandroot=/dev/mtdblock4 rw\0" \ 124 "nandrootfstype=ubifs\0" \ 125 "mmcargs=setenv bootargs console=${console} " \ 126 "mpurate=${mpurate} " \ 127 "vram=${vram} " \ 128 "omapfb.mode=dvi:${dvimode} " \ 129 "omapdss.def_disp=${defaultdisplay} " \ 130 "root=${mmcroot} " \ 131 "rootfstype=${mmcrootfstype}\0" \ 132 "nandargs=setenv bootargs console=${console} " \ 133 "mpurate=${mpurate} " \ 134 "vram=${vram} " \ 135 "omapfb.mode=dvi:${dvimode} " \ 136 "omapdss.def_disp=${defaultdisplay} " \ 137 "root=${nandroot} " \ 138 "rootfstype=${nandrootfstype}\0" \ 139 "loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \ 140 "bootscript=echo Running bootscript from mmc ...; " \ 141 "source ${loadaddr}\0" \ 142 "loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \ 143 "mmcboot=echo Booting from mmc ...; " \ 144 "run mmcargs; " \ 145 "bootm ${loadaddr}\0" \ 146 "nandboot=echo Booting from nand ...; " \ 147 "run nandargs; " \ 148 "nand read ${loadaddr} 2a0000 400000; " \ 149 "bootm ${loadaddr}\0" \ 150 151 #define CONFIG_BOOTCOMMAND \ 152 "mmc dev ${mmcdev}; if mmc rescan; then " \ 153 "if run loadbootscript; then " \ 154 "run bootscript; " \ 155 "else " \ 156 "if run loaduimage; then " \ 157 "run mmcboot; " \ 158 "else run nandboot; " \ 159 "fi; " \ 160 "fi; " \ 161 "else run nandboot; fi" 162 163 /* 164 * Miscellaneous configurable options 165 */ 166 #define CONFIG_AUTO_COMPLETE 167 #define CONFIG_CMDLINE_EDITING 168 #define CONFIG_TIMESTAMP 169 #define CONFIG_SYS_AUTOLOAD "no" 170 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 171 172 #define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0) /* memtest */ 173 /* works on */ 174 #define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + \ 175 0x01F00000) /* 31MB */ 176 177 #define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default */ 178 /* load address */ 179 180 /* 181 * OMAP3 has 12 GP timers, they can be driven by the system clock 182 * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK). 183 * This rate is divided by a local divisor. 184 */ 185 #define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2) 186 #define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ 187 188 /*----------------------------------------------------------------------- 189 * Physical Memory Map 190 */ 191 #define CONFIG_NR_DRAM_BANKS 1 /* CS1 is never populated */ 192 #define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0 193 194 /*----------------------------------------------------------------------- 195 * FLASH and environment organization 196 */ 197 198 /* **** PISMO SUPPORT *** */ 199 /* Monitor at start of flash */ 200 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE 201 #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */ 202 203 #define SMNAND_ENV_OFFSET 0x260000 /* environment starts here */ 204 #define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET 205 #define CONFIG_ENV_ADDR SMNAND_ENV_OFFSET 206 207 #if defined(CONFIG_CMD_NET) 208 #define CONFIG_SMC911X 209 #define CONFIG_SMC911X_32_BIT 210 #define CM_T3X_SMC911X_BASE 0x2C000000 211 #define SB_T35_SMC911X_BASE (CM_T3X_SMC911X_BASE + (16 << 20)) 212 #define CONFIG_SMC911X_BASE CM_T3X_SMC911X_BASE 213 #endif /* (CONFIG_CMD_NET) */ 214 215 /* additions for new relocation code, must be added to all boards */ 216 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 217 #define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800 218 #define CONFIG_SYS_INIT_RAM_SIZE 0x800 219 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ 220 CONFIG_SYS_INIT_RAM_SIZE - \ 221 GENERATED_GBL_DATA_SIZE) 222 223 /* Status LED */ 224 #define GREEN_LED_GPIO 186 /* CM-T35 Green LED is GPIO186 */ 225 226 #define CONFIG_SPLASHIMAGE_GUARD 227 228 /* Display Configuration */ 229 #define CONFIG_VIDEO_OMAP3 230 #define LCD_BPP LCD_COLOR16 231 232 #define CONFIG_SPLASH_SCREEN 233 #define CONFIG_SPLASH_SOURCE 234 #define CONFIG_BMP_16BPP 235 #define CONFIG_SCF0403_LCD 236 237 /* Defines for SPL */ 238 #define CONFIG_SPL_FRAMEWORK 239 240 #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 241 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" 242 243 #define CONFIG_SPL_NAND_BASE 244 #define CONFIG_SPL_NAND_DRIVERS 245 #define CONFIG_SPL_NAND_ECC 246 247 /* NAND boot config */ 248 #define CONFIG_SYS_NAND_5_ADDR_CYCLE 249 #define CONFIG_SYS_NAND_PAGE_COUNT 64 250 #define CONFIG_SYS_NAND_PAGE_SIZE 2048 251 #define CONFIG_SYS_NAND_OOBSIZE 64 252 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 253 #define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS 254 /* 255 * Use the ECC/OOB layout from omap_gpmc.h that matches your chip: 256 * SP vs LP, 8bit vs 16bit: GPMC_NAND_HW_ECC_LAYOUT 257 */ 258 #define CONFIG_SYS_NAND_ECCPOS { 1, 2, 3, 4, 5, 6, 7, 8, 9, \ 259 10, 11, 12 } 260 #define CONFIG_SYS_NAND_ECCSIZE 512 261 #define CONFIG_SYS_NAND_ECCBYTES 3 262 #define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_HAM1_CODE_HW 263 264 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE 265 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000 266 267 #define CONFIG_SPL_TEXT_BASE 0x40200800 268 #define CONFIG_SPL_MAX_SIZE (SRAM_SCRATCH_SPACE_ADDR - \ 269 CONFIG_SPL_TEXT_BASE) 270 271 /* 272 * Use 0x80008000 as TEXT_BASE here for compatibility reasons with the 273 * older x-loader implementations. And move the BSS area so that it 274 * doesn't overlap with TEXT_BASE. 275 */ 276 #define CONFIG_SYS_TEXT_BASE 0x80008000 277 #define CONFIG_SPL_BSS_START_ADDR 0x80100000 278 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* 512 KB */ 279 280 #define CONFIG_SYS_SPL_MALLOC_START 0x80208000 281 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 282 283 /* EEPROM */ 284 #define CONFIG_ENV_EEPROM_IS_ON_I2C 285 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 286 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 287 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 288 #define CONFIG_SYS_EEPROM_SIZE 256 289 290 #endif /* __CONFIG_H */ 291