1 /* 2 * Copyright 2014 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 /* 8 * T4240 RDB board configuration file 9 */ 10 #ifndef __CONFIG_H 11 #define __CONFIG_H 12 13 #define CONFIG_FSL_SATA_V2 14 #define CONFIG_PCIE4 15 16 #define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */ 17 18 #ifdef CONFIG_RAMBOOT_PBL 19 #define CONFIG_SYS_FSL_PBL_PBI $(SRCTREE)/board/freescale/t4rdb/t4_pbi.cfg 20 #ifndef CONFIG_SDCARD 21 #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE 22 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc 23 #else 24 #define CONFIG_SPL_FLUSH_IMAGE 25 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 26 #define CONFIG_SYS_TEXT_BASE 0x00201000 27 #define CONFIG_SPL_TEXT_BASE 0xFFFD8000 28 #define CONFIG_SPL_PAD_TO 0x40000 29 #define CONFIG_SPL_MAX_SIZE 0x28000 30 #define RESET_VECTOR_OFFSET 0x27FFC 31 #define BOOT_PAGE_OFFSET 0x27000 32 33 #ifdef CONFIG_SDCARD 34 #define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC 35 #define CONFIG_SPL_MMC_MINIMAL 36 #define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10) 37 #define CONFIG_SYS_MMC_U_BOOT_DST 0x00200000 38 #define CONFIG_SYS_MMC_U_BOOT_START 0x00200000 39 #define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10) 40 #ifndef CONFIG_SPL_BUILD 41 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 42 #endif 43 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 44 #define CONFIG_SYS_FSL_PBL_RCW $(SRCTREE)/board/freescale/t4rdb/t4_sd_rcw.cfg 45 #define CONFIG_SPL_MMC_BOOT 46 #endif 47 48 #ifdef CONFIG_SPL_BUILD 49 #define CONFIG_SPL_SKIP_RELOCATE 50 #define CONFIG_SPL_COMMON_INIT_DDR 51 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE 52 #endif 53 54 #endif 55 #endif /* CONFIG_RAMBOOT_PBL */ 56 57 #define CONFIG_DDR_ECC 58 59 /* High Level Configuration Options */ 60 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ 61 #define CONFIG_MP /* support multiple processors */ 62 63 #ifndef CONFIG_SYS_TEXT_BASE 64 #define CONFIG_SYS_TEXT_BASE 0xeff40000 65 #endif 66 67 #ifndef CONFIG_RESET_VECTOR_ADDRESS 68 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 69 #endif 70 71 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ 72 #define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS 73 #define CONFIG_PCIE1 /* PCIE controller 1 */ 74 #define CONFIG_PCIE2 /* PCIE controller 2 */ 75 #define CONFIG_PCIE3 /* PCIE controller 3 */ 76 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 77 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 78 79 #define CONFIG_ENV_OVERWRITE 80 81 /* 82 * These can be toggled for performance analysis, otherwise use default. 83 */ 84 #define CONFIG_SYS_CACHE_STASHING 85 #define CONFIG_BTB /* toggle branch predition */ 86 #ifdef CONFIG_DDR_ECC 87 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 88 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef 89 #endif 90 91 #define CONFIG_ENABLE_36BIT_PHYS 92 93 #define CONFIG_ADDR_MAP 94 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ 95 96 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 97 #define CONFIG_SYS_MEMTEST_END 0x00400000 98 #define CONFIG_SYS_ALT_MEMTEST 99 100 /* 101 * Config the L3 Cache as L3 SRAM 102 */ 103 #define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000 104 #define CONFIG_SYS_L3_SIZE (512 << 10) 105 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024) 106 #ifdef CONFIG_RAMBOOT_PBL 107 #define CONFIG_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024) 108 #endif 109 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024) 110 #define CONFIG_SPL_RELOC_MALLOC_SIZE (50 << 10) 111 #define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024) 112 #define CONFIG_SPL_RELOC_STACK_SIZE (22 << 10) 113 114 #define CONFIG_SYS_DCSRBAR 0xf0000000 115 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull 116 117 /* 118 * DDR Setup 119 */ 120 #define CONFIG_VERY_BIG_RAM 121 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 122 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 123 124 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 125 #define CONFIG_CHIP_SELECTS_PER_CTRL 4 126 #define CONFIG_FSL_DDR_FIRST_SLOT_QUAD_CAPABLE 127 128 #define CONFIG_DDR_SPD 129 130 /* 131 * IFC Definitions 132 */ 133 #define CONFIG_SYS_FLASH_BASE 0xe0000000 134 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) 135 136 #ifdef CONFIG_SPL_BUILD 137 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE 138 #else 139 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE 140 #endif 141 142 #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */ 143 #define CONFIG_MISC_INIT_R 144 145 #define CONFIG_HWCONFIG 146 147 /* define to use L1 as initial stack */ 148 #define CONFIG_L1_INIT_RAM 149 #define CONFIG_SYS_INIT_RAM_LOCK 150 #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ 151 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf 152 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000 153 /* The assembler doesn't like typecast */ 154 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ 155 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ 156 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) 157 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 158 159 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ 160 GENERATED_GBL_DATA_SIZE) 161 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 162 163 #define CONFIG_SYS_MONITOR_LEN (768 * 1024) 164 #define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024) 165 166 /* Serial Port - controlled on board with jumper J8 167 * open - index 2 168 * shorted - index 1 169 */ 170 #define CONFIG_CONS_INDEX 1 171 #define CONFIG_SYS_NS16550_SERIAL 172 #define CONFIG_SYS_NS16550_REG_SIZE 1 173 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) 174 175 #define CONFIG_SYS_BAUDRATE_TABLE \ 176 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 177 178 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) 179 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) 180 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) 181 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) 182 183 /* I2C */ 184 #define CONFIG_SYS_I2C 185 #define CONFIG_SYS_I2C_FSL 186 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 187 #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 188 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 189 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100 190 191 /* 192 * General PCI 193 * Memory space is mapped 1-1, but I/O space must start from 0. 194 */ 195 196 /* controller 1, direct to uli, tgtid 3, Base address 20000 */ 197 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 198 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 199 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull 200 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 201 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 202 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 203 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull 204 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 205 206 /* controller 2, Slot 2, tgtid 2, Base address 201000 */ 207 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 208 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 209 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull 210 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ 211 #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 212 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 213 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull 214 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 215 216 /* controller 3, Slot 1, tgtid 1, Base address 202000 */ 217 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xc0000000 218 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 219 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc40000000ull 220 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */ 221 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 222 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 223 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull 224 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ 225 226 /* controller 4, Base address 203000 */ 227 #define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000 228 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc60000000ull 229 #define CONFIG_SYS_PCIE4_MEM_SIZE 0x20000000 /* 512M */ 230 #define CONFIG_SYS_PCIE4_IO_BUS 0x00000000 231 #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull 232 #define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */ 233 234 #ifdef CONFIG_PCI 235 #define CONFIG_PCI_INDIRECT_BRIDGE 236 237 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 238 #endif /* CONFIG_PCI */ 239 240 /* SATA */ 241 #ifdef CONFIG_FSL_SATA_V2 242 #define CONFIG_LIBATA 243 #define CONFIG_FSL_SATA 244 245 #define CONFIG_SYS_SATA_MAX_DEVICE 2 246 #define CONFIG_SATA1 247 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR 248 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA 249 #define CONFIG_SATA2 250 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR 251 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA 252 253 #define CONFIG_LBA48 254 #endif 255 256 #ifdef CONFIG_FMAN_ENET 257 #define CONFIG_MII /* MII PHY management */ 258 #define CONFIG_ETHPRIME "FM1@DTSEC1" 259 #endif 260 261 /* 262 * Environment 263 */ 264 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 265 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 266 267 /* 268 * Command line configuration. 269 */ 270 271 /* 272 * Miscellaneous configurable options 273 */ 274 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 275 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 276 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 277 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 278 279 /* 280 * For booting Linux, the board info and command line data 281 * have to be in the first 64 MB of memory, since this is 282 * the maximum mapped by the Linux kernel during initialization. 283 */ 284 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/ 285 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 286 287 #ifdef CONFIG_CMD_KGDB 288 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 289 #endif 290 291 /* 292 * Environment Configuration 293 */ 294 #define CONFIG_ROOTPATH "/opt/nfsroot" 295 #define CONFIG_BOOTFILE "uImage" 296 #define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server*/ 297 298 /* default location for tftp and bootm */ 299 #define CONFIG_LOADADDR 1000000 300 301 #define CONFIG_HVBOOT \ 302 "setenv bootargs config-addr=0x60000000; " \ 303 "bootm 0x01000000 - 0x00f00000" 304 305 #ifndef CONFIG_MTD_NOR_FLASH 306 #else 307 #define CONFIG_FLASH_CFI_DRIVER 308 #define CONFIG_SYS_FLASH_CFI 309 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 310 #endif 311 312 #if defined(CONFIG_SPIFLASH) 313 #define CONFIG_SYS_EXTRA_ENV_RELOC 314 #define CONFIG_ENV_SPI_BUS 0 315 #define CONFIG_ENV_SPI_CS 0 316 #define CONFIG_ENV_SPI_MAX_HZ 10000000 317 #define CONFIG_ENV_SPI_MODE 0 318 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 319 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 320 #define CONFIG_ENV_SECT_SIZE 0x10000 321 #elif defined(CONFIG_SDCARD) 322 #define CONFIG_SYS_EXTRA_ENV_RELOC 323 #define CONFIG_SYS_MMC_ENV_DEV 0 324 #define CONFIG_ENV_SIZE 0x2000 325 #define CONFIG_ENV_OFFSET (512 * 0x800) 326 #elif defined(CONFIG_NAND) 327 #define CONFIG_SYS_EXTRA_ENV_RELOC 328 #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE 329 #define CONFIG_ENV_OFFSET (7 * CONFIG_SYS_NAND_BLOCK_SIZE) 330 #elif defined(CONFIG_ENV_IS_NOWHERE) 331 #define CONFIG_ENV_SIZE 0x2000 332 #else 333 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 334 #define CONFIG_ENV_SIZE 0x2000 335 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 336 #endif 337 338 #define CONFIG_SYS_CLK_FREQ 66666666 339 #define CONFIG_DDR_CLK_FREQ 133333333 340 341 #ifndef __ASSEMBLY__ 342 unsigned long get_board_sys_clk(void); 343 unsigned long get_board_ddr_clk(void); 344 #endif 345 346 /* 347 * DDR Setup 348 */ 349 #define CONFIG_SYS_SPD_BUS_NUM 0 350 #define SPD_EEPROM_ADDRESS1 0x52 351 #define SPD_EEPROM_ADDRESS2 0x54 352 #define SPD_EEPROM_ADDRESS3 0x56 353 #define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 /* for p3041/p5010 */ 354 #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ 355 356 /* 357 * IFC Definitions 358 */ 359 #define CONFIG_SYS_NOR0_CSPR_EXT (0xf) 360 #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \ 361 + 0x8000000) | \ 362 CSPR_PORT_SIZE_16 | \ 363 CSPR_MSEL_NOR | \ 364 CSPR_V) 365 #define CONFIG_SYS_NOR1_CSPR_EXT (0xf) 366 #define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ 367 CSPR_PORT_SIZE_16 | \ 368 CSPR_MSEL_NOR | \ 369 CSPR_V) 370 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) 371 /* NOR Flash Timing Params */ 372 #define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80 373 374 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ 375 FTIM0_NOR_TEADC(0x5) | \ 376 FTIM0_NOR_TEAHC(0x5)) 377 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ 378 FTIM1_NOR_TRAD_NOR(0x1A) |\ 379 FTIM1_NOR_TSEQRAD_NOR(0x13)) 380 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ 381 FTIM2_NOR_TCH(0x4) | \ 382 FTIM2_NOR_TWPH(0x0E) | \ 383 FTIM2_NOR_TWP(0x1c)) 384 #define CONFIG_SYS_NOR_FTIM3 0x0 385 386 #define CONFIG_SYS_FLASH_QUIET_TEST 387 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 388 389 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 390 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 391 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 392 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 393 394 #define CONFIG_SYS_FLASH_EMPTY_INFO 395 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS \ 396 + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS} 397 398 /* NAND Flash on IFC */ 399 #define CONFIG_NAND_FSL_IFC 400 #define CONFIG_SYS_NAND_MAX_ECCPOS 256 401 #define CONFIG_SYS_NAND_MAX_OOBFREE 2 402 #define CONFIG_SYS_NAND_BASE 0xff800000 403 #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE) 404 405 #define CONFIG_SYS_NAND_CSPR_EXT (0xf) 406 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 407 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ 408 | CSPR_MSEL_NAND /* MSEL = NAND */ \ 409 | CSPR_V) 410 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) 411 412 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 413 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 414 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 415 | CSOR_NAND_RAL_3 /* RAL = 2Byes */ \ 416 | CSOR_NAND_PGS_4K /* Page Size = 4K */ \ 417 | CSOR_NAND_SPRZ_224 /* Spare size = 224 */ \ 418 | CSOR_NAND_PB(128)) /*Page Per Block = 128*/ 419 420 #define CONFIG_SYS_NAND_ONFI_DETECTION 421 422 /* ONFI NAND Flash mode0 Timing Params */ 423 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ 424 FTIM0_NAND_TWP(0x18) | \ 425 FTIM0_NAND_TWCHT(0x07) | \ 426 FTIM0_NAND_TWH(0x0a)) 427 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ 428 FTIM1_NAND_TWBE(0x39) | \ 429 FTIM1_NAND_TRR(0x0e) | \ 430 FTIM1_NAND_TRP(0x18)) 431 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ 432 FTIM2_NAND_TREH(0x0a) | \ 433 FTIM2_NAND_TWHRE(0x1e)) 434 #define CONFIG_SYS_NAND_FTIM3 0x0 435 436 #define CONFIG_SYS_NAND_DDR_LAW 11 437 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 438 #define CONFIG_SYS_MAX_NAND_DEVICE 1 439 440 #define CONFIG_SYS_NAND_BLOCK_SIZE (512 * 1024) 441 442 #if defined(CONFIG_NAND) 443 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT 444 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR 445 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK 446 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR 447 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 448 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 449 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 450 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 451 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR0_CSPR_EXT 452 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR0_CSPR 453 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK 454 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR 455 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0 456 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1 457 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2 458 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3 459 #else 460 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT 461 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR 462 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 463 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 464 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 465 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 466 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 467 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 468 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT 469 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR 470 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK 471 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR 472 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0 473 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1 474 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2 475 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3 476 #endif 477 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT 478 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR 479 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK 480 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR 481 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0 482 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1 483 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2 484 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3 485 486 /* CPLD on IFC */ 487 #define CONFIG_SYS_CPLD_BASE 0xffdf0000 488 #define CONFIG_SYS_CPLD_BASE_PHYS (0xf00000000ull | CONFIG_SYS_CPLD_BASE) 489 #define CONFIG_SYS_CSPR3_EXT (0xf) 490 #define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) \ 491 | CSPR_PORT_SIZE_8 \ 492 | CSPR_MSEL_GPCM \ 493 | CSPR_V) 494 495 #define CONFIG_SYS_AMASK3 IFC_AMASK(4*1024) 496 #define CONFIG_SYS_CSOR3 0x0 497 498 /* CPLD Timing parameters for IFC CS3 */ 499 #define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ 500 FTIM0_GPCM_TEADC(0x0e) | \ 501 FTIM0_GPCM_TEAHC(0x0e)) 502 #define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \ 503 FTIM1_GPCM_TRAD(0x1f)) 504 #define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ 505 FTIM2_GPCM_TCH(0x8) | \ 506 FTIM2_GPCM_TWP(0x1f)) 507 #define CONFIG_SYS_CS3_FTIM3 0x0 508 509 #if defined(CONFIG_RAMBOOT_PBL) 510 #define CONFIG_SYS_RAMBOOT 511 #endif 512 513 /* I2C */ 514 #define CONFIG_SYS_FSL_I2C_SPEED 100000 /* I2C speed */ 515 #define CONFIG_SYS_FSL_I2C2_SPEED 100000 /* I2C2 speed */ 516 #define I2C_MUX_PCA_ADDR_PRI 0x77 /* I2C bus multiplexer,primary */ 517 #define I2C_MUX_PCA_ADDR_SEC 0x76 /* I2C bus multiplexer,secondary */ 518 519 #define I2C_MUX_CH_DEFAULT 0x8 520 #define I2C_MUX_CH_VOL_MONITOR 0xa 521 #define I2C_MUX_CH_VSC3316_FS 0xc 522 #define I2C_MUX_CH_VSC3316_BS 0xd 523 524 /* Voltage monitor on channel 2*/ 525 #define I2C_VOL_MONITOR_ADDR 0x40 526 #define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2 527 #define I2C_VOL_MONITOR_BUS_V_OVF 0x1 528 #define I2C_VOL_MONITOR_BUS_V_SHIFT 3 529 530 #define CONFIG_VID_FLS_ENV "t4240rdb_vdd_mv" 531 #ifndef CONFIG_SPL_BUILD 532 #define CONFIG_VID 533 #endif 534 #define CONFIG_VOL_MONITOR_IR36021_SET 535 #define CONFIG_VOL_MONITOR_IR36021_READ 536 /* The lowest and highest voltage allowed for T4240RDB */ 537 #define VDD_MV_MIN 819 538 #define VDD_MV_MAX 1212 539 540 /* 541 * eSPI - Enhanced SPI 542 */ 543 #define CONFIG_SF_DEFAULT_SPEED 10000000 544 #define CONFIG_SF_DEFAULT_MODE 0 545 546 /* Qman/Bman */ 547 #ifndef CONFIG_NOBQFMAN 548 #define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */ 549 #define CONFIG_SYS_BMAN_NUM_PORTALS 50 550 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 551 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull 552 #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000 553 #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000 554 #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000 555 #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE 556 #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 557 #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \ 558 CONFIG_SYS_BMAN_CENA_SIZE) 559 #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 560 #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08 561 #define CONFIG_SYS_QMAN_NUM_PORTALS 50 562 #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000 563 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull 564 #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000 565 #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000 566 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000 567 #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE 568 #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 569 #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ 570 CONFIG_SYS_QMAN_CENA_SIZE) 571 #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 572 #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08 573 574 #define CONFIG_SYS_DPAA_FMAN 575 #define CONFIG_SYS_DPAA_PME 576 #define CONFIG_SYS_PMAN 577 #define CONFIG_SYS_DPAA_DCE 578 #define CONFIG_SYS_DPAA_RMAN 579 #define CONFIG_SYS_INTERLAKEN 580 581 /* Default address of microcode for the Linux Fman driver */ 582 #if defined(CONFIG_SPIFLASH) 583 /* 584 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after 585 * env, so we got 0x110000. 586 */ 587 #define CONFIG_SYS_QE_FW_IN_SPIFLASH 588 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000 589 #elif defined(CONFIG_SDCARD) 590 /* 591 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is 592 * about 1MB (2048 blocks), Env is stored after the image, and the env size is 593 * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080. 594 */ 595 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC 596 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820) 597 #elif defined(CONFIG_NAND) 598 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND 599 #define CONFIG_SYS_FMAN_FW_ADDR (8 * CONFIG_SYS_NAND_BLOCK_SIZE) 600 #else 601 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR 602 #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000 603 #endif 604 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 605 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) 606 #endif /* CONFIG_NOBQFMAN */ 607 608 #ifdef CONFIG_SYS_DPAA_FMAN 609 #define CONFIG_FMAN_ENET 610 #define CONFIG_PHYLIB_10G 611 #define CONFIG_PHY_VITESSE 612 #define CONFIG_PHY_CORTINA 613 #define CONFIG_SYS_CORTINA_FW_IN_NOR 614 #define CONFIG_CORTINA_FW_ADDR 0xefe00000 615 #define CONFIG_CORTINA_FW_LENGTH 0x40000 616 #define CONFIG_PHY_TERANETICS 617 #define SGMII_PHY_ADDR1 0x0 618 #define SGMII_PHY_ADDR2 0x1 619 #define SGMII_PHY_ADDR3 0x2 620 #define SGMII_PHY_ADDR4 0x3 621 #define SGMII_PHY_ADDR5 0x4 622 #define SGMII_PHY_ADDR6 0x5 623 #define SGMII_PHY_ADDR7 0x6 624 #define SGMII_PHY_ADDR8 0x7 625 #define FM1_10GEC1_PHY_ADDR 0x10 626 #define FM1_10GEC2_PHY_ADDR 0x11 627 #define FM2_10GEC1_PHY_ADDR 0x12 628 #define FM2_10GEC2_PHY_ADDR 0x13 629 #define CORTINA_PHY_ADDR1 FM1_10GEC1_PHY_ADDR 630 #define CORTINA_PHY_ADDR2 FM1_10GEC2_PHY_ADDR 631 #define CORTINA_PHY_ADDR3 FM2_10GEC1_PHY_ADDR 632 #define CORTINA_PHY_ADDR4 FM2_10GEC2_PHY_ADDR 633 #endif 634 635 /* SATA */ 636 #ifdef CONFIG_FSL_SATA_V2 637 #define CONFIG_LIBATA 638 #define CONFIG_FSL_SATA 639 640 #define CONFIG_SYS_SATA_MAX_DEVICE 2 641 #define CONFIG_SATA1 642 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR 643 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA 644 #define CONFIG_SATA2 645 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR 646 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA 647 648 #define CONFIG_LBA48 649 #endif 650 651 #ifdef CONFIG_FMAN_ENET 652 #define CONFIG_MII /* MII PHY management */ 653 #define CONFIG_ETHPRIME "FM1@DTSEC1" 654 #endif 655 656 /* 657 * USB 658 */ 659 #define CONFIG_USB_EHCI_FSL 660 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 661 #define CONFIG_HAS_FSL_DR_USB 662 663 #ifdef CONFIG_MMC 664 #define CONFIG_FSL_ESDHC 665 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 666 #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT 667 #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33 668 #endif 669 670 671 #define __USB_PHY_TYPE utmi 672 673 /* 674 * T4240 has 3 DDR controllers. Default to 3-way interleaving. It can be 675 * 3way_1KB, 3way_4KB, 3way_8KB. T4160 has 2 DDR controllers. Default to 2-way 676 * interleaving. It can be cacheline, page, bank, superbank. 677 * See doc/README.fsl-ddr for details. 678 */ 679 #ifdef CONFIG_ARCH_T4240 680 #define CTRL_INTLV_PREFERED 3way_4KB 681 #else 682 #define CTRL_INTLV_PREFERED cacheline 683 #endif 684 685 #define CONFIG_EXTRA_ENV_SETTINGS \ 686 "hwconfig=fsl_ddr:" \ 687 "ctlr_intlv=" __stringify(CTRL_INTLV_PREFERED) "," \ 688 "bank_intlv=auto;" \ 689 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\ 690 "netdev=eth0\0" \ 691 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 692 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ 693 "tftpflash=tftpboot $loadaddr $uboot && " \ 694 "protect off $ubootaddr +$filesize && " \ 695 "erase $ubootaddr +$filesize && " \ 696 "cp.b $loadaddr $ubootaddr $filesize && " \ 697 "protect on $ubootaddr +$filesize && " \ 698 "cmp.b $loadaddr $ubootaddr $filesize\0" \ 699 "consoledev=ttyS0\0" \ 700 "ramdiskaddr=2000000\0" \ 701 "ramdiskfile=t4240rdb/ramdisk.uboot\0" \ 702 "fdtaddr=1e00000\0" \ 703 "fdtfile=t4240rdb/t4240rdb.dtb\0" \ 704 "bdev=sda3\0" 705 706 #define CONFIG_HVBOOT \ 707 "setenv bootargs config-addr=0x60000000; " \ 708 "bootm 0x01000000 - 0x00f00000" 709 710 #define CONFIG_LINUX \ 711 "setenv bootargs root=/dev/ram rw " \ 712 "console=$consoledev,$baudrate $othbootargs;" \ 713 "setenv ramdiskaddr 0x02000000;" \ 714 "setenv fdtaddr 0x00c00000;" \ 715 "setenv loadaddr 0x1000000;" \ 716 "bootm $loadaddr $ramdiskaddr $fdtaddr" 717 718 #define CONFIG_HDBOOT \ 719 "setenv bootargs root=/dev/$bdev rw " \ 720 "console=$consoledev,$baudrate $othbootargs;" \ 721 "tftp $loadaddr $bootfile;" \ 722 "tftp $fdtaddr $fdtfile;" \ 723 "bootm $loadaddr - $fdtaddr" 724 725 #define CONFIG_NFSBOOTCOMMAND \ 726 "setenv bootargs root=/dev/nfs rw " \ 727 "nfsroot=$serverip:$rootpath " \ 728 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 729 "console=$consoledev,$baudrate $othbootargs;" \ 730 "tftp $loadaddr $bootfile;" \ 731 "tftp $fdtaddr $fdtfile;" \ 732 "bootm $loadaddr - $fdtaddr" 733 734 #define CONFIG_RAMBOOTCOMMAND \ 735 "setenv bootargs root=/dev/ram rw " \ 736 "console=$consoledev,$baudrate $othbootargs;" \ 737 "tftp $ramdiskaddr $ramdiskfile;" \ 738 "tftp $loadaddr $bootfile;" \ 739 "tftp $fdtaddr $fdtfile;" \ 740 "bootm $loadaddr $ramdiskaddr $fdtaddr" 741 742 #define CONFIG_BOOTCOMMAND CONFIG_LINUX 743 744 #include <asm/fsl_secure_boot.h> 745 746 #endif /* __CONFIG_H */ 747