1 /* 2 * This is from the ARM TF Project, 3 * Repository: https://github.com/ARM-software/arm-trusted-firmware.git 4 * File: include/common/bl_common.h 5 * Portions copyright (c) 2013-2016, ARM Limited and Contributors. All rights 6 * reserved. 7 * Copyright (C) 2016-2017 Rockchip Electronic Co.,Ltd 8 * 9 * SPDX-License-Identifier: BSD-3-Clause 10 */ 11 12 #ifndef __BL_COMMON_H__ 13 #define __BL_COMMON_H__ 14 15 #define ATF_PARAM_EP 0x01 16 #define ATF_PARAM_IMAGE_BINARY 0x02 17 #define ATF_PARAM_BL31 0x03 18 19 #define ATF_VERSION_1 0x01 20 21 #define ATF_EP_SECURE 0x0 22 #define ATF_EP_NON_SECURE 0x1 23 24 #define SET_PARAM_HEAD(_p, _type, _ver, _attr) do { \ 25 (_p)->h.type = (uint8_t)(_type); \ 26 (_p)->h.version = (uint8_t)(_ver); \ 27 (_p)->h.size = (uint16_t)sizeof(*_p); \ 28 (_p)->h.attr = (uint32_t)(_attr) ; \ 29 } while (0) 30 31 /* ARM64 */ 32 #define MODE_RW_SHIFT 0x4 33 #define MODE_RW_MASK 0x1 34 #define MODE_RW_64 0x0 35 #define MODE_RW_32 0x1 36 37 #define MODE_EL_SHIFT 0x2 38 #define MODE_EL_MASK 0x3 39 #define MODE_EL3 0x3 40 #define MODE_EL2 0x2 41 #define MODE_EL1 0x1 42 #define MODE_EL0 0x0 43 44 #define MODE_SP_SHIFT 0x0 45 #define MODE_SP_MASK 0x1 46 #define MODE_SP_EL0 0x0 47 #define MODE_SP_ELX 0x1 48 49 #define SPSR_DAIF_SHIFT 6 50 #define SPSR_DAIF_MASK 0x0f 51 52 #define SPSR_64(el, sp, daif) \ 53 (MODE_RW_64 << MODE_RW_SHIFT | \ 54 ((el) & MODE_EL_MASK) << MODE_EL_SHIFT | \ 55 ((sp) & MODE_SP_MASK) << MODE_SP_SHIFT | \ 56 ((daif) & SPSR_DAIF_MASK) << SPSR_DAIF_SHIFT) 57 58 #define SPSR_FIQ (1 << 6) 59 #define SPSR_IRQ (1 << 7) 60 #define SPSR_SERROR (1 << 8) 61 #define SPSR_DEBUG (1 << 9) 62 #define SPSR_EXCEPTION_MASK (SPSR_FIQ | SPSR_IRQ | SPSR_SERROR | SPSR_DEBUG) 63 64 #define DAIF_FIQ_BIT (1<<0) 65 #define DAIF_IRQ_BIT (1<<1) 66 #define DAIF_ABT_BIT (1<<2) 67 #define DAIF_DBG_BIT (1<<3) 68 #define DISABLE_ALL_EXECPTIONS \ 69 (DAIF_FIQ_BIT | DAIF_IRQ_BIT | DAIF_ABT_BIT | DAIF_DBG_BIT) 70 71 /* ARM */ 72 #define MODE32_SHIFT 0 73 #define MODE32_MASK 0x1f 74 #define MODE32_svc 0x13 75 76 #define SPSR_FIQ_BIT (1 << 0) 77 #define SPSR_IRQ_BIT (1 << 1) 78 #define SPSR_ABT_BIT (1 << 2) 79 #define SPSR_AIF_SHIFT 6 80 #define SPSR_AIF_MASK 0x7 81 82 #define EP_EE_LITTLE 0x0 83 #define SPSR_E_SHIFT 9 84 #define SPSR_E_MASK 0x1 85 #define SPSR_T_SHIFT 5 86 #define SPSR_T_MASK 0x1 87 #define SPSR_T_ARM 0 88 89 #define DISABLE_ALL_EXECPTIONS_32 \ 90 (SPSR_FIQ_BIT | SPSR_IRQ_BIT | SPSR_ABT_BIT) 91 92 #define SPSR_32(mode, isa, endian, aif) \ 93 (MODE_RW_32 << MODE_RW_SHIFT | \ 94 ((mode) & MODE32_MASK) << MODE32_SHIFT | \ 95 ((isa) & SPSR_T_MASK) << SPSR_T_SHIFT | \ 96 ((endian) & SPSR_E_MASK) << SPSR_E_SHIFT | \ 97 ((aif) & SPSR_AIF_MASK) << SPSR_AIF_SHIFT) 98 99 #ifndef __ASSEMBLY__ 100 101 /******************************************************************************* 102 * Structure used for telling the next BL how much of a particular type of 103 * memory is available for its use and how much is already used. 104 ******************************************************************************/ 105 struct aapcs64_params { 106 unsigned long arg0; 107 unsigned long arg1; 108 unsigned long arg2; 109 unsigned long arg3; 110 unsigned long arg4; 111 unsigned long arg5; 112 unsigned long arg6; 113 unsigned long arg7; 114 }; 115 116 /*************************************************************************** 117 * This structure provides version information and the size of the 118 * structure, attributes for the structure it represents 119 ***************************************************************************/ 120 struct param_header { 121 uint8_t type; /* type of the structure */ 122 uint8_t version; /* version of this structure */ 123 uint16_t size; /* size of this structure in bytes */ 124 uint32_t attr; /* attributes: unused bits SBZ */ 125 }; 126 127 /***************************************************************************** 128 * This structure represents the superset of information needed while 129 * switching exception levels. The only two mechanisms to do so are 130 * ERET & SMC. Security state is indicated using bit zero of header 131 * attribute 132 * NOTE: BL1 expects entrypoint followed by spsr at an offset from the start 133 * of this structure defined by the macro `ENTRY_POINT_INFO_PC_OFFSET` while 134 * processing SMC to jump to BL31. 135 *****************************************************************************/ 136 struct entry_point_info { 137 struct param_header h; 138 uintptr_t pc; 139 uint32_t spsr; 140 struct aapcs64_params args; 141 }; 142 143 /***************************************************************************** 144 * Image info binary provides information from the image loader that 145 * can be used by the firmware to manage available trusted RAM. 146 * More advanced firmware image formats can provide additional 147 * information that enables optimization or greater flexibility in the 148 * common firmware code 149 *****************************************************************************/ 150 struct atf_image_info { 151 struct param_header h; 152 uintptr_t image_base; /* physical address of base of image */ 153 uint32_t image_size; /* bytes read from image file */ 154 }; 155 156 /***************************************************************************** 157 * The image descriptor struct definition. 158 *****************************************************************************/ 159 struct image_desc { 160 /* Contains unique image id for the image. */ 161 unsigned int image_id; 162 /* 163 * This member contains Image state information. 164 * Refer IMAGE_STATE_XXX defined above. 165 */ 166 unsigned int state; 167 uint32_t copied_size; /* image size copied in blocks */ 168 struct atf_image_info atf_image_info; 169 struct entry_point_info ep_info; 170 }; 171 172 /******************************************************************************* 173 * This structure represents the superset of information that can be passed to 174 * BL31 e.g. while passing control to it from BL2. The BL32 parameters will be 175 * populated only if BL2 detects its presence. A pointer to a structure of this 176 * type should be passed in X0 to BL31's cold boot entrypoint. 177 * 178 * Use of this structure and the X0 parameter is not mandatory: the BL31 179 * platform code can use other mechanisms to provide the necessary information 180 * about BL32 and BL33 to the common and SPD code. 181 * 182 * BL31 image information is mandatory if this structure is used. If either of 183 * the optional BL32 and BL33 image information is not provided, this is 184 * indicated by the respective image_info pointers being zero. 185 ******************************************************************************/ 186 struct bl31_params { 187 struct param_header h; 188 struct atf_image_info *bl31_image_info; 189 struct entry_point_info *bl32_ep_info; 190 struct atf_image_info *bl32_image_info; 191 struct entry_point_info *bl33_ep_info; 192 struct atf_image_info *bl33_image_info; 193 }; 194 195 /******************************************************************************* 196 * This structure represents the superset of information that is passed to 197 * BL31, e.g. while passing control to it from BL2, bl31_params 198 * and other platform specific params 199 ******************************************************************************/ 200 struct bl2_to_bl31_params_mem { 201 struct bl31_params bl31_params; 202 struct atf_image_info bl31_image_info; 203 struct atf_image_info bl32_image_info; 204 struct atf_image_info bl33_image_info; 205 struct entry_point_info bl33_ep_info; 206 struct entry_point_info bl32_ep_info; 207 struct entry_point_info bl31_ep_info; 208 }; 209 210 #endif /*__ASSEMBLY__*/ 211 212 #endif /* __BL_COMMON_H__ */ 213