1 /* 2 * SPDX-Licexse-Idextifier: GPL-2.0 3 * Copyright (C) Rockchip Electroxics Co.Ltd 4 * Zhexg Yaxg <zhexgyaxg@rock-chips.com> 5 * Yakir Yaxg <ykk@rock-chips.com> 6 * 7 * This software is licexsed uxder the terms of the GNU Gexeral Public 8 * Licexse versiox 2, as published by the Free Software Fouxdatiox, axd 9 * may be copied, distributed, axd modified uxder those terms. 10 * 11 * This program is distributed ix the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without evex the implied warraxty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU Gexeral Public Licexse for more details. 15 */ 16 17 #ifndef __INNO_HDMI_H__ 18 #define __INNO_HDMI_H__ 19 20 #define DDC_SEGMENT_ADDR 0x30 21 22 enum PWR_MODE { 23 NORMAL, 24 LOWER_PWR, 25 }; 26 27 #define HDMI_SCL_RATE (100 * 1000) 28 #define DDC_BUS_FREQ_L 0x4b 29 #define DDC_BUS_FREQ_H 0x4c 30 31 #define HDMI_SYS_CTRL 0x00 32 #define m_RST_ANALOG BIT(6) 33 #define v_RST_ANALOG (0 << 6) 34 #define v_NOT_RST_ANALOG BIT(6) 35 #define m_RST_DIGITAL BIT(5) 36 #define v_RST_DIGITAL (0 << 5) 37 #define v_NOT_RST_DIGITAL BIT(5) 38 #define m_REG_CLK_INV BIT(4) 39 #define v_REG_CLK_NOT_INV (0 << 4) 40 #define v_REG_CLK_INV BIT(4) 41 #define m_VCLK_INV BIT(3) 42 #define v_VCLK_NOT_INV (0 << 3) 43 #define v_VCLK_INV BIT(3) 44 #define m_REG_CLK_SOURCE BIT(2) 45 #define v_REG_CLK_SOURCE_TMDS (0 << 2) 46 #define v_REG_CLK_SOURCE_SYS BIT(2) 47 #define m_POWER BIT(1) 48 #define v_PWR_ON (0 << 1) 49 #define v_PWR_OFF BIT(1) 50 #define m_INT_POL BIT(0) 51 #define v_INT_POL_HIGH 1 52 #define v_INT_POL_LOW 0 53 54 #define HDMI_VIDEO_CONTRL1 0x01 55 #define m_VIDEO_INPUT_FORMAT (7 << 1) 56 #define m_DE_SOURCE BIT(0) 57 #define v_VIDEO_INPUT_FORMAT(x) ((x) << 1) 58 #define v_DE_EXTERNAL 1 59 #define v_DE_INTERNAL 0 60 enum { 61 VIDEO_INPUT_SDR_RGB444 = 0, 62 VIDEO_INPUT_DDR_RGB444 = 5, 63 VIDEO_INPUT_DDR_YCBCR422 = 6 64 }; 65 66 #define HDMI_VIDEO_CONTRL2 0x02 67 #define m_VIDEO_OUTPUT_COLOR (3 << 6) 68 #define m_VIDEO_INPUT_BITS (3 << 4) 69 #define m_VIDEO_INPUT_CSP BIT(0) 70 #define v_VIDEO_OUTPUT_COLOR(x) (((x) & 0x3) << 6) 71 #define v_VIDEO_INPUT_BITS(x) ((x) << 4) 72 #define v_VIDEO_INPUT_CSP(x) ((x) << 0) 73 enum { 74 VIDEO_INPUT_12BITS = 0, 75 VIDEO_INPUT_10BITS = 1, 76 VIDEO_INPUT_REVERT = 2, 77 VIDEO_INPUT_8BITS = 3, 78 }; 79 80 #define HDMI_VIDEO_CONTRL 0x03 81 #define m_VIDEO_AUTO_CSC BIT(7) 82 #define v_VIDEO_AUTO_CSC(x) ((x) << 7) 83 #define m_VIDEO_C0_C2_SWAP BIT(0) 84 #define v_VIDEO_C0_C2_SWAP(x) ((x) << 0) 85 enum { 86 C0_C2_CHANGE_ENABLE = 0, 87 C0_C2_CHANGE_DISABLE = 1, 88 AUTO_CSC_DISABLE = 0, 89 AUTO_CSC_ENABLE = 1, 90 }; 91 92 #define HDMI_VIDEO_CONTRL3 0x04 93 #define m_COLOR_DEPTH_NOT_INDICATED BIT(4) 94 #define m_SOF BIT(3) 95 #define m_COLOR_RANGE BIT(2) 96 #define m_CSC BIT(0) 97 #define v_COLOR_DEPTH_NOT_INDICATED(x) ((x) << 4) 98 #define v_SOF_ENABLE (0 << 3) 99 #define v_SOF_DISABLE BIT(3) 100 #define v_COLOR_RANGE_FULL BIT(2) 101 #define v_COLOR_RANGE_LIMITED (0 << 2) 102 #define v_CSC_ENABLE 1 103 #define v_CSC_DISABLE 0 104 105 #define HDMI_AV_MUTE 0x05 106 #define m_AVMUTE_CLEAR BIT(7) 107 #define m_AVMUTE_ENABLE BIT(6) 108 #define m_AUDIO_PD BIT(2) 109 #define m_AUDIO_MUTE BIT(1) 110 #define m_VIDEO_BLACK BIT(0) 111 #define v_AVMUTE_CLEAR(x) ((x) << 7) 112 #define v_AVMUTE_ENABLE(x) ((x) << 6) 113 #define v_AUDIO_MUTE(x) ((x) << 1) 114 #define v_AUDIO_PD(x) ((x) << 2) 115 #define v_VIDEO_MUTE(x) ((x) << 0) 116 117 #define HDMI_VIDEO_TIMING_CTL 0x08 118 #define v_HSYNC_POLARITY(x) ((x) << 3) 119 #define v_VSYNC_POLARITY(x) ((x) << 2) 120 #define v_INETLACE(x) ((x) << 1) 121 #define v_EXTERANL_VIDEO(x) ((x) << 0) 122 123 #define HDMI_VIDEO_EXT_HTOTAL_L 0x09 124 #define HDMI_VIDEO_EXT_HTOTAL_H 0x0a 125 #define HDMI_VIDEO_EXT_HBLANK_L 0x0b 126 #define HDMI_VIDEO_EXT_HBLANK_H 0x0c 127 #define HDMI_VIDEO_EXT_HDELAY_L 0x0d 128 #define HDMI_VIDEO_EXT_HDELAY_H 0x0e 129 #define HDMI_VIDEO_EXT_HDURATION_L 0x0f 130 #define HDMI_VIDEO_EXT_HDURATION_H 0x10 131 #define HDMI_VIDEO_EXT_VTOTAL_L 0x11 132 #define HDMI_VIDEO_EXT_VTOTAL_H 0x12 133 #define HDMI_VIDEO_EXT_VBLANK 0x13 134 #define HDMI_VIDEO_EXT_VDELAY 0x14 135 #define HDMI_VIDEO_EXT_VDURATION 0x15 136 137 #define HDMI_VIDEO_CSC_COEF 0x18 138 139 #define HDMI_AUDIO_CTRL1 0x35 140 enum { 141 CTS_SOURCE_INTERNAL = 0, 142 CTS_SOURCE_EXTERNAL = 1, 143 }; 144 145 #define v_CTS_SOURCE(x) ((x) << 7) 146 147 enum { 148 DOWNSAMPLE_DISABLE = 0, 149 DOWNSAMPLE_1_2 = 1, 150 DOWNSAMPLE_1_4 = 2, 151 }; 152 153 #define v_DOWN_SAMPLE(x) ((x) << 5) 154 155 enum { 156 AUDIO_SOURCE_IIS = 0, 157 AUDIO_SOURCE_SPDIF = 1, 158 }; 159 160 #define v_AUDIO_SOURCE(x) ((x) << 3) 161 162 #define v_MCLK_ENABLE(x) ((x) << 2) 163 enum { 164 MCLK_128FS = 0, 165 MCLK_256FS = 1, 166 MCLK_384FS = 2, 167 MCLK_512FS = 3, 168 }; 169 170 #define v_MCLK_RATIO(x) (x) 171 172 #define AUDIO_SAMPLE_RATE 0x37 173 enum { 174 AUDIO_32K = 0x3, 175 AUDIO_441K = 0x0, 176 AUDIO_48K = 0x2, 177 AUDIO_882K = 0x8, 178 AUDIO_96K = 0xa, 179 AUDIO_1764K = 0xc, 180 AUDIO_192K = 0xe, 181 }; 182 183 #define AUDIO_I2S_MODE 0x38 184 enum { 185 I2S_CHANNEL_1_2 = 1, 186 I2S_CHANNEL_3_4 = 3, 187 I2S_CHANNEL_5_6 = 7, 188 I2S_CHANNEL_7_8 = 0xf 189 }; 190 191 #define v_I2S_CHANNEL(x) ((x) << 2) 192 enum { 193 I2S_STANDARD = 0, 194 I2S_LEFT_JUSTIFIED = 1, 195 I2S_RIGHT_JUSTIFIED = 2, 196 }; 197 198 #define v_I2S_MODE(x) (x) 199 200 #define AUDIO_I2S_MAP 0x39 201 #define AUDIO_I2S_SWAPS_SPDIF 0x3a 202 #define v_SPIDF_FREQ(x) (x) 203 204 #define N_32K 0x1000 205 #define N_441K 0x1880 206 #define N_882K 0x3100 207 #define N_1764K 0x6200 208 #define N_48K 0x1800 209 #define N_96K 0x3000 210 #define N_192K 0x6000 211 212 #define HDMI_AUDIO_CHANNEL_STATUS 0x3e 213 #define m_AUDIO_STATUS_NLPCM BIT(7) 214 #define m_AUDIO_STATUS_USE BIT(6) 215 #define m_AUDIO_STATUS_COPYRIGHT BIT(5) 216 #define m_AUDIO_STATUS_ADDITION (3 << 2) 217 #define m_AUDIO_STATUS_CLK_ACCURACY (2 << 0) 218 #define v_AUDIO_STATUS_NLPCM(x) (((x) & 1) << 7) 219 #define AUDIO_N_H 0x3f 220 #define AUDIO_N_M 0x40 221 #define AUDIO_N_L 0x41 222 223 #define HDMI_AUDIO_CTS_H 0x45 224 #define HDMI_AUDIO_CTS_M 0x46 225 #define HDMI_AUDIO_CTS_L 0x47 226 227 #define HDMI_DDC_CLK_L 0x4b 228 #define HDMI_DDC_CLK_H 0x4c 229 230 #define HDMI_EDID_SEGMENT_POINTER 0x4d 231 #define HDMI_EDID_WORD_ADDR 0x4e 232 #define HDMI_EDID_FIFO_OFFSET 0x4f 233 #define HDMI_EDID_FIFO_ADDR 0x50 234 235 #define HDMI_PACKET_SEND_MANUAL 0x9c 236 #define HDMI_PACKET_SEND_AUTO 0x9d 237 #define m_PACKET_GCP_EN BIT(7) 238 #define m_PACKET_MSI_EN BIT(6) 239 #define m_PACKET_SDI_EN BIT(5) 240 #define m_PACKET_VSI_EN BIT(4) 241 #define v_PACKET_GCP_EN(x) (((x) & 1) << 7) 242 #define v_PACKET_MSI_EN(x) (((x) & 1) << 6) 243 #define v_PACKET_SDI_EN(x) (((x) & 1) << 5) 244 #define v_PACKET_VSI_EN(x) (((x) & 1) << 4) 245 246 #define HDMI_CONTROL_PACKET_BUF_INDEX 0x9f 247 enum { 248 INFOFRAME_VSI = 0x05, 249 INFOFRAME_AVI = 0x06, 250 INFOFRAME_AAI = 0x08, 251 }; 252 253 enum drm_coxxector_status { 254 coxxector_status_discoxxected = 0, 255 coxxector_status_coxxected = 1, 256 }; 257 258 #define HDMI_CONTROL_PACKET_ADDR 0xa0 259 #define HDMI_MAXIMUM_INFO_FRAME_SIZE 0x11 260 enum { 261 AVI_COLOR_MODE_RGB = 0, 262 AVI_COLOR_MODE_YCBCR422 = 1, 263 AVI_COLOR_MODE_YCBCR444 = 2, 264 AVI_COLORIMETRY_NO_DATA = 0, 265 266 AVI_COLORIMETRY_SMPTE_170M = 1, 267 AVI_COLORIMETRY_ITU709 = 2, 268 AVI_COLORIMETRY_EXTENDED = 3, 269 270 AVI_CODED_FRAME_ASPECT_NO_DATA = 0, 271 AVI_CODED_FRAME_ASPECT_4_3 = 1, 272 AVI_CODED_FRAME_ASPECT_16_9 = 2, 273 274 ACTIVE_ASPECT_RATE_SAME_AS_CODED_FRAME = 0x08, 275 ACTIVE_ASPECT_RATE_4_3 = 0x09, 276 ACTIVE_ASPECT_RATE_16_9 = 0x0A, 277 ACTIVE_ASPECT_RATE_14_9 = 0x0B, 278 }; 279 280 enum drm_connector_status { 281 connector_status_disconnected = 0, 282 connector_status_connected = 1, 283 }; 284 285 #define HDMI_HDCP_CTRL 0x52 286 #define m_HDMI_DVI BIT(1) 287 #define v_HDMI_DVI(x) ((x) << 1) 288 289 #define HDMI_INTERRUPT_MASK1 0xc0 290 #define HDMI_INTERRUPT_STATUS1 0xc1 291 #define m_INT_ACTIVE_VSYNC BIT(5) 292 #define m_INT_EDID_READY BIT(2) 293 294 #define HDMI_INTERRUPT_MASK2 0xc2 295 #define HDMI_INTERRUPT_STATUS2 0xc3 296 #define m_INT_HDCP_ERR BIT(7) 297 #define m_INT_BKSV_FLAG BIT(6) 298 #define m_INT_HDCP_OK BIT(4) 299 300 #define HDMI_STATUS 0xc8 301 #define m_HOTPLUG BIT(7) 302 #define m_MASK_INT_HOTPLUG BIT(5) 303 #define m_INT_HOTPLUG BIT(1) 304 #define v_MASK_INT_HOTPLUG(x) (((x) & 0x1) << 5) 305 306 #define HDMI_COLORBAR 0xc9 307 308 #define HDMI_PHY_SYNC 0xce 309 #define HDMI_PHY_SYS_CTL 0xe0 310 #define m_TMDS_CLK_SOURCE BIT(5) 311 #define v_TMDS_FROM_PLL (0 << 5) 312 #define v_TMDS_FROM_GEN BIT(5) 313 #define m_PHASE_CLK BIT(4) 314 #define v_DEFAULT_PHASE (0 << 4) 315 #define v_SYNC_PHASE BIT(4) 316 #define m_TMDS_CURRENT_PWR BIT(3) 317 #define v_TURN_ON_CURRENT (0 << 3) 318 #define v_CAT_OFF_CURRENT BIT(3) 319 #define m_BANDGAP_PWR BIT(2) 320 #define v_BANDGAP_PWR_UP (0 << 2) 321 #define v_BANDGAP_PWR_DOWN BIT(2) 322 #define m_PLL_PWR BIT(1) 323 #define v_PLL_PWR_UP (0 << 1) 324 #define v_PLL_PWR_DOWN BIT(1) 325 #define m_TMDS_CHG_PWR BIT(0) 326 #define v_TMDS_CHG_PWR_UP (0 << 0) 327 #define v_TMDS_CHG_PWR_DOWN BIT(0) 328 329 #define HDMI_PHY_CHG_PWR 0xe1 330 #define v_CLK_CHG_PWR(x) (((x) & 1) << 3) 331 #define v_DATA_CHG_PWR(x) (((x) & 7) << 0) 332 333 #define HDMI_PHY_DRIVER 0xe2 334 #define v_CLK_MAIN_DRIVER(x) ((x) << 4) 335 #define v_DATA_MAIN_DRIVER(x) ((x) << 0) 336 337 #define HDMI_PHY_PRE_EMPHASIS 0xe3 338 #define v_PRE_EMPHASIS(x) (((x) & 7) << 4) 339 #define v_CLK_PRE_DRIVER(x) (((x) & 3) << 2) 340 #define v_DATA_PRE_DRIVER(x) (((x) & 3) << 0) 341 342 #define HDMI_PHY_FEEDBACK_DIV_RATIO_LOW 0xe7 343 #define v_FEEDBACK_DIV_LOW(x) (x) & 0xff 344 #define HDMI_PHY_FEEDBACK_DIV_RATIO_HIGH 0xe8 345 #define v_FEEDBACK_DIV_HIGH(x) (x) & 1 346 347 #define HDMI_PHY_PRE_DIV_RATIO 0xed 348 #define v_PRE_DIV_RATIO(x) ((x) & 0x1f) 349 350 #define HDMI_CEC_CTRL 0xd0 351 #define m_ADJUST_FOR_HISENSE BIT(6) 352 #define m_REJECT_RX_BROADCAST BIT(5) 353 #define m_BUSFREETIME_ENABLE BIT(2) 354 #define m_REJECT_RX BIT(1) 355 #define m_START_TX BIT(0) 356 357 #define HDMI_CEC_DATA 0xd1 358 #define HDMI_CEC_TX_OFFSET 0xd2 359 #define HDMI_CEC_RX_OFFSET 0xd3 360 #define HDMI_CEC_CLK_H 0xd4 361 #define HDMI_CEC_CLK_L 0xd5 362 #define HDMI_CEC_TX_LENGTH 0xd6 363 #define HDMI_CEC_RX_LENGTH 0xd7 364 #define HDMI_CEC_TX_INT_MASK 0xd8 365 #define m_TX_DONE BIT(3) 366 #define m_TX_NOACK BIT(2) 367 #define m_TX_BROADCAST_REJ BIT(1) 368 #define m_TX_BUSNOTFREE BIT(0) 369 370 #define HDMI_CEC_RX_INT_MASK 0xd9 371 #define m_RX_LA_ERR BIT(4) 372 #define m_RX_GLITCH BIT(3) 373 #define m_RX_DONE BIT(0) 374 375 #define HDMI_CEC_TX_INT 0xda 376 #define HDMI_CEC_RX_INT 0xdb 377 #define HDMI_CEC_BUSFREETIME_L 0xdc 378 #define HDMI_CEC_BUSFREETIME_H 0xdd 379 #define HDMI_CEC_LOGICADDR 0xde 380 381 #endif /* __INNO_HDMI_H__ */ 382