1 /*
2 * Copyright 2016 Rockchip Electronics Co., Ltd
3 *
4 * SPDX-License-Identifier: GPL-2.0+
5 */
6
7 #include <common.h>
8 #include <asm/arch/clock.h>
9 #include <asm/io.h>
10 #include <dm.h>
11 #include <fdtdec.h>
12 #include <fdt_support.h>
13 #include <syscon.h>
14 #include <linux/libfdt.h>
15
16 #include "../gadget/dwc2_udc_otg_priv.h"
17
18 DECLARE_GLOBAL_DATA_PTR;
19
20 #define BIT_WRITEABLE_SHIFT 16
21
22 struct usb2phy_reg {
23 unsigned int offset;
24 unsigned int bitend;
25 unsigned int bitstart;
26 unsigned int disable;
27 unsigned int enable;
28 };
29
30 /**
31 * struct rockchip_usb2_phy_cfg: usb-phy port configuration
32 * @port_reset: usb otg per-port reset register
33 * @soft_con: software control usb otg register
34 * @suspend: phy suspend register
35 */
36 struct rockchip_usb2_phy_cfg {
37 struct usb2phy_reg port_reset;
38 struct usb2phy_reg siddq;
39 struct usb2phy_reg soft_con;
40 struct usb2phy_reg suspend;
41 };
42
43 struct rockchip_usb2_phy_dt_id {
44 char compatible[128];
45 const void *data;
46 };
47
48 static const struct rockchip_usb2_phy_cfg rk3288_pdata = {
49 .port_reset = {0x00, 12, 12, 0, 1},
50 .siddq = {0x00, 13, 13, 0, 1},
51 .soft_con = {0x08, 2, 2, 0, 1},
52 .suspend = {0x0c, 5, 0, 0x01, 0x2A},
53 };
54
55 static struct rockchip_usb2_phy_dt_id rockchip_usb2_phy_dt_ids[] = {
56 { .compatible = "rockchip,rk3288-usb-phy", .data = &rk3288_pdata },
57 {}
58 };
59
property_enable(struct dwc2_plat_otg_data * pdata,const struct usb2phy_reg * reg,bool en)60 static void property_enable(struct dwc2_plat_otg_data *pdata,
61 const struct usb2phy_reg *reg, bool en)
62 {
63 unsigned int val, mask, tmp;
64
65 tmp = en ? reg->enable : reg->disable;
66 mask = GENMASK(reg->bitend, reg->bitstart);
67 val = (tmp << reg->bitstart) | (mask << BIT_WRITEABLE_SHIFT);
68
69 writel(val, pdata->regs_phy + reg->offset);
70 }
71
rockchip_u2phy_vbus_detect(void)72 int rockchip_u2phy_vbus_detect(void)
73 {
74 u32 val = 0;
75
76 #ifdef CONFIG_ROCKCHIP_RK3288
77 u32 grf_base = (u32)syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
78
79 val = readl(grf_base + 0x288);
80 val = (val & BIT(14)) >> 14;
81 #endif
82
83 return val;
84 }
85
otg_phy_parse(struct dwc2_udc * dev)86 static int otg_phy_parse(struct dwc2_udc *dev)
87 {
88 int node, phy_node;
89 u32 grf_base, grf_offset;
90 const void *blob = gd->fdt_blob;
91 const fdt32_t *reg;
92 fdt_addr_t addr;
93 struct dwc2_plat_otg_data *pdata = dev->pdata;
94
95 /* Find the usb_otg node */
96 node = fdt_node_offset_by_compatible(blob, -1, "snps,dwc2");
97
98 #if defined(CONFIG_ROCKCHIP_RK3288)
99 retry:
100 #endif
101 if (node > 0) {
102 reg = fdt_getprop(blob, node, "reg", NULL);
103 if (!reg)
104 return -EINVAL;
105
106 addr = fdt_translate_address(blob, node, reg);
107 if (addr == OF_BAD_ADDR) {
108 pr_err("Not found usb_otg address\n");
109 return -EINVAL;
110 }
111
112 #if defined(CONFIG_ROCKCHIP_RK3288)
113 if (addr != 0xff580000) {
114 node = fdt_node_offset_by_compatible(blob, node,
115 "snps,dwc2");
116 goto retry;
117 }
118 #endif
119 } else {
120 /*
121 * With kernel dtb support, rk3288 dwc2 otg node
122 * use the rockchip legacy dwc2 driver "dwc_otg_310"
123 * with the compatible "rockchip,rk3288_usb20_otg".
124 */
125 #if defined(CONFIG_ROCKCHIP_RK3288)
126 node = fdt_node_offset_by_compatible(blob, -1,
127 "rockchip,rk3288_usb20_otg");
128 #endif
129 if (node < 0) {
130 pr_err("Not found usb_otg device\n");
131 return -ENODEV;
132 }
133 }
134
135 /* Find the usb phy node */
136 node = fdtdec_lookup_phandle(blob, node, "phys");
137 if (node <= 0) {
138 pr_err("Not found usbphy device\n");
139 return -ENODEV;
140 }
141
142 /* Find the usb otg-phy node */
143 phy_node = fdt_parent_offset(blob, node);
144 if (phy_node <= 0) {
145 pr_err("Not found sub usbphy device\n");
146 return -ENODEV;
147 }
148
149 grf_base = (u32)syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
150 grf_offset = fdtdec_get_addr(blob, node, "reg");
151
152 /* Pad dwc2_plat_otg_data related to phy */
153 pdata->phy_of_node = phy_node;
154 pdata->regs_phy = grf_base + grf_offset;
155
156 return 0;
157 }
158
otg_phy_init(struct dwc2_udc * dev)159 void otg_phy_init(struct dwc2_udc *dev)
160 {
161 struct dwc2_plat_otg_data *pdata = dev->pdata;
162 struct rockchip_usb2_phy_cfg *phy_cfg = NULL;
163 struct rockchip_usb2_phy_dt_id *of_id;
164 int i;
165
166 if (!pdata->regs_phy && otg_phy_parse(dev)) {
167 pr_err("otg-phy parse error\n");
168 return;
169 }
170
171 for (i = 0; i < ARRAY_SIZE(rockchip_usb2_phy_dt_ids); i++) {
172 of_id = &rockchip_usb2_phy_dt_ids[i];
173 if (fdt_node_check_compatible(gd->fdt_blob, pdata->phy_of_node,
174 of_id->compatible) == 0) {
175 phy_cfg = (struct rockchip_usb2_phy_cfg *)of_id->data;
176 break;
177 }
178 }
179 if (!phy_cfg) {
180 debug("Can't find device platform data\n");
181
182 hang();
183 return;
184 }
185 pdata->priv = phy_cfg;
186
187 /* power up usb phy analog blocks by set siddq 0 */
188 property_enable(pdata, &phy_cfg->siddq, false);
189
190 /* disable software control */
191 property_enable(pdata, &phy_cfg->soft_con, false);
192
193 /* reset otg port */
194 property_enable(pdata, &phy_cfg->port_reset, true);
195 mdelay(1);
196 property_enable(pdata, &phy_cfg->port_reset, false);
197 udelay(1);
198 }
199
otg_phy_off(struct dwc2_udc * dev)200 void otg_phy_off(struct dwc2_udc *dev)
201 {
202 struct dwc2_plat_otg_data *pdata = dev->pdata;
203 struct rockchip_usb2_phy_cfg *phy_cfg = pdata->priv;
204
205 if (!pdata->regs_phy && otg_phy_parse(dev)) {
206 pr_err("otg-phy parse error\n");
207 return;
208 }
209
210 /* enable software control */
211 property_enable(pdata, &phy_cfg->soft_con, true);
212 /* enter suspend */
213 property_enable(pdata, &phy_cfg->suspend, true);
214 }
215