1 /******************************************************************
2 * Copyright 2008 Mentor Graphics Corporation
3 * Copyright (C) 2008 by Texas Instruments
4 *
5 * This file is part of the Inventra Controller Driver for Linux.
6 *
7 * SPDX-License-Identifier: GPL-2.0
8 ******************************************************************/
9
10 #ifndef __MUSB_HDRC_DEFS_H__
11 #define __MUSB_HDRC_DEFS_H__
12
13 #include <usb_defs.h>
14 #include <asm/io.h>
15
16 #define MUSB_EP0_FIFOSIZE 64 /* This is non-configurable */
17
18 /* EP0 */
19 struct musb_ep0_regs {
20 u16 reserved4;
21 u16 csr0;
22 u16 reserved5;
23 u16 reserved6;
24 u16 count0;
25 u8 host_type0;
26 u8 host_naklimit0;
27 u8 reserved7;
28 u8 reserved8;
29 u8 reserved9;
30 u8 configdata;
31 };
32
33 /* EP 1-15 */
34 struct musb_epN_regs {
35 u16 txmaxp;
36 u16 txcsr;
37 u16 rxmaxp;
38 u16 rxcsr;
39 u16 rxcount;
40 u8 txtype;
41 u8 txinterval;
42 u8 rxtype;
43 u8 rxinterval;
44 u8 reserved0;
45 u8 fifosize;
46 };
47
48 /* Mentor USB core register overlay structure */
49 #ifndef musb_regs
50 struct musb_regs {
51 /* common registers */
52 u8 faddr;
53 u8 power;
54 u16 intrtx;
55 u16 intrrx;
56 u16 intrtxe;
57 u16 intrrxe;
58 u8 intrusb;
59 u8 intrusbe;
60 u16 frame;
61 u8 index;
62 u8 testmode;
63 /* indexed registers */
64 u16 txmaxp;
65 u16 txcsr;
66 u16 rxmaxp;
67 u16 rxcsr;
68 u16 rxcount;
69 u8 txtype;
70 u8 txinterval;
71 u8 rxtype;
72 u8 rxinterval;
73 u8 reserved0;
74 u8 fifosize;
75 /* fifo */
76 u32 fifox[16];
77 /* OTG, dynamic FIFO, version & vendor registers */
78 u8 devctl;
79 u8 reserved1;
80 u8 txfifosz;
81 u8 rxfifosz;
82 u16 txfifoadd;
83 u16 rxfifoadd;
84 u32 vcontrol;
85 u16 hwvers;
86 u16 reserved2a[1];
87 u8 ulpi_busctl;
88 u8 reserved2b[1];
89 u16 reserved2[3];
90 u8 epinfo;
91 u8 raminfo;
92 u8 linkinfo;
93 u8 vplen;
94 u8 hseof1;
95 u8 fseof1;
96 u8 lseof1;
97 u8 reserved3;
98 /* target address registers */
99 struct musb_tar_regs {
100 u8 txfuncaddr;
101 u8 reserved0;
102 u8 txhubaddr;
103 u8 txhubport;
104 u8 rxfuncaddr;
105 u8 reserved1;
106 u8 rxhubaddr;
107 u8 rxhubport;
108 } tar[16];
109 /*
110 * endpoint registers
111 * ep0 elements are valid when array index is 0
112 * otherwise epN is valid
113 */
114 union musb_ep_regs {
115 struct musb_ep0_regs ep0;
116 struct musb_epN_regs epN;
117 } ep[16];
118
119 } __attribute__((packed));
120 #endif
121
122 /*
123 * MUSB Register bits
124 */
125
126 /* POWER */
127 #define MUSB_POWER_ISOUPDATE 0x80
128 #define MUSB_POWER_SOFTCONN 0x40
129 #define MUSB_POWER_HSENAB 0x20
130 #define MUSB_POWER_HSMODE 0x10
131 #define MUSB_POWER_RESET 0x08
132 #define MUSB_POWER_RESUME 0x04
133 #define MUSB_POWER_SUSPENDM 0x02
134 #define MUSB_POWER_ENSUSPEND 0x01
135 #define MUSB_POWER_HSMODE_SHIFT 4
136
137 /* INTRUSB */
138 #define MUSB_INTR_SUSPEND 0x01
139 #define MUSB_INTR_RESUME 0x02
140 #define MUSB_INTR_RESET 0x04
141 #define MUSB_INTR_BABBLE 0x04
142 #define MUSB_INTR_SOF 0x08
143 #define MUSB_INTR_CONNECT 0x10
144 #define MUSB_INTR_DISCONNECT 0x20
145 #define MUSB_INTR_SESSREQ 0x40
146 #define MUSB_INTR_VBUSERROR 0x80 /* For SESSION end */
147
148 /* DEVCTL */
149 #define MUSB_DEVCTL_BDEVICE 0x80
150 #define MUSB_DEVCTL_FSDEV 0x40
151 #define MUSB_DEVCTL_LSDEV 0x20
152 #define MUSB_DEVCTL_VBUS 0x18
153 #define MUSB_DEVCTL_VBUS_SHIFT 3
154 #define MUSB_DEVCTL_HM 0x04
155 #define MUSB_DEVCTL_HR 0x02
156 #define MUSB_DEVCTL_SESSION 0x01
157
158 /* ULPI VBUSCONTROL */
159 #define ULPI_USE_EXTVBUS 0x01
160 #define ULPI_USE_EXTVBUSIND 0x02
161
162 /* TESTMODE */
163 #define MUSB_TEST_FORCE_HOST 0x80
164 #define MUSB_TEST_FIFO_ACCESS 0x40
165 #define MUSB_TEST_FORCE_FS 0x20
166 #define MUSB_TEST_FORCE_HS 0x10
167 #define MUSB_TEST_PACKET 0x08
168 #define MUSB_TEST_K 0x04
169 #define MUSB_TEST_J 0x02
170 #define MUSB_TEST_SE0_NAK 0x01
171
172 /* Allocate for double-packet buffering (effectively doubles assigned _SIZE) */
173 #define MUSB_FIFOSZ_DPB 0x10
174 /* Allocation size (8, 16, 32, ... 4096) */
175 #define MUSB_FIFOSZ_SIZE 0x0f
176
177 /* CSR0 */
178 #define MUSB_CSR0_FLUSHFIFO 0x0100
179 #define MUSB_CSR0_TXPKTRDY 0x0002
180 #define MUSB_CSR0_RXPKTRDY 0x0001
181
182 /* CSR0 in Peripheral mode */
183 #define MUSB_CSR0_P_SVDSETUPEND 0x0080
184 #define MUSB_CSR0_P_SVDRXPKTRDY 0x0040
185 #define MUSB_CSR0_P_SENDSTALL 0x0020
186 #define MUSB_CSR0_P_SETUPEND 0x0010
187 #define MUSB_CSR0_P_DATAEND 0x0008
188 #define MUSB_CSR0_P_SENTSTALL 0x0004
189
190 /* CSR0 in Host mode */
191 #define MUSB_CSR0_H_DIS_PING 0x0800
192 #define MUSB_CSR0_H_WR_DATATOGGLE 0x0400 /* Set to allow setting: */
193 #define MUSB_CSR0_H_DATATOGGLE 0x0200 /* Data toggle control */
194 #define MUSB_CSR0_H_NAKTIMEOUT 0x0080
195 #define MUSB_CSR0_H_STATUSPKT 0x0040
196 #define MUSB_CSR0_H_REQPKT 0x0020
197 #define MUSB_CSR0_H_ERROR 0x0010
198 #define MUSB_CSR0_H_SETUPPKT 0x0008
199 #define MUSB_CSR0_H_RXSTALL 0x0004
200
201 /* CSR0 bits to avoid zeroing (write zero clears, write 1 ignored) */
202 #define MUSB_CSR0_P_WZC_BITS \
203 (MUSB_CSR0_P_SENTSTALL)
204 #define MUSB_CSR0_H_WZC_BITS \
205 (MUSB_CSR0_H_NAKTIMEOUT | MUSB_CSR0_H_RXSTALL \
206 | MUSB_CSR0_RXPKTRDY)
207
208 /* TxType/RxType */
209 #define MUSB_TYPE_SPEED 0xc0
210 #define MUSB_TYPE_SPEED_SHIFT 6
211 #define MUSB_TYPE_SPEED_HIGH 1
212 #define MUSB_TYPE_SPEED_FULL 2
213 #define MUSB_TYPE_SPEED_LOW 3
214 #define MUSB_TYPE_PROTO 0x30 /* Implicitly zero for ep0 */
215 #define MUSB_TYPE_PROTO_SHIFT 4
216 #define MUSB_TYPE_REMOTE_END 0xf /* Implicitly zero for ep0 */
217 #define MUSB_TYPE_PROTO_BULK 2
218 #define MUSB_TYPE_PROTO_INTR 3
219
220 /* CONFIGDATA */
221 #define MUSB_CONFIGDATA_MPRXE 0x80 /* Auto bulk pkt combining */
222 #define MUSB_CONFIGDATA_MPTXE 0x40 /* Auto bulk pkt splitting */
223 #define MUSB_CONFIGDATA_BIGENDIAN 0x20
224 #define MUSB_CONFIGDATA_HBRXE 0x10 /* HB-ISO for RX */
225 #define MUSB_CONFIGDATA_HBTXE 0x08 /* HB-ISO for TX */
226 #define MUSB_CONFIGDATA_DYNFIFO 0x04 /* Dynamic FIFO sizing */
227 #define MUSB_CONFIGDATA_SOFTCONE 0x02 /* SoftConnect */
228 #define MUSB_CONFIGDATA_UTMIDW 0x01 /* Data width 0/1 => 8/16bits */
229
230 /* TXCSR in Peripheral and Host mode */
231 #define MUSB_TXCSR_AUTOSET 0x8000
232 #define MUSB_TXCSR_MODE 0x2000
233 #define MUSB_TXCSR_DMAENAB 0x1000
234 #define MUSB_TXCSR_FRCDATATOG 0x0800
235 #define MUSB_TXCSR_DMAMODE 0x0400
236 #define MUSB_TXCSR_CLRDATATOG 0x0040
237 #define MUSB_TXCSR_FLUSHFIFO 0x0008
238 #define MUSB_TXCSR_FIFONOTEMPTY 0x0002
239 #define MUSB_TXCSR_TXPKTRDY 0x0001
240
241 /* TXCSR in Peripheral mode */
242 #define MUSB_TXCSR_P_ISO 0x4000
243 #define MUSB_TXCSR_P_INCOMPTX 0x0080
244 #define MUSB_TXCSR_P_SENTSTALL 0x0020
245 #define MUSB_TXCSR_P_SENDSTALL 0x0010
246 #define MUSB_TXCSR_P_UNDERRUN 0x0004
247
248 /* TXCSR in Host mode */
249 #define MUSB_TXCSR_H_WR_DATATOGGLE 0x0200
250 #define MUSB_TXCSR_H_DATATOGGLE 0x0100
251 #define MUSB_TXCSR_H_NAKTIMEOUT 0x0080
252 #define MUSB_TXCSR_H_RXSTALL 0x0020
253 #define MUSB_TXCSR_H_ERROR 0x0004
254 #define MUSB_TXCSR_H_DATATOGGLE_SHIFT 8
255
256 /* TXCSR bits to avoid zeroing (write zero clears, write 1 ignored) */
257 #define MUSB_TXCSR_P_WZC_BITS \
258 (MUSB_TXCSR_P_INCOMPTX | MUSB_TXCSR_P_SENTSTALL \
259 | MUSB_TXCSR_P_UNDERRUN | MUSB_TXCSR_FIFONOTEMPTY)
260 #define MUSB_TXCSR_H_WZC_BITS \
261 (MUSB_TXCSR_H_NAKTIMEOUT | MUSB_TXCSR_H_RXSTALL \
262 | MUSB_TXCSR_H_ERROR | MUSB_TXCSR_FIFONOTEMPTY)
263
264 /* RXCSR in Peripheral and Host mode */
265 #define MUSB_RXCSR_AUTOCLEAR 0x8000
266 #define MUSB_RXCSR_DMAENAB 0x2000
267 #define MUSB_RXCSR_DISNYET 0x1000
268 #define MUSB_RXCSR_PID_ERR 0x1000
269 #define MUSB_RXCSR_DMAMODE 0x0800
270 #define MUSB_RXCSR_INCOMPRX 0x0100
271 #define MUSB_RXCSR_CLRDATATOG 0x0080
272 #define MUSB_RXCSR_FLUSHFIFO 0x0010
273 #define MUSB_RXCSR_DATAERROR 0x0008
274 #define MUSB_RXCSR_FIFOFULL 0x0002
275 #define MUSB_RXCSR_RXPKTRDY 0x0001
276
277 /* RXCSR in Peripheral mode */
278 #define MUSB_RXCSR_P_ISO 0x4000
279 #define MUSB_RXCSR_P_SENTSTALL 0x0040
280 #define MUSB_RXCSR_P_SENDSTALL 0x0020
281 #define MUSB_RXCSR_P_OVERRUN 0x0004
282
283 /* RXCSR in Host mode */
284 #define MUSB_RXCSR_H_AUTOREQ 0x4000
285 #define MUSB_RXCSR_H_WR_DATATOGGLE 0x0400
286 #define MUSB_RXCSR_H_DATATOGGLE 0x0200
287 #define MUSB_RXCSR_H_RXSTALL 0x0040
288 #define MUSB_RXCSR_H_REQPKT 0x0020
289 #define MUSB_RXCSR_H_ERROR 0x0004
290 #define MUSB_S_RXCSR_H_DATATOGGLE 9
291
292 /* RXCSR bits to avoid zeroing (write zero clears, write 1 ignored) */
293 #define MUSB_RXCSR_P_WZC_BITS \
294 (MUSB_RXCSR_P_SENTSTALL | MUSB_RXCSR_P_OVERRUN \
295 | MUSB_RXCSR_RXPKTRDY)
296 #define MUSB_RXCSR_H_WZC_BITS \
297 (MUSB_RXCSR_H_RXSTALL | MUSB_RXCSR_H_ERROR \
298 | MUSB_RXCSR_DATAERROR | MUSB_RXCSR_RXPKTRDY)
299
300 /* HUBADDR */
301 #define MUSB_HUBADDR_MULTI_TT 0x80
302
303 /* Endpoint configuration information. Note: The value of endpoint fifo size
304 * element should be either 8,16,32,64,128,256,512,1024,2048 or 4096. Other
305 * values are not supported
306 */
307 struct musb_epinfo {
308 u8 epnum; /* endpoint number */
309 u8 epdir; /* endpoint direction */
310 u16 epsize; /* endpoint FIFO size */
311 };
312
313 /*
314 * Platform specific MUSB configuration. Any platform using the musb
315 * functionality should create one instance of this structure in the
316 * platform specific file.
317 */
318 struct musb_config {
319 struct musb_regs *regs;
320 u32 timeout;
321 u8 musb_speed;
322 u8 extvbus;
323 };
324
325 /* externally defined data */
326 extern struct musb_config musb_cfg;
327 extern struct musb_regs *musbr;
328
329 /* exported functions */
330 extern void musb_start(void);
331 extern void musb_configure_ep(const struct musb_epinfo *epinfo, u8 cnt);
332 extern void write_fifo(u8 ep, u32 length, void *fifo_data);
333 extern void read_fifo(u8 ep, u32 length, void *fifo_data);
334
musb_read_ulpi_buscontrol(struct musb_regs * musbr)335 static inline u8 musb_read_ulpi_buscontrol(struct musb_regs *musbr)
336 {
337 return readb(&musbr->ulpi_busctl);
338 }
musb_write_ulpi_buscontrol(struct musb_regs * musbr,u8 val)339 static inline void musb_write_ulpi_buscontrol(struct musb_regs *musbr, u8 val)
340 {
341 writeb(val, &musbr->ulpi_busctl);
342 }
343
344 #endif /* __MUSB_HDRC_DEFS_H__ */
345