1 /*
2 * Copyright (c) 2009 Daniel Mack <daniel@caiaq.de>
3 * Copyright (C) 2010 Freescale Semiconductor, Inc.
4 *
5 * SPDX-License-Identifier: GPL-2.0+
6 */
7
8 #include <common.h>
9 #include <usb.h>
10 #include <errno.h>
11 #include <wait_bit.h>
12 #include <linux/compiler.h>
13 #include <usb/ehci-ci.h>
14 #include <asm/io.h>
15 #include <asm/arch/imx-regs.h>
16 #include <asm/arch/clock.h>
17 #include <asm/mach-imx/iomux-v3.h>
18 #include <asm/mach-imx/sys_proto.h>
19 #include <dm.h>
20 #include <asm/mach-types.h>
21 #include <power/regulator.h>
22 #include <linux/usb/otg.h>
23
24 #include "ehci.h"
25
26 DECLARE_GLOBAL_DATA_PTR;
27
28 #define USB_OTGREGS_OFFSET 0x000
29 #define USB_H1REGS_OFFSET 0x200
30 #define USB_H2REGS_OFFSET 0x400
31 #define USB_H3REGS_OFFSET 0x600
32 #define USB_OTHERREGS_OFFSET 0x800
33
34 #define USB_H1_CTRL_OFFSET 0x04
35
36 #define USBPHY_CTRL 0x00000030
37 #define USBPHY_CTRL_SET 0x00000034
38 #define USBPHY_CTRL_CLR 0x00000038
39 #define USBPHY_CTRL_TOG 0x0000003c
40
41 #define USBPHY_PWD 0x00000000
42 #define USBPHY_CTRL_SFTRST 0x80000000
43 #define USBPHY_CTRL_CLKGATE 0x40000000
44 #define USBPHY_CTRL_ENUTMILEVEL3 0x00008000
45 #define USBPHY_CTRL_ENUTMILEVEL2 0x00004000
46 #define USBPHY_CTRL_OTG_ID 0x08000000
47
48 #define ANADIG_USB2_CHRG_DETECT_EN_B 0x00100000
49 #define ANADIG_USB2_CHRG_DETECT_CHK_CHRG_B 0x00080000
50
51 #define ANADIG_USB2_PLL_480_CTRL_BYPASS 0x00010000
52 #define ANADIG_USB2_PLL_480_CTRL_ENABLE 0x00002000
53 #define ANADIG_USB2_PLL_480_CTRL_POWER 0x00001000
54 #define ANADIG_USB2_PLL_480_CTRL_EN_USB_CLKS 0x00000040
55
56 #define USBNC_OFFSET 0x200
57 #define USBNC_PHY_STATUS_OFFSET 0x23C
58 #define USBNC_PHYSTATUS_ID_DIG (1 << 4) /* otg_id status */
59 #define USBNC_PHYCFG2_ACAENB (1 << 4) /* otg_id detection enable */
60 #define UCTRL_PWR_POL (1 << 9) /* OTG Polarity of Power Pin */
61 #define UCTRL_OVER_CUR_POL (1 << 8) /* OTG Polarity of Overcurrent */
62 #define UCTRL_OVER_CUR_DIS (1 << 7) /* Disable OTG Overcurrent Detection */
63
64 /* USBCMD */
65 #define UCMD_RUN_STOP (1 << 0) /* controller run/stop */
66 #define UCMD_RESET (1 << 1) /* controller reset */
67
68 #if defined(CONFIG_MX6) || defined(CONFIG_MX7ULP)
69 static const unsigned phy_bases[] = {
70 USB_PHY0_BASE_ADDR,
71 #if defined(USB_PHY1_BASE_ADDR)
72 USB_PHY1_BASE_ADDR,
73 #endif
74 };
75
usb_internal_phy_clock_gate(int index,int on)76 static void usb_internal_phy_clock_gate(int index, int on)
77 {
78 void __iomem *phy_reg;
79
80 if (index >= ARRAY_SIZE(phy_bases))
81 return;
82
83 phy_reg = (void __iomem *)phy_bases[index];
84 phy_reg += on ? USBPHY_CTRL_CLR : USBPHY_CTRL_SET;
85 writel(USBPHY_CTRL_CLKGATE, phy_reg);
86 }
87
usb_power_config(int index)88 static void usb_power_config(int index)
89 {
90 #if defined(CONFIG_MX7ULP)
91 struct usbphy_regs __iomem *usbphy =
92 (struct usbphy_regs __iomem *)USB_PHY0_BASE_ADDR;
93
94 if (index > 0)
95 return;
96
97 writel(ANADIG_USB2_CHRG_DETECT_EN_B |
98 ANADIG_USB2_CHRG_DETECT_CHK_CHRG_B,
99 &usbphy->usb1_chrg_detect);
100
101 scg_enable_usb_pll(true);
102
103 #else
104 struct anatop_regs __iomem *anatop =
105 (struct anatop_regs __iomem *)ANATOP_BASE_ADDR;
106 void __iomem *chrg_detect;
107 void __iomem *pll_480_ctrl_clr;
108 void __iomem *pll_480_ctrl_set;
109
110 switch (index) {
111 case 0:
112 chrg_detect = &anatop->usb1_chrg_detect;
113 pll_480_ctrl_clr = &anatop->usb1_pll_480_ctrl_clr;
114 pll_480_ctrl_set = &anatop->usb1_pll_480_ctrl_set;
115 break;
116 case 1:
117 chrg_detect = &anatop->usb2_chrg_detect;
118 pll_480_ctrl_clr = &anatop->usb2_pll_480_ctrl_clr;
119 pll_480_ctrl_set = &anatop->usb2_pll_480_ctrl_set;
120 break;
121 default:
122 return;
123 }
124 /*
125 * Some phy and power's special controls
126 * 1. The external charger detector needs to be disabled
127 * or the signal at DP will be poor
128 * 2. The PLL's power and output to usb
129 * is totally controlled by IC, so the Software only needs
130 * to enable them at initializtion.
131 */
132 writel(ANADIG_USB2_CHRG_DETECT_EN_B |
133 ANADIG_USB2_CHRG_DETECT_CHK_CHRG_B,
134 chrg_detect);
135
136 writel(ANADIG_USB2_PLL_480_CTRL_BYPASS,
137 pll_480_ctrl_clr);
138
139 writel(ANADIG_USB2_PLL_480_CTRL_ENABLE |
140 ANADIG_USB2_PLL_480_CTRL_POWER |
141 ANADIG_USB2_PLL_480_CTRL_EN_USB_CLKS,
142 pll_480_ctrl_set);
143
144 #endif
145 }
146
147 /* Return 0 : host node, <>0 : device mode */
usb_phy_enable(int index,struct usb_ehci * ehci)148 static int usb_phy_enable(int index, struct usb_ehci *ehci)
149 {
150 void __iomem *phy_reg;
151 void __iomem *phy_ctrl;
152 void __iomem *usb_cmd;
153 int ret;
154
155 if (index >= ARRAY_SIZE(phy_bases))
156 return 0;
157
158 phy_reg = (void __iomem *)phy_bases[index];
159 phy_ctrl = (void __iomem *)(phy_reg + USBPHY_CTRL);
160 usb_cmd = (void __iomem *)&ehci->usbcmd;
161
162 /* Stop then Reset */
163 clrbits_le32(usb_cmd, UCMD_RUN_STOP);
164 ret = wait_for_bit_le32(usb_cmd, UCMD_RUN_STOP, false, 10000, false);
165 if (ret)
166 return ret;
167
168 setbits_le32(usb_cmd, UCMD_RESET);
169 ret = wait_for_bit_le32(usb_cmd, UCMD_RESET, false, 10000, false);
170 if (ret)
171 return ret;
172
173 /* Reset USBPHY module */
174 setbits_le32(phy_ctrl, USBPHY_CTRL_SFTRST);
175 udelay(10);
176
177 /* Remove CLKGATE and SFTRST */
178 clrbits_le32(phy_ctrl, USBPHY_CTRL_CLKGATE | USBPHY_CTRL_SFTRST);
179 udelay(10);
180
181 /* Power up the PHY */
182 writel(0, phy_reg + USBPHY_PWD);
183 /* enable FS/LS device */
184 setbits_le32(phy_ctrl, USBPHY_CTRL_ENUTMILEVEL2 |
185 USBPHY_CTRL_ENUTMILEVEL3);
186
187 return 0;
188 }
189
usb_phy_mode(int port)190 int usb_phy_mode(int port)
191 {
192 void __iomem *phy_reg;
193 void __iomem *phy_ctrl;
194 u32 val;
195
196 phy_reg = (void __iomem *)phy_bases[port];
197 phy_ctrl = (void __iomem *)(phy_reg + USBPHY_CTRL);
198
199 val = readl(phy_ctrl);
200
201 if (val & USBPHY_CTRL_OTG_ID)
202 return USB_INIT_DEVICE;
203 else
204 return USB_INIT_HOST;
205 }
206
207 #if defined(CONFIG_MX7ULP)
208 struct usbnc_regs {
209 u32 ctrl1;
210 u32 ctrl2;
211 u32 reserve0[2];
212 u32 hsic_ctrl;
213 };
214 #else
215 /* Base address for this IP block is 0x02184800 */
216 struct usbnc_regs {
217 u32 ctrl[4]; /* otg/host1-3 */
218 u32 uh2_hsic_ctrl;
219 u32 uh3_hsic_ctrl;
220 u32 otg_phy_ctrl_0;
221 u32 uh1_phy_ctrl_0;
222 };
223 #endif
224
225 #elif defined(CONFIG_MX7)
226 struct usbnc_regs {
227 u32 ctrl1;
228 u32 ctrl2;
229 u32 reserve1[10];
230 u32 phy_cfg1;
231 u32 phy_cfg2;
232 u32 reserve2;
233 u32 phy_status;
234 u32 reserve3[4];
235 u32 adp_cfg1;
236 u32 adp_cfg2;
237 u32 adp_status;
238 };
239
usb_power_config(int index)240 static void usb_power_config(int index)
241 {
242 struct usbnc_regs *usbnc = (struct usbnc_regs *)(USB_BASE_ADDR +
243 (0x10000 * index) + USBNC_OFFSET);
244 void __iomem *phy_cfg2 = (void __iomem *)(&usbnc->phy_cfg2);
245
246 /*
247 * Clear the ACAENB to enable usb_otg_id detection,
248 * otherwise it is the ACA detection enabled.
249 */
250 clrbits_le32(phy_cfg2, USBNC_PHYCFG2_ACAENB);
251 }
252
usb_phy_mode(int port)253 int usb_phy_mode(int port)
254 {
255 struct usbnc_regs *usbnc = (struct usbnc_regs *)(USB_BASE_ADDR +
256 (0x10000 * port) + USBNC_OFFSET);
257 void __iomem *status = (void __iomem *)(&usbnc->phy_status);
258 u32 val;
259
260 val = readl(status);
261
262 if (val & USBNC_PHYSTATUS_ID_DIG)
263 return USB_INIT_DEVICE;
264 else
265 return USB_INIT_HOST;
266 }
267 #endif
268
usb_oc_config(int index)269 static void usb_oc_config(int index)
270 {
271 #if defined(CONFIG_MX6)
272 struct usbnc_regs *usbnc = (struct usbnc_regs *)(USB_BASE_ADDR +
273 USB_OTHERREGS_OFFSET);
274 void __iomem *ctrl = (void __iomem *)(&usbnc->ctrl[index]);
275 #elif defined(CONFIG_MX7) || defined(CONFIG_MX7ULP)
276 struct usbnc_regs *usbnc = (struct usbnc_regs *)(USB_BASE_ADDR +
277 (0x10000 * index) + USBNC_OFFSET);
278 void __iomem *ctrl = (void __iomem *)(&usbnc->ctrl1);
279 #endif
280
281 #if CONFIG_MACH_TYPE == MACH_TYPE_MX6Q_ARM2
282 /* mx6qarm2 seems to required a different setting*/
283 clrbits_le32(ctrl, UCTRL_OVER_CUR_POL);
284 #else
285 setbits_le32(ctrl, UCTRL_OVER_CUR_POL);
286 #endif
287
288 setbits_le32(ctrl, UCTRL_OVER_CUR_DIS);
289
290 /* Set power polarity to high active */
291 #ifdef CONFIG_MXC_USB_OTG_HACTIVE
292 setbits_le32(ctrl, UCTRL_PWR_POL);
293 #else
294 clrbits_le32(ctrl, UCTRL_PWR_POL);
295 #endif
296 }
297
298 /**
299 * board_usb_phy_mode - override usb phy mode
300 * @port: usb host/otg port
301 *
302 * Target board specific, override usb_phy_mode.
303 * When usb-otg is used as usb host port, iomux pad usb_otg_id can be
304 * left disconnected in this case usb_phy_mode will not be able to identify
305 * the phy mode that usb port is used.
306 * Machine file overrides board_usb_phy_mode.
307 *
308 * Return: USB_INIT_DEVICE or USB_INIT_HOST
309 */
board_usb_phy_mode(int port)310 int __weak board_usb_phy_mode(int port)
311 {
312 return usb_phy_mode(port);
313 }
314
315 /**
316 * board_ehci_hcd_init - set usb vbus voltage
317 * @port: usb otg port
318 *
319 * Target board specific, setup iomux pad to setup supply vbus voltage
320 * for usb otg port. Machine board file overrides board_ehci_hcd_init
321 *
322 * Return: 0 Success
323 */
board_ehci_hcd_init(int port)324 int __weak board_ehci_hcd_init(int port)
325 {
326 return 0;
327 }
328
329 /**
330 * board_ehci_power - enables/disables usb vbus voltage
331 * @port: usb otg port
332 * @on: on/off vbus voltage
333 *
334 * Enables/disables supply vbus voltage for usb otg port.
335 * Machine board file overrides board_ehci_power
336 *
337 * Return: 0 Success
338 */
board_ehci_power(int port,int on)339 int __weak board_ehci_power(int port, int on)
340 {
341 return 0;
342 }
343
ehci_mx6_common_init(struct usb_ehci * ehci,int index)344 int ehci_mx6_common_init(struct usb_ehci *ehci, int index)
345 {
346 int ret;
347
348 enable_usboh3_clk(1);
349 mdelay(1);
350
351 /* Do board specific initialization */
352 ret = board_ehci_hcd_init(index);
353 if (ret)
354 return ret;
355
356 usb_power_config(index);
357 usb_oc_config(index);
358
359 #if defined(CONFIG_MX6) || defined(CONFIG_MX7ULP)
360 usb_internal_phy_clock_gate(index, 1);
361 usb_phy_enable(index, ehci);
362 #endif
363
364 return 0;
365 }
366
367 #if !CONFIG_IS_ENABLED(DM_USB)
ehci_hcd_init(int index,enum usb_init_type init,struct ehci_hccr ** hccr,struct ehci_hcor ** hcor)368 int ehci_hcd_init(int index, enum usb_init_type init,
369 struct ehci_hccr **hccr, struct ehci_hcor **hcor)
370 {
371 enum usb_init_type type;
372 #if defined(CONFIG_MX6)
373 u32 controller_spacing = 0x200;
374 #elif defined(CONFIG_MX7) || defined(CONFIG_MX7ULP)
375 u32 controller_spacing = 0x10000;
376 #endif
377 struct usb_ehci *ehci = (struct usb_ehci *)(USB_BASE_ADDR +
378 (controller_spacing * index));
379 int ret;
380
381 if (index > 3)
382 return -EINVAL;
383
384 ret = ehci_mx6_common_init(ehci, index);
385 if (ret)
386 return ret;
387
388 type = board_usb_phy_mode(index);
389
390 if (hccr && hcor) {
391 *hccr = (struct ehci_hccr *)((uint32_t)&ehci->caplength);
392 *hcor = (struct ehci_hcor *)((uint32_t)*hccr +
393 HC_LENGTH(ehci_readl(&(*hccr)->cr_capbase)));
394 }
395
396 if ((type == init) || (type == USB_INIT_DEVICE))
397 board_ehci_power(index, (type == USB_INIT_DEVICE) ? 0 : 1);
398 if (type != init)
399 return -ENODEV;
400 if (type == USB_INIT_DEVICE)
401 return 0;
402
403 setbits_le32(&ehci->usbmode, CM_HOST);
404 writel(CONFIG_MXC_USB_PORTSC, &ehci->portsc);
405 setbits_le32(&ehci->portsc, USB_EN);
406
407 mdelay(10);
408
409 return 0;
410 }
411
ehci_hcd_stop(int index)412 int ehci_hcd_stop(int index)
413 {
414 return 0;
415 }
416 #else
417 struct ehci_mx6_priv_data {
418 struct ehci_ctrl ctrl;
419 struct usb_ehci *ehci;
420 struct udevice *vbus_supply;
421 enum usb_init_type init_type;
422 int portnr;
423 };
424
mx6_init_after_reset(struct ehci_ctrl * dev)425 static int mx6_init_after_reset(struct ehci_ctrl *dev)
426 {
427 struct ehci_mx6_priv_data *priv = dev->priv;
428 enum usb_init_type type = priv->init_type;
429 struct usb_ehci *ehci = priv->ehci;
430 int ret;
431
432 ret = ehci_mx6_common_init(priv->ehci, priv->portnr);
433 if (ret)
434 return ret;
435
436 #if CONFIG_IS_ENABLED(DM_REGULATOR)
437 if (priv->vbus_supply) {
438 ret = regulator_set_enable(priv->vbus_supply,
439 (type == USB_INIT_DEVICE) ?
440 false : true);
441 if (ret) {
442 puts("Error enabling VBUS supply\n");
443 return ret;
444 }
445 }
446 #endif
447
448 if (type == USB_INIT_DEVICE)
449 return 0;
450
451 setbits_le32(&ehci->usbmode, CM_HOST);
452 writel(CONFIG_MXC_USB_PORTSC, &ehci->portsc);
453 setbits_le32(&ehci->portsc, USB_EN);
454
455 mdelay(10);
456
457 return 0;
458 }
459
460 static const struct ehci_ops mx6_ehci_ops = {
461 .init_after_reset = mx6_init_after_reset
462 };
463
ehci_usb_phy_mode(struct udevice * dev)464 static int ehci_usb_phy_mode(struct udevice *dev)
465 {
466 struct usb_platdata *plat = dev_get_platdata(dev);
467 void *__iomem addr = (void *__iomem)devfdt_get_addr(dev);
468 void *__iomem phy_ctrl, *__iomem phy_status;
469 const void *blob = gd->fdt_blob;
470 int offset = dev_of_offset(dev), phy_off;
471 u32 val;
472
473 /*
474 * About fsl,usbphy, Refer to
475 * Documentation/devicetree/bindings/usb/ci-hdrc-usb2.txt.
476 */
477 if (is_mx6() || is_mx7ulp()) {
478 phy_off = fdtdec_lookup_phandle(blob,
479 offset,
480 "fsl,usbphy");
481 if (phy_off < 0)
482 return -EINVAL;
483
484 addr = (void __iomem *)fdtdec_get_addr(blob, phy_off,
485 "reg");
486 if ((fdt_addr_t)addr == FDT_ADDR_T_NONE)
487 return -EINVAL;
488
489 phy_ctrl = (void __iomem *)(addr + USBPHY_CTRL);
490 val = readl(phy_ctrl);
491
492 if (val & USBPHY_CTRL_OTG_ID)
493 plat->init_type = USB_INIT_DEVICE;
494 else
495 plat->init_type = USB_INIT_HOST;
496 } else if (is_mx7()) {
497 phy_status = (void __iomem *)(addr +
498 USBNC_PHY_STATUS_OFFSET);
499 val = readl(phy_status);
500
501 if (val & USBNC_PHYSTATUS_ID_DIG)
502 plat->init_type = USB_INIT_DEVICE;
503 else
504 plat->init_type = USB_INIT_HOST;
505 } else {
506 return -EINVAL;
507 }
508
509 return 0;
510 }
511
ehci_usb_ofdata_to_platdata(struct udevice * dev)512 static int ehci_usb_ofdata_to_platdata(struct udevice *dev)
513 {
514 struct usb_platdata *plat = dev_get_platdata(dev);
515 enum usb_dr_mode dr_mode;
516
517 dr_mode = usb_get_dr_mode(dev->node);
518
519 switch (dr_mode) {
520 case USB_DR_MODE_HOST:
521 plat->init_type = USB_INIT_HOST;
522 break;
523 case USB_DR_MODE_PERIPHERAL:
524 plat->init_type = USB_INIT_DEVICE;
525 break;
526 case USB_DR_MODE_OTG:
527 case USB_DR_MODE_UNKNOWN:
528 return ehci_usb_phy_mode(dev);
529 };
530
531 return 0;
532 }
533
ehci_usb_bind(struct udevice * dev)534 static int ehci_usb_bind(struct udevice *dev)
535 {
536 /*
537 * TODO:
538 * This driver is only partly converted to DT probing and still uses
539 * a tremendous amount of hard-coded addresses. To make things worse,
540 * the driver depends on specific sequential indexing of controllers,
541 * from which it derives offsets in the PHY and ANATOP register sets.
542 *
543 * Here we attempt to calculate these indexes from DT information as
544 * well as we can. The USB controllers on all existing iMX6 SoCs
545 * are placed next to each other, at addresses incremented by 0x200,
546 * and iMX7 their addresses are shifted by 0x10000.
547 * Thus, the index is derived from the multiple of 0x200 (0x10000 for
548 * iMX7) offset from the first controller address.
549 *
550 * However, to complete conversion of this driver to DT probing, the
551 * following has to be done:
552 * - DM clock framework support for iMX must be implemented
553 * - usb_power_config() has to be converted to clock framework
554 * -> Thus, the ad-hoc "index" variable goes away.
555 * - USB PHY handling has to be factored out into separate driver
556 * -> Thus, the ad-hoc "index" variable goes away from the PHY
557 * code, the PHY driver must parse it's address from DT. This
558 * USB driver must find the PHY driver via DT phandle.
559 * -> usb_power_config() shall be moved to PHY driver
560 * With these changes in place, the ad-hoc indexing goes away and
561 * the driver is fully converted to DT probing.
562 */
563 u32 controller_spacing = is_mx7() ? 0x10000 : 0x200;
564 fdt_addr_t addr = devfdt_get_addr_index(dev, 0);
565
566 dev->req_seq = (addr - USB_BASE_ADDR) / controller_spacing;
567
568 return 0;
569 }
570
ehci_usb_probe(struct udevice * dev)571 static int ehci_usb_probe(struct udevice *dev)
572 {
573 struct usb_platdata *plat = dev_get_platdata(dev);
574 struct usb_ehci *ehci = (struct usb_ehci *)devfdt_get_addr(dev);
575 struct ehci_mx6_priv_data *priv = dev_get_priv(dev);
576 enum usb_init_type type = plat->init_type;
577 struct ehci_hccr *hccr;
578 struct ehci_hcor *hcor;
579 int ret;
580
581 priv->ehci = ehci;
582 priv->portnr = dev->seq;
583 priv->init_type = type;
584
585 #if CONFIG_IS_ENABLED(DM_REGULATOR)
586 ret = device_get_supply_regulator(dev, "vbus-supply",
587 &priv->vbus_supply);
588 if (ret)
589 debug("%s: No vbus supply\n", dev->name);
590 #endif
591 ret = ehci_mx6_common_init(ehci, priv->portnr);
592 if (ret)
593 return ret;
594
595 #if CONFIG_IS_ENABLED(DM_REGULATOR)
596 if (priv->vbus_supply) {
597 ret = regulator_set_enable(priv->vbus_supply,
598 (type == USB_INIT_DEVICE) ?
599 false : true);
600 if (ret) {
601 puts("Error enabling VBUS supply\n");
602 return ret;
603 }
604 }
605 #endif
606
607 if (priv->init_type == USB_INIT_HOST) {
608 setbits_le32(&ehci->usbmode, CM_HOST);
609 writel(CONFIG_MXC_USB_PORTSC, &ehci->portsc);
610 setbits_le32(&ehci->portsc, USB_EN);
611 }
612
613 mdelay(10);
614
615 hccr = (struct ehci_hccr *)((uint32_t)&ehci->caplength);
616 hcor = (struct ehci_hcor *)((uint32_t)hccr +
617 HC_LENGTH(ehci_readl(&(hccr)->cr_capbase)));
618
619 return ehci_register(dev, hccr, hcor, &mx6_ehci_ops, 0, priv->init_type);
620 }
621
622 static const struct udevice_id mx6_usb_ids[] = {
623 { .compatible = "fsl,imx27-usb" },
624 { }
625 };
626
627 U_BOOT_DRIVER(usb_mx6) = {
628 .name = "ehci_mx6",
629 .id = UCLASS_USB,
630 .of_match = mx6_usb_ids,
631 .ofdata_to_platdata = ehci_usb_ofdata_to_platdata,
632 .bind = ehci_usb_bind,
633 .probe = ehci_usb_probe,
634 .remove = ehci_deregister,
635 .ops = &ehci_usb_ops,
636 .platdata_auto_alloc_size = sizeof(struct usb_platdata),
637 .priv_auto_alloc_size = sizeof(struct ehci_mx6_priv_data),
638 .flags = DM_FLAG_ALLOC_PRIV_DMA,
639 };
640 #endif
641