1 /*
2 * Copyright (C) 2012 Oleksandr Tymoshenko <gonzo@freebsd.org>
3 * Copyright (C) 2014 Marek Vasut <marex@denx.de>
4 *
5 * SPDX-License-Identifier: GPL-2.0+
6 */
7
8 #include <common.h>
9 #include <dm.h>
10 #include <errno.h>
11 #include <usb.h>
12 #include <malloc.h>
13 #include <memalign.h>
14 #include <phys2bus.h>
15 #include <usbroothubdes.h>
16 #include <wait_bit.h>
17 #include <asm/io.h>
18 #include <power/regulator.h>
19 #include <reset.h>
20
21 #include "dwc2.h"
22
23 DECLARE_GLOBAL_DATA_PTR;
24
25 /* Use only HC channel 0. */
26 #define DWC2_HC_CHANNEL 0
27
28 #define DWC2_STATUS_BUF_SIZE 64
29 #define DWC2_DATA_BUF_SIZE (CONFIG_USB_DWC2_BUFFER_SIZE * 1024)
30
31 #define MAX_DEVICE 16
32 #define MAX_ENDPOINT 16
33
34 struct dwc2_priv {
35 #if CONFIG_IS_ENABLED(DM_USB)
36 uint8_t aligned_buffer[DWC2_DATA_BUF_SIZE] __aligned(ARCH_DMA_MINALIGN);
37 uint8_t status_buffer[DWC2_STATUS_BUF_SIZE] __aligned(ARCH_DMA_MINALIGN);
38 #ifdef CONFIG_DM_REGULATOR
39 struct udevice *vbus_supply;
40 #endif
41 #else
42 uint8_t *aligned_buffer;
43 uint8_t *status_buffer;
44 #endif
45 u8 in_data_toggle[MAX_DEVICE][MAX_ENDPOINT];
46 u8 out_data_toggle[MAX_DEVICE][MAX_ENDPOINT];
47 struct dwc2_core_regs *regs;
48 int root_hub_devnum;
49 bool ext_vbus;
50 /*
51 * The hnp/srp capability must be disabled if the platform
52 * does't support hnp/srp. Otherwise the force mode can't work.
53 */
54 bool hnp_srp_disable;
55 bool oc_disable;
56
57 struct reset_ctl_bulk resets;
58 };
59
60 #if !CONFIG_IS_ENABLED(DM_USB)
61 /* We need cacheline-aligned buffers for DMA transfers and dcache support */
62 DEFINE_ALIGN_BUFFER(uint8_t, aligned_buffer_addr, DWC2_DATA_BUF_SIZE,
63 ARCH_DMA_MINALIGN);
64 DEFINE_ALIGN_BUFFER(uint8_t, status_buffer_addr, DWC2_STATUS_BUF_SIZE,
65 ARCH_DMA_MINALIGN);
66
67 static struct dwc2_priv local;
68 #endif
69
70 /*
71 * DWC2 IP interface
72 */
73
74 /*
75 * Initializes the FSLSPClkSel field of the HCFG register
76 * depending on the PHY type.
77 */
init_fslspclksel(struct dwc2_core_regs * regs)78 static void init_fslspclksel(struct dwc2_core_regs *regs)
79 {
80 uint32_t phyclk;
81
82 #if (CONFIG_DWC2_PHY_TYPE == DWC2_PHY_TYPE_FS)
83 phyclk = DWC2_HCFG_FSLSPCLKSEL_48_MHZ; /* Full speed PHY */
84 #else
85 /* High speed PHY running at full speed or high speed */
86 phyclk = DWC2_HCFG_FSLSPCLKSEL_30_60_MHZ;
87 #endif
88
89 #ifdef CONFIG_DWC2_ULPI_FS_LS
90 uint32_t hwcfg2 = readl(®s->ghwcfg2);
91 uint32_t hval = (ghwcfg2 & DWC2_HWCFG2_HS_PHY_TYPE_MASK) >>
92 DWC2_HWCFG2_HS_PHY_TYPE_OFFSET;
93 uint32_t fval = (ghwcfg2 & DWC2_HWCFG2_FS_PHY_TYPE_MASK) >>
94 DWC2_HWCFG2_FS_PHY_TYPE_OFFSET;
95
96 if (hval == 2 && fval == 1)
97 phyclk = DWC2_HCFG_FSLSPCLKSEL_48_MHZ; /* Full speed PHY */
98 #endif
99
100 clrsetbits_le32(®s->host_regs.hcfg,
101 DWC2_HCFG_FSLSPCLKSEL_MASK,
102 phyclk << DWC2_HCFG_FSLSPCLKSEL_OFFSET);
103 }
104
105 /*
106 * Flush a Tx FIFO.
107 *
108 * @param regs Programming view of DWC_otg controller.
109 * @param num Tx FIFO to flush.
110 */
dwc_otg_flush_tx_fifo(struct dwc2_core_regs * regs,const int num)111 static void dwc_otg_flush_tx_fifo(struct dwc2_core_regs *regs, const int num)
112 {
113 int ret;
114
115 writel(DWC2_GRSTCTL_TXFFLSH | (num << DWC2_GRSTCTL_TXFNUM_OFFSET),
116 ®s->grstctl);
117 ret = wait_for_bit_le32(®s->grstctl, DWC2_GRSTCTL_TXFFLSH,
118 false, 1000, false);
119 if (ret)
120 dev_info(dev, "%s: Timeout!\n", __func__);
121
122 /* Wait for 3 PHY Clocks */
123 udelay(1);
124 }
125
126 /*
127 * Flush Rx FIFO.
128 *
129 * @param regs Programming view of DWC_otg controller.
130 */
dwc_otg_flush_rx_fifo(struct dwc2_core_regs * regs)131 static void dwc_otg_flush_rx_fifo(struct dwc2_core_regs *regs)
132 {
133 int ret;
134
135 writel(DWC2_GRSTCTL_RXFFLSH, ®s->grstctl);
136 ret = wait_for_bit_le32(®s->grstctl, DWC2_GRSTCTL_RXFFLSH,
137 false, 1000, false);
138 if (ret)
139 dev_info(dev, "%s: Timeout!\n", __func__);
140
141 /* Wait for 3 PHY Clocks */
142 udelay(1);
143 }
144
145 /*
146 * Do core a soft reset of the core. Be careful with this because it
147 * resets all the internal state machines of the core.
148 */
dwc_otg_core_reset(struct dwc2_core_regs * regs)149 static void dwc_otg_core_reset(struct dwc2_core_regs *regs)
150 {
151 int ret;
152
153 /* Wait for AHB master IDLE state. */
154 ret = wait_for_bit_le32(®s->grstctl, DWC2_GRSTCTL_AHBIDLE,
155 true, 1000, false);
156 if (ret)
157 dev_info(dev, "%s: Timeout!\n", __func__);
158
159 /* Core Soft Reset */
160 writel(DWC2_GRSTCTL_CSFTRST, ®s->grstctl);
161 ret = wait_for_bit_le32(®s->grstctl, DWC2_GRSTCTL_CSFTRST,
162 false, 1000, false);
163 if (ret)
164 dev_info(dev, "%s: Timeout!\n", __func__);
165
166 /*
167 * Wait for core to come out of reset.
168 * NOTE: This long sleep is _very_ important, otherwise the core will
169 * not stay in host mode after a connector ID change!
170 */
171 mdelay(100);
172 }
173
174 #if CONFIG_IS_ENABLED(DM_USB) && defined(CONFIG_DM_REGULATOR)
dwc_vbus_supply_init(struct udevice * dev)175 static int dwc_vbus_supply_init(struct udevice *dev)
176 {
177 struct dwc2_priv *priv = dev_get_priv(dev);
178 int ret;
179
180 ret = device_get_supply_regulator(dev, "vbus-supply",
181 &priv->vbus_supply);
182 if (ret) {
183 debug("%s: No vbus supply\n", dev->name);
184 return 0;
185 }
186
187 ret = regulator_set_enable(priv->vbus_supply, true);
188 if (ret) {
189 dev_err(dev, "Error enabling vbus supply\n");
190 return ret;
191 }
192
193 return 0;
194 }
195
dwc_vbus_supply_exit(struct udevice * dev)196 static int dwc_vbus_supply_exit(struct udevice *dev)
197 {
198 struct dwc2_priv *priv = dev_get_priv(dev);
199 int ret;
200
201 if (priv->vbus_supply) {
202 ret = regulator_set_enable(priv->vbus_supply, false);
203 if (ret) {
204 dev_err(dev, "Error disabling vbus supply\n");
205 return ret;
206 }
207 }
208
209 return 0;
210 }
211 #else
dwc_vbus_supply_init(struct udevice * dev)212 static int dwc_vbus_supply_init(struct udevice *dev)
213 {
214 return 0;
215 }
216
217 #if CONFIG_IS_ENABLED(DM_USB)
dwc_vbus_supply_exit(struct udevice * dev)218 static int dwc_vbus_supply_exit(struct udevice *dev)
219 {
220 return 0;
221 }
222 #endif
223 #endif
224
225 /*
226 * This function initializes the DWC_otg controller registers for
227 * host mode.
228 *
229 * This function flushes the Tx and Rx FIFOs and it flushes any entries in the
230 * request queues. Host channels are reset to ensure that they are ready for
231 * performing transfers.
232 *
233 * @param dev USB Device (NULL if driver model is not being used)
234 * @param regs Programming view of DWC_otg controller
235 *
236 */
dwc_otg_core_host_init(struct udevice * dev,struct dwc2_core_regs * regs)237 static void dwc_otg_core_host_init(struct udevice *dev,
238 struct dwc2_core_regs *regs)
239 {
240 uint32_t nptxfifosize = 0;
241 uint32_t ptxfifosize = 0;
242 uint32_t hprt0 = 0;
243 int i, ret, num_channels;
244
245 /* Restart the Phy Clock */
246 writel(0, ®s->pcgcctl);
247
248 /* Initialize Host Configuration Register */
249 init_fslspclksel(regs);
250 #ifdef CONFIG_DWC2_DFLT_SPEED_FULL
251 setbits_le32(®s->host_regs.hcfg, DWC2_HCFG_FSLSSUPP);
252 #endif
253
254 /* Configure data FIFO sizes */
255 #ifdef CONFIG_DWC2_ENABLE_DYNAMIC_FIFO
256 if (readl(®s->ghwcfg2) & DWC2_HWCFG2_DYNAMIC_FIFO) {
257 /* Rx FIFO */
258 writel(CONFIG_DWC2_HOST_RX_FIFO_SIZE, ®s->grxfsiz);
259
260 /* Non-periodic Tx FIFO */
261 nptxfifosize |= CONFIG_DWC2_HOST_NPERIO_TX_FIFO_SIZE <<
262 DWC2_FIFOSIZE_DEPTH_OFFSET;
263 nptxfifosize |= CONFIG_DWC2_HOST_RX_FIFO_SIZE <<
264 DWC2_FIFOSIZE_STARTADDR_OFFSET;
265 writel(nptxfifosize, ®s->gnptxfsiz);
266
267 /* Periodic Tx FIFO */
268 ptxfifosize |= CONFIG_DWC2_HOST_PERIO_TX_FIFO_SIZE <<
269 DWC2_FIFOSIZE_DEPTH_OFFSET;
270 ptxfifosize |= (CONFIG_DWC2_HOST_RX_FIFO_SIZE +
271 CONFIG_DWC2_HOST_NPERIO_TX_FIFO_SIZE) <<
272 DWC2_FIFOSIZE_STARTADDR_OFFSET;
273 writel(ptxfifosize, ®s->hptxfsiz);
274 }
275 #endif
276
277 /* Clear Host Set HNP Enable in the OTG Control Register */
278 clrbits_le32(®s->gotgctl, DWC2_GOTGCTL_HSTSETHNPEN);
279
280 /* Make sure the FIFOs are flushed. */
281 dwc_otg_flush_tx_fifo(regs, 0x10); /* All Tx FIFOs */
282 dwc_otg_flush_rx_fifo(regs);
283
284 /* Flush out any leftover queued requests. */
285 num_channels = readl(®s->ghwcfg2);
286 num_channels &= DWC2_HWCFG2_NUM_HOST_CHAN_MASK;
287 num_channels >>= DWC2_HWCFG2_NUM_HOST_CHAN_OFFSET;
288 num_channels += 1;
289
290 for (i = 0; i < num_channels; i++)
291 clrsetbits_le32(®s->hc_regs[i].hcchar,
292 DWC2_HCCHAR_CHEN | DWC2_HCCHAR_EPDIR,
293 DWC2_HCCHAR_CHDIS);
294
295 /* Halt all channels to put them into a known state. */
296 for (i = 0; i < num_channels; i++) {
297 clrsetbits_le32(®s->hc_regs[i].hcchar,
298 DWC2_HCCHAR_EPDIR,
299 DWC2_HCCHAR_CHEN | DWC2_HCCHAR_CHDIS);
300 ret = wait_for_bit_le32(®s->hc_regs[i].hcchar,
301 DWC2_HCCHAR_CHEN, false, 1000, false);
302 if (ret)
303 dev_info("%s: Timeout!\n", __func__);
304 }
305
306 /* Turn on the vbus power. */
307 if (readl(®s->gintsts) & DWC2_GINTSTS_CURMODE_HOST) {
308 hprt0 = readl(®s->hprt0);
309 hprt0 &= ~(DWC2_HPRT0_PRTENA | DWC2_HPRT0_PRTCONNDET);
310 hprt0 &= ~(DWC2_HPRT0_PRTENCHNG | DWC2_HPRT0_PRTOVRCURRCHNG);
311 if (!(hprt0 & DWC2_HPRT0_PRTPWR)) {
312 hprt0 |= DWC2_HPRT0_PRTPWR;
313 writel(hprt0, ®s->hprt0);
314 }
315 }
316
317 if (dev)
318 dwc_vbus_supply_init(dev);
319 }
320
321 /*
322 * This function initializes the DWC_otg controller registers and
323 * prepares the core for device mode or host mode operation.
324 *
325 * @param regs Programming view of the DWC_otg controller
326 */
dwc_otg_core_init(struct dwc2_priv * priv)327 static void dwc_otg_core_init(struct dwc2_priv *priv)
328 {
329 struct dwc2_core_regs *regs = priv->regs;
330 uint32_t ahbcfg = 0;
331 uint32_t usbcfg = 0;
332 uint8_t brst_sz = CONFIG_DWC2_DMA_BURST_SIZE;
333
334 /* Common Initialization */
335 usbcfg = readl(®s->gusbcfg);
336
337 /* Program the ULPI External VBUS bit if needed */
338 if (priv->ext_vbus) {
339 usbcfg |= DWC2_GUSBCFG_ULPI_EXT_VBUS_DRV;
340 if (!priv->oc_disable) {
341 usbcfg |= DWC2_GUSBCFG_ULPI_INT_VBUS_INDICATOR |
342 DWC2_GUSBCFG_INDICATOR_PASSTHROUGH;
343 }
344 } else {
345 usbcfg &= ~DWC2_GUSBCFG_ULPI_EXT_VBUS_DRV;
346 }
347
348 /* Set external TS Dline pulsing */
349 #ifdef CONFIG_DWC2_TS_DLINE
350 usbcfg |= DWC2_GUSBCFG_TERM_SEL_DL_PULSE;
351 #else
352 usbcfg &= ~DWC2_GUSBCFG_TERM_SEL_DL_PULSE;
353 #endif
354 writel(usbcfg, ®s->gusbcfg);
355
356 /* Reset the Controller */
357 dwc_otg_core_reset(regs);
358
359 /*
360 * This programming sequence needs to happen in FS mode before
361 * any other programming occurs
362 */
363 #if defined(CONFIG_DWC2_DFLT_SPEED_FULL) && \
364 (CONFIG_DWC2_PHY_TYPE == DWC2_PHY_TYPE_FS)
365 /* If FS mode with FS PHY */
366 setbits_le32(®s->gusbcfg, DWC2_GUSBCFG_PHYSEL);
367
368 /* Reset after a PHY select */
369 dwc_otg_core_reset(regs);
370
371 /*
372 * Program DCFG.DevSpd or HCFG.FSLSPclkSel to 48Mhz in FS.
373 * Also do this on HNP Dev/Host mode switches (done in dev_init
374 * and host_init).
375 */
376 if (readl(®s->gintsts) & DWC2_GINTSTS_CURMODE_HOST)
377 init_fslspclksel(regs);
378
379 #ifdef CONFIG_DWC2_I2C_ENABLE
380 /* Program GUSBCFG.OtgUtmifsSel to I2C */
381 setbits_le32(®s->gusbcfg, DWC2_GUSBCFG_OTGUTMIFSSEL);
382
383 /* Program GI2CCTL.I2CEn */
384 clrsetbits_le32(®s->gi2cctl, DWC2_GI2CCTL_I2CEN |
385 DWC2_GI2CCTL_I2CDEVADDR_MASK,
386 1 << DWC2_GI2CCTL_I2CDEVADDR_OFFSET);
387 setbits_le32(®s->gi2cctl, DWC2_GI2CCTL_I2CEN);
388 #endif
389
390 #else
391 /* High speed PHY. */
392
393 /*
394 * HS PHY parameters. These parameters are preserved during
395 * soft reset so only program the first time. Do a soft reset
396 * immediately after setting phyif.
397 */
398 usbcfg &= ~(DWC2_GUSBCFG_ULPI_UTMI_SEL | DWC2_GUSBCFG_PHYIF);
399 usbcfg |= CONFIG_DWC2_PHY_TYPE << DWC2_GUSBCFG_ULPI_UTMI_SEL_OFFSET;
400
401 if (usbcfg & DWC2_GUSBCFG_ULPI_UTMI_SEL) { /* ULPI interface */
402 #ifdef CONFIG_DWC2_PHY_ULPI_DDR
403 usbcfg |= DWC2_GUSBCFG_DDRSEL;
404 #else
405 usbcfg &= ~DWC2_GUSBCFG_DDRSEL;
406 #endif
407 } else { /* UTMI+ interface */
408 #if (CONFIG_DWC2_UTMI_WIDTH == 16)
409 usbcfg |= DWC2_GUSBCFG_PHYIF;
410 #endif
411 }
412
413 writel(usbcfg, ®s->gusbcfg);
414
415 /* Reset after setting the PHY parameters */
416 dwc_otg_core_reset(regs);
417 #endif
418
419 usbcfg = readl(®s->gusbcfg);
420 usbcfg &= ~(DWC2_GUSBCFG_ULPI_FSLS | DWC2_GUSBCFG_ULPI_CLK_SUS_M);
421 #ifdef CONFIG_DWC2_ULPI_FS_LS
422 uint32_t hwcfg2 = readl(®s->ghwcfg2);
423 uint32_t hval = (ghwcfg2 & DWC2_HWCFG2_HS_PHY_TYPE_MASK) >>
424 DWC2_HWCFG2_HS_PHY_TYPE_OFFSET;
425 uint32_t fval = (ghwcfg2 & DWC2_HWCFG2_FS_PHY_TYPE_MASK) >>
426 DWC2_HWCFG2_FS_PHY_TYPE_OFFSET;
427 if (hval == 2 && fval == 1) {
428 usbcfg |= DWC2_GUSBCFG_ULPI_FSLS;
429 usbcfg |= DWC2_GUSBCFG_ULPI_CLK_SUS_M;
430 }
431 #endif
432 if (priv->hnp_srp_disable)
433 usbcfg |= DWC2_GUSBCFG_FORCEHOSTMODE;
434
435 writel(usbcfg, ®s->gusbcfg);
436
437 /* Program the GAHBCFG Register. */
438 switch (readl(®s->ghwcfg2) & DWC2_HWCFG2_ARCHITECTURE_MASK) {
439 case DWC2_HWCFG2_ARCHITECTURE_SLAVE_ONLY:
440 break;
441 case DWC2_HWCFG2_ARCHITECTURE_EXT_DMA:
442 while (brst_sz > 1) {
443 ahbcfg |= ahbcfg + (1 << DWC2_GAHBCFG_HBURSTLEN_OFFSET);
444 ahbcfg &= DWC2_GAHBCFG_HBURSTLEN_MASK;
445 brst_sz >>= 1;
446 }
447
448 #ifdef CONFIG_DWC2_DMA_ENABLE
449 ahbcfg |= DWC2_GAHBCFG_DMAENABLE;
450 #endif
451 break;
452
453 case DWC2_HWCFG2_ARCHITECTURE_INT_DMA:
454 ahbcfg |= DWC2_GAHBCFG_HBURSTLEN_INCR4;
455 #ifdef CONFIG_DWC2_DMA_ENABLE
456 ahbcfg |= DWC2_GAHBCFG_DMAENABLE;
457 #endif
458 break;
459 }
460
461 writel(ahbcfg, ®s->gahbcfg);
462
463 /* Program the capabilities in GUSBCFG Register */
464 usbcfg = 0;
465
466 if (!priv->hnp_srp_disable)
467 usbcfg |= DWC2_GUSBCFG_HNPCAP | DWC2_GUSBCFG_SRPCAP;
468 #ifdef CONFIG_DWC2_IC_USB_CAP
469 usbcfg |= DWC2_GUSBCFG_IC_USB_CAP;
470 #endif
471
472 setbits_le32(®s->gusbcfg, usbcfg);
473 }
474
475 /*
476 * Prepares a host channel for transferring packets to/from a specific
477 * endpoint. The HCCHARn register is set up with the characteristics specified
478 * in _hc. Host channel interrupts that may need to be serviced while this
479 * transfer is in progress are enabled.
480 *
481 * @param regs Programming view of DWC_otg controller
482 * @param hc Information needed to initialize the host channel
483 */
dwc_otg_hc_init(struct dwc2_core_regs * regs,uint8_t hc_num,struct usb_device * dev,uint8_t dev_addr,uint8_t ep_num,uint8_t ep_is_in,uint8_t ep_type,uint16_t max_packet)484 static void dwc_otg_hc_init(struct dwc2_core_regs *regs, uint8_t hc_num,
485 struct usb_device *dev, uint8_t dev_addr, uint8_t ep_num,
486 uint8_t ep_is_in, uint8_t ep_type, uint16_t max_packet)
487 {
488 struct dwc2_hc_regs *hc_regs = ®s->hc_regs[hc_num];
489 uint32_t hcchar = (dev_addr << DWC2_HCCHAR_DEVADDR_OFFSET) |
490 (ep_num << DWC2_HCCHAR_EPNUM_OFFSET) |
491 (ep_is_in << DWC2_HCCHAR_EPDIR_OFFSET) |
492 (ep_type << DWC2_HCCHAR_EPTYPE_OFFSET) |
493 (max_packet << DWC2_HCCHAR_MPS_OFFSET);
494
495 if (dev->speed == USB_SPEED_LOW)
496 hcchar |= DWC2_HCCHAR_LSPDDEV;
497
498 /*
499 * Program the HCCHARn register with the endpoint characteristics
500 * for the current transfer.
501 */
502 writel(hcchar, &hc_regs->hcchar);
503
504 /* Program the HCSPLIT register, default to no SPLIT */
505 writel(0, &hc_regs->hcsplt);
506 }
507
dwc_otg_hc_init_split(struct dwc2_hc_regs * hc_regs,uint8_t hub_devnum,uint8_t hub_port)508 static void dwc_otg_hc_init_split(struct dwc2_hc_regs *hc_regs,
509 uint8_t hub_devnum, uint8_t hub_port)
510 {
511 uint32_t hcsplt = 0;
512
513 hcsplt = DWC2_HCSPLT_SPLTENA;
514 hcsplt |= hub_devnum << DWC2_HCSPLT_HUBADDR_OFFSET;
515 hcsplt |= hub_port << DWC2_HCSPLT_PRTADDR_OFFSET;
516
517 /* Program the HCSPLIT register for SPLITs */
518 writel(hcsplt, &hc_regs->hcsplt);
519 }
520
521 /*
522 * DWC2 to USB API interface
523 */
524 /* Direction: In ; Request: Status */
dwc_otg_submit_rh_msg_in_status(struct dwc2_core_regs * regs,struct usb_device * dev,void * buffer,int txlen,struct devrequest * cmd)525 static int dwc_otg_submit_rh_msg_in_status(struct dwc2_core_regs *regs,
526 struct usb_device *dev, void *buffer,
527 int txlen, struct devrequest *cmd)
528 {
529 uint32_t hprt0 = 0;
530 uint32_t port_status = 0;
531 uint32_t port_change = 0;
532 int len = 0;
533 int stat = 0;
534
535 switch (cmd->requesttype & ~USB_DIR_IN) {
536 case 0:
537 *(uint16_t *)buffer = cpu_to_le16(1);
538 len = 2;
539 break;
540 case USB_RECIP_INTERFACE:
541 case USB_RECIP_ENDPOINT:
542 *(uint16_t *)buffer = cpu_to_le16(0);
543 len = 2;
544 break;
545 case USB_TYPE_CLASS:
546 *(uint32_t *)buffer = cpu_to_le32(0);
547 len = 4;
548 break;
549 case USB_RECIP_OTHER | USB_TYPE_CLASS:
550 hprt0 = readl(®s->hprt0);
551 if (hprt0 & DWC2_HPRT0_PRTCONNSTS)
552 port_status |= USB_PORT_STAT_CONNECTION;
553 if (hprt0 & DWC2_HPRT0_PRTENA)
554 port_status |= USB_PORT_STAT_ENABLE;
555 if (hprt0 & DWC2_HPRT0_PRTSUSP)
556 port_status |= USB_PORT_STAT_SUSPEND;
557 if (hprt0 & DWC2_HPRT0_PRTOVRCURRACT)
558 port_status |= USB_PORT_STAT_OVERCURRENT;
559 if (hprt0 & DWC2_HPRT0_PRTRST)
560 port_status |= USB_PORT_STAT_RESET;
561 if (hprt0 & DWC2_HPRT0_PRTPWR)
562 port_status |= USB_PORT_STAT_POWER;
563
564 if ((hprt0 & DWC2_HPRT0_PRTSPD_MASK) == DWC2_HPRT0_PRTSPD_LOW)
565 port_status |= USB_PORT_STAT_LOW_SPEED;
566 else if ((hprt0 & DWC2_HPRT0_PRTSPD_MASK) ==
567 DWC2_HPRT0_PRTSPD_HIGH)
568 port_status |= USB_PORT_STAT_HIGH_SPEED;
569
570 if (hprt0 & DWC2_HPRT0_PRTENCHNG)
571 port_change |= USB_PORT_STAT_C_ENABLE;
572 if (hprt0 & DWC2_HPRT0_PRTCONNDET)
573 port_change |= USB_PORT_STAT_C_CONNECTION;
574 if (hprt0 & DWC2_HPRT0_PRTOVRCURRCHNG)
575 port_change |= USB_PORT_STAT_C_OVERCURRENT;
576
577 *(uint32_t *)buffer = cpu_to_le32(port_status |
578 (port_change << 16));
579 len = 4;
580 break;
581 default:
582 puts("unsupported root hub command\n");
583 stat = USB_ST_STALLED;
584 }
585
586 dev->act_len = min(len, txlen);
587 dev->status = stat;
588
589 return stat;
590 }
591
592 /* Direction: In ; Request: Descriptor */
dwc_otg_submit_rh_msg_in_descriptor(struct usb_device * dev,void * buffer,int txlen,struct devrequest * cmd)593 static int dwc_otg_submit_rh_msg_in_descriptor(struct usb_device *dev,
594 void *buffer, int txlen,
595 struct devrequest *cmd)
596 {
597 unsigned char data[32];
598 uint32_t dsc;
599 int len = 0;
600 int stat = 0;
601 uint16_t wValue = cpu_to_le16(cmd->value);
602 uint16_t wLength = cpu_to_le16(cmd->length);
603
604 switch (cmd->requesttype & ~USB_DIR_IN) {
605 case 0:
606 switch (wValue & 0xff00) {
607 case 0x0100: /* device descriptor */
608 len = min3(txlen, (int)sizeof(root_hub_dev_des), (int)wLength);
609 memcpy(buffer, root_hub_dev_des, len);
610 break;
611 case 0x0200: /* configuration descriptor */
612 len = min3(txlen, (int)sizeof(root_hub_config_des), (int)wLength);
613 memcpy(buffer, root_hub_config_des, len);
614 break;
615 case 0x0300: /* string descriptors */
616 switch (wValue & 0xff) {
617 case 0x00:
618 len = min3(txlen, (int)sizeof(root_hub_str_index0),
619 (int)wLength);
620 memcpy(buffer, root_hub_str_index0, len);
621 break;
622 case 0x01:
623 len = min3(txlen, (int)sizeof(root_hub_str_index1),
624 (int)wLength);
625 memcpy(buffer, root_hub_str_index1, len);
626 break;
627 }
628 break;
629 default:
630 stat = USB_ST_STALLED;
631 }
632 break;
633
634 case USB_TYPE_CLASS:
635 /* Root port config, set 1 port and nothing else. */
636 dsc = 0x00000001;
637
638 data[0] = 9; /* min length; */
639 data[1] = 0x29;
640 data[2] = dsc & RH_A_NDP;
641 data[3] = 0;
642 if (dsc & RH_A_PSM)
643 data[3] |= 0x1;
644 if (dsc & RH_A_NOCP)
645 data[3] |= 0x10;
646 else if (dsc & RH_A_OCPM)
647 data[3] |= 0x8;
648
649 /* corresponds to data[4-7] */
650 data[5] = (dsc & RH_A_POTPGT) >> 24;
651 data[7] = dsc & RH_B_DR;
652 if (data[2] < 7) {
653 data[8] = 0xff;
654 } else {
655 data[0] += 2;
656 data[8] = (dsc & RH_B_DR) >> 8;
657 data[9] = 0xff;
658 data[10] = data[9];
659 }
660
661 len = min3(txlen, (int)data[0], (int)wLength);
662 memcpy(buffer, data, len);
663 break;
664 default:
665 puts("unsupported root hub command\n");
666 stat = USB_ST_STALLED;
667 }
668
669 dev->act_len = min(len, txlen);
670 dev->status = stat;
671
672 return stat;
673 }
674
675 /* Direction: In ; Request: Configuration */
dwc_otg_submit_rh_msg_in_configuration(struct usb_device * dev,void * buffer,int txlen,struct devrequest * cmd)676 static int dwc_otg_submit_rh_msg_in_configuration(struct usb_device *dev,
677 void *buffer, int txlen,
678 struct devrequest *cmd)
679 {
680 int len = 0;
681 int stat = 0;
682
683 switch (cmd->requesttype & ~USB_DIR_IN) {
684 case 0:
685 *(uint8_t *)buffer = 0x01;
686 len = 1;
687 break;
688 default:
689 puts("unsupported root hub command\n");
690 stat = USB_ST_STALLED;
691 }
692
693 dev->act_len = min(len, txlen);
694 dev->status = stat;
695
696 return stat;
697 }
698
699 /* Direction: In */
dwc_otg_submit_rh_msg_in(struct dwc2_priv * priv,struct usb_device * dev,void * buffer,int txlen,struct devrequest * cmd)700 static int dwc_otg_submit_rh_msg_in(struct dwc2_priv *priv,
701 struct usb_device *dev, void *buffer,
702 int txlen, struct devrequest *cmd)
703 {
704 switch (cmd->request) {
705 case USB_REQ_GET_STATUS:
706 return dwc_otg_submit_rh_msg_in_status(priv->regs, dev, buffer,
707 txlen, cmd);
708 case USB_REQ_GET_DESCRIPTOR:
709 return dwc_otg_submit_rh_msg_in_descriptor(dev, buffer,
710 txlen, cmd);
711 case USB_REQ_GET_CONFIGURATION:
712 return dwc_otg_submit_rh_msg_in_configuration(dev, buffer,
713 txlen, cmd);
714 default:
715 puts("unsupported root hub command\n");
716 return USB_ST_STALLED;
717 }
718 }
719
720 /* Direction: Out */
dwc_otg_submit_rh_msg_out(struct dwc2_priv * priv,struct usb_device * dev,void * buffer,int txlen,struct devrequest * cmd)721 static int dwc_otg_submit_rh_msg_out(struct dwc2_priv *priv,
722 struct usb_device *dev,
723 void *buffer, int txlen,
724 struct devrequest *cmd)
725 {
726 struct dwc2_core_regs *regs = priv->regs;
727 int len = 0;
728 int stat = 0;
729 uint16_t bmrtype_breq = cmd->requesttype | (cmd->request << 8);
730 uint16_t wValue = cpu_to_le16(cmd->value);
731
732 switch (bmrtype_breq & ~USB_DIR_IN) {
733 case (USB_REQ_CLEAR_FEATURE << 8) | USB_RECIP_ENDPOINT:
734 case (USB_REQ_CLEAR_FEATURE << 8) | USB_TYPE_CLASS:
735 break;
736
737 case (USB_REQ_CLEAR_FEATURE << 8) | USB_RECIP_OTHER | USB_TYPE_CLASS:
738 switch (wValue) {
739 case USB_PORT_FEAT_C_CONNECTION:
740 setbits_le32(®s->hprt0, DWC2_HPRT0_PRTCONNDET);
741 break;
742 }
743 break;
744
745 case (USB_REQ_SET_FEATURE << 8) | USB_RECIP_OTHER | USB_TYPE_CLASS:
746 switch (wValue) {
747 case USB_PORT_FEAT_SUSPEND:
748 break;
749
750 case USB_PORT_FEAT_RESET:
751 clrsetbits_le32(®s->hprt0, DWC2_HPRT0_PRTENA |
752 DWC2_HPRT0_PRTCONNDET |
753 DWC2_HPRT0_PRTENCHNG |
754 DWC2_HPRT0_PRTOVRCURRCHNG,
755 DWC2_HPRT0_PRTRST);
756 mdelay(50);
757 clrbits_le32(®s->hprt0, DWC2_HPRT0_PRTRST);
758 break;
759
760 case USB_PORT_FEAT_POWER:
761 clrsetbits_le32(®s->hprt0, DWC2_HPRT0_PRTENA |
762 DWC2_HPRT0_PRTCONNDET |
763 DWC2_HPRT0_PRTENCHNG |
764 DWC2_HPRT0_PRTOVRCURRCHNG,
765 DWC2_HPRT0_PRTRST);
766 break;
767
768 case USB_PORT_FEAT_ENABLE:
769 break;
770 }
771 break;
772 case (USB_REQ_SET_ADDRESS << 8):
773 priv->root_hub_devnum = wValue;
774 break;
775 case (USB_REQ_SET_CONFIGURATION << 8):
776 break;
777 default:
778 puts("unsupported root hub command\n");
779 stat = USB_ST_STALLED;
780 }
781
782 len = min(len, txlen);
783
784 dev->act_len = len;
785 dev->status = stat;
786
787 return stat;
788 }
789
dwc_otg_submit_rh_msg(struct dwc2_priv * priv,struct usb_device * dev,unsigned long pipe,void * buffer,int txlen,struct devrequest * cmd)790 static int dwc_otg_submit_rh_msg(struct dwc2_priv *priv, struct usb_device *dev,
791 unsigned long pipe, void *buffer, int txlen,
792 struct devrequest *cmd)
793 {
794 int stat = 0;
795
796 if (usb_pipeint(pipe)) {
797 puts("Root-Hub submit IRQ: NOT implemented\n");
798 return 0;
799 }
800
801 if (cmd->requesttype & USB_DIR_IN)
802 stat = dwc_otg_submit_rh_msg_in(priv, dev, buffer, txlen, cmd);
803 else
804 stat = dwc_otg_submit_rh_msg_out(priv, dev, buffer, txlen, cmd);
805
806 mdelay(1);
807
808 return stat;
809 }
810
wait_for_chhltd(struct dwc2_hc_regs * hc_regs,uint32_t * sub,u8 * toggle)811 int wait_for_chhltd(struct dwc2_hc_regs *hc_regs, uint32_t *sub, u8 *toggle)
812 {
813 int ret;
814 uint32_t hcint, hctsiz;
815
816 ret = wait_for_bit_le32(&hc_regs->hcint, DWC2_HCINT_CHHLTD, true,
817 2000, false);
818 if (ret)
819 return ret;
820
821 hcint = readl(&hc_regs->hcint);
822 hctsiz = readl(&hc_regs->hctsiz);
823 *sub = (hctsiz & DWC2_HCTSIZ_XFERSIZE_MASK) >>
824 DWC2_HCTSIZ_XFERSIZE_OFFSET;
825 *toggle = (hctsiz & DWC2_HCTSIZ_PID_MASK) >> DWC2_HCTSIZ_PID_OFFSET;
826
827 debug("%s: HCINT=%08x sub=%u toggle=%d\n", __func__, hcint, *sub,
828 *toggle);
829
830 if (hcint & DWC2_HCINT_XFERCOMP)
831 return 0;
832
833 if (hcint & (DWC2_HCINT_NAK | DWC2_HCINT_FRMOVRUN))
834 return -EAGAIN;
835
836 debug("%s: Error (HCINT=%08x)\n", __func__, hcint);
837 return -EINVAL;
838 }
839
840 static int dwc2_eptype[] = {
841 DWC2_HCCHAR_EPTYPE_ISOC,
842 DWC2_HCCHAR_EPTYPE_INTR,
843 DWC2_HCCHAR_EPTYPE_CONTROL,
844 DWC2_HCCHAR_EPTYPE_BULK,
845 };
846
transfer_chunk(struct dwc2_hc_regs * hc_regs,void * aligned_buffer,u8 * pid,int in,void * buffer,int num_packets,int xfer_len,int * actual_len,int odd_frame)847 static int transfer_chunk(struct dwc2_hc_regs *hc_regs, void *aligned_buffer,
848 u8 *pid, int in, void *buffer, int num_packets,
849 int xfer_len, int *actual_len, int odd_frame)
850 {
851 int ret = 0;
852 uint32_t sub;
853
854 debug("%s: chunk: pid %d xfer_len %u pkts %u\n", __func__,
855 *pid, xfer_len, num_packets);
856
857 writel((xfer_len << DWC2_HCTSIZ_XFERSIZE_OFFSET) |
858 (num_packets << DWC2_HCTSIZ_PKTCNT_OFFSET) |
859 (*pid << DWC2_HCTSIZ_PID_OFFSET),
860 &hc_regs->hctsiz);
861
862 if (xfer_len) {
863 if (in) {
864 invalidate_dcache_range(
865 (uintptr_t)aligned_buffer,
866 (uintptr_t)aligned_buffer +
867 roundup(xfer_len, ARCH_DMA_MINALIGN));
868 } else {
869 memcpy(aligned_buffer, buffer, xfer_len);
870 flush_dcache_range(
871 (uintptr_t)aligned_buffer,
872 (uintptr_t)aligned_buffer +
873 roundup(xfer_len, ARCH_DMA_MINALIGN));
874 }
875 }
876
877 writel(phys_to_bus((unsigned long)aligned_buffer), &hc_regs->hcdma);
878
879 /* Clear old interrupt conditions for this host channel. */
880 writel(0x3fff, &hc_regs->hcint);
881
882 /* Set host channel enable after all other setup is complete. */
883 clrsetbits_le32(&hc_regs->hcchar, DWC2_HCCHAR_MULTICNT_MASK |
884 DWC2_HCCHAR_CHEN | DWC2_HCCHAR_CHDIS |
885 DWC2_HCCHAR_ODDFRM,
886 (1 << DWC2_HCCHAR_MULTICNT_OFFSET) |
887 (odd_frame << DWC2_HCCHAR_ODDFRM_OFFSET) |
888 DWC2_HCCHAR_CHEN);
889
890 ret = wait_for_chhltd(hc_regs, &sub, pid);
891 if (ret < 0)
892 return ret;
893
894 if (in) {
895 xfer_len -= sub;
896
897 invalidate_dcache_range((unsigned long)aligned_buffer,
898 (unsigned long)aligned_buffer +
899 roundup(xfer_len, ARCH_DMA_MINALIGN));
900
901 memcpy(buffer, aligned_buffer, xfer_len);
902 }
903 *actual_len = xfer_len;
904
905 return ret;
906 }
907
chunk_msg(struct dwc2_priv * priv,struct usb_device * dev,unsigned long pipe,u8 * pid,int in,void * buffer,int len)908 int chunk_msg(struct dwc2_priv *priv, struct usb_device *dev,
909 unsigned long pipe, u8 *pid, int in, void *buffer, int len)
910 {
911 struct dwc2_core_regs *regs = priv->regs;
912 struct dwc2_hc_regs *hc_regs = ®s->hc_regs[DWC2_HC_CHANNEL];
913 struct dwc2_host_regs *host_regs = ®s->host_regs;
914 int devnum = usb_pipedevice(pipe);
915 int ep = usb_pipeendpoint(pipe);
916 int max = usb_maxpacket(dev, pipe);
917 int eptype = dwc2_eptype[usb_pipetype(pipe)];
918 int done = 0;
919 int ret = 0;
920 int do_split = 0;
921 int complete_split = 0;
922 uint32_t xfer_len;
923 uint32_t num_packets;
924 int stop_transfer = 0;
925 uint32_t max_xfer_len;
926 int ssplit_frame_num = 0;
927
928 debug("%s: msg: pipe %lx pid %d in %d len %d\n", __func__, pipe, *pid,
929 in, len);
930
931 max_xfer_len = CONFIG_DWC2_MAX_PACKET_COUNT * max;
932 if (max_xfer_len > CONFIG_DWC2_MAX_TRANSFER_SIZE)
933 max_xfer_len = CONFIG_DWC2_MAX_TRANSFER_SIZE;
934 if (max_xfer_len > DWC2_DATA_BUF_SIZE)
935 max_xfer_len = DWC2_DATA_BUF_SIZE;
936
937 /* Make sure that max_xfer_len is a multiple of max packet size. */
938 num_packets = max_xfer_len / max;
939 max_xfer_len = num_packets * max;
940
941 /* Initialize channel */
942 dwc_otg_hc_init(regs, DWC2_HC_CHANNEL, dev, devnum, ep, in,
943 eptype, max);
944
945 /* Check if the target is a FS/LS device behind a HS hub */
946 if (dev->speed != USB_SPEED_HIGH) {
947 uint8_t hub_addr;
948 uint8_t hub_port;
949 uint32_t hprt0 = readl(®s->hprt0);
950 if ((hprt0 & DWC2_HPRT0_PRTSPD_MASK) ==
951 DWC2_HPRT0_PRTSPD_HIGH) {
952 usb_find_usb2_hub_address_port(dev, &hub_addr,
953 &hub_port);
954 dwc_otg_hc_init_split(hc_regs, hub_addr, hub_port);
955
956 do_split = 1;
957 num_packets = 1;
958 max_xfer_len = max;
959 }
960 }
961
962 do {
963 int actual_len = 0;
964 uint32_t hcint;
965 int odd_frame = 0;
966 xfer_len = len - done;
967
968 if (xfer_len > max_xfer_len)
969 xfer_len = max_xfer_len;
970 else if (xfer_len > max)
971 num_packets = (xfer_len + max - 1) / max;
972 else
973 num_packets = 1;
974
975 if (complete_split)
976 setbits_le32(&hc_regs->hcsplt, DWC2_HCSPLT_COMPSPLT);
977 else if (do_split)
978 clrbits_le32(&hc_regs->hcsplt, DWC2_HCSPLT_COMPSPLT);
979
980 if (eptype == DWC2_HCCHAR_EPTYPE_INTR) {
981 int uframe_num = readl(&host_regs->hfnum);
982 if (!(uframe_num & 0x1))
983 odd_frame = 1;
984 }
985
986 ret = transfer_chunk(hc_regs, priv->aligned_buffer, pid,
987 in, (char *)buffer + done, num_packets,
988 xfer_len, &actual_len, odd_frame);
989
990 hcint = readl(&hc_regs->hcint);
991 if (complete_split) {
992 stop_transfer = 0;
993 if (hcint & DWC2_HCINT_NYET) {
994 ret = 0;
995 int frame_num = DWC2_HFNUM_MAX_FRNUM &
996 readl(&host_regs->hfnum);
997 if (((frame_num - ssplit_frame_num) &
998 DWC2_HFNUM_MAX_FRNUM) > 4)
999 ret = -EAGAIN;
1000 } else
1001 complete_split = 0;
1002 } else if (do_split) {
1003 if (hcint & DWC2_HCINT_ACK) {
1004 ssplit_frame_num = DWC2_HFNUM_MAX_FRNUM &
1005 readl(&host_regs->hfnum);
1006 ret = 0;
1007 complete_split = 1;
1008 }
1009 }
1010
1011 if (ret)
1012 break;
1013
1014 if (actual_len < xfer_len)
1015 stop_transfer = 1;
1016
1017 done += actual_len;
1018
1019 /* Transactions are done when when either all data is transferred or
1020 * there is a short transfer. In case of a SPLIT make sure the CSPLIT
1021 * is executed.
1022 */
1023 } while (((done < len) && !stop_transfer) || complete_split);
1024
1025 writel(0, &hc_regs->hcintmsk);
1026 writel(0xFFFFFFFF, &hc_regs->hcint);
1027
1028 dev->status = 0;
1029 dev->act_len = done;
1030
1031 return ret;
1032 }
1033
1034 /* U-Boot USB transmission interface */
_submit_bulk_msg(struct dwc2_priv * priv,struct usb_device * dev,unsigned long pipe,void * buffer,int len)1035 int _submit_bulk_msg(struct dwc2_priv *priv, struct usb_device *dev,
1036 unsigned long pipe, void *buffer, int len)
1037 {
1038 int devnum = usb_pipedevice(pipe);
1039 int ep = usb_pipeendpoint(pipe);
1040 u8* pid;
1041
1042 if ((devnum >= MAX_DEVICE) || (devnum == priv->root_hub_devnum)) {
1043 dev->status = 0;
1044 return -EINVAL;
1045 }
1046
1047 if (usb_pipein(pipe))
1048 pid = &priv->in_data_toggle[devnum][ep];
1049 else
1050 pid = &priv->out_data_toggle[devnum][ep];
1051
1052 return chunk_msg(priv, dev, pipe, pid, usb_pipein(pipe), buffer, len);
1053 }
1054
_submit_control_msg(struct dwc2_priv * priv,struct usb_device * dev,unsigned long pipe,void * buffer,int len,struct devrequest * setup)1055 static int _submit_control_msg(struct dwc2_priv *priv, struct usb_device *dev,
1056 unsigned long pipe, void *buffer, int len,
1057 struct devrequest *setup)
1058 {
1059 int devnum = usb_pipedevice(pipe);
1060 int ret, act_len;
1061 u8 pid;
1062 /* For CONTROL endpoint pid should start with DATA1 */
1063 int status_direction;
1064
1065 if (devnum == priv->root_hub_devnum) {
1066 dev->status = 0;
1067 dev->speed = USB_SPEED_HIGH;
1068 return dwc_otg_submit_rh_msg(priv, dev, pipe, buffer, len,
1069 setup);
1070 }
1071
1072 /* SETUP stage */
1073 pid = DWC2_HC_PID_SETUP;
1074 do {
1075 ret = chunk_msg(priv, dev, pipe, &pid, 0, setup, 8);
1076 } while (ret == -EAGAIN);
1077 if (ret)
1078 return ret;
1079
1080 /* DATA stage */
1081 act_len = 0;
1082 if (buffer) {
1083 pid = DWC2_HC_PID_DATA1;
1084 do {
1085 ret = chunk_msg(priv, dev, pipe, &pid, usb_pipein(pipe),
1086 buffer, len);
1087 act_len += dev->act_len;
1088 buffer += dev->act_len;
1089 len -= dev->act_len;
1090 } while (ret == -EAGAIN);
1091 if (ret)
1092 return ret;
1093 status_direction = usb_pipeout(pipe);
1094 } else {
1095 /* No-data CONTROL always ends with an IN transaction */
1096 status_direction = 1;
1097 }
1098
1099 /* STATUS stage */
1100 pid = DWC2_HC_PID_DATA1;
1101 do {
1102 ret = chunk_msg(priv, dev, pipe, &pid, status_direction,
1103 priv->status_buffer, 0);
1104 } while (ret == -EAGAIN);
1105 if (ret)
1106 return ret;
1107
1108 dev->act_len = act_len;
1109
1110 return 0;
1111 }
1112
_submit_int_msg(struct dwc2_priv * priv,struct usb_device * dev,unsigned long pipe,void * buffer,int len,int interval,bool nonblock)1113 int _submit_int_msg(struct dwc2_priv *priv, struct usb_device *dev,
1114 unsigned long pipe, void *buffer, int len, int interval,
1115 bool nonblock)
1116 {
1117 unsigned long timeout;
1118 int ret;
1119
1120 /* FIXME: what is interval? */
1121
1122 timeout = get_timer(0) + USB_TIMEOUT_MS(pipe);
1123 for (;;) {
1124 if (get_timer(0) > timeout) {
1125 dev_err(dev, "Timeout poll on interrupt endpoint\n");
1126 return -ETIMEDOUT;
1127 }
1128 ret = _submit_bulk_msg(priv, dev, pipe, buffer, len);
1129 if ((ret != -EAGAIN) || nonblock)
1130 return ret;
1131 }
1132 }
1133
dwc2_reset(struct udevice * dev)1134 static int dwc2_reset(struct udevice *dev)
1135 {
1136 int ret;
1137 struct dwc2_priv *priv = dev_get_priv(dev);
1138
1139 ret = reset_get_bulk(dev, &priv->resets);
1140 if (ret) {
1141 dev_warn(dev, "Can't get reset: %d\n", ret);
1142 /* Return 0 if error due to !CONFIG_DM_RESET and reset
1143 * DT property is not present.
1144 */
1145 if (ret == -ENOENT || ret == -ENOTSUPP)
1146 return 0;
1147 else
1148 return ret;
1149 }
1150
1151 ret = reset_deassert_bulk(&priv->resets);
1152 if (ret) {
1153 reset_release_bulk(&priv->resets);
1154 dev_err(dev, "Failed to reset: %d\n", ret);
1155 return ret;
1156 }
1157
1158 return 0;
1159 }
1160
dwc2_init_common(struct udevice * dev,struct dwc2_priv * priv)1161 static int dwc2_init_common(struct udevice *dev, struct dwc2_priv *priv)
1162 {
1163 struct dwc2_core_regs *regs = priv->regs;
1164 uint32_t snpsid;
1165 int i, j;
1166 int ret;
1167
1168 ret = dwc2_reset(dev);
1169 if (ret)
1170 return ret;
1171
1172 snpsid = readl(®s->gsnpsid);
1173 dev_info(dev, "Core Release: %x.%03x\n",
1174 snpsid >> 12 & 0xf, snpsid & 0xfff);
1175
1176 if ((snpsid & DWC2_SNPSID_DEVID_MASK) != DWC2_SNPSID_DEVID_VER_2xx &&
1177 (snpsid & DWC2_SNPSID_DEVID_MASK) != DWC2_SNPSID_DEVID_VER_3xx) {
1178 dev_info(dev, "SNPSID invalid (not DWC2 OTG device): %08x\n",
1179 snpsid);
1180 return -ENODEV;
1181 }
1182
1183 #ifdef CONFIG_DWC2_PHY_ULPI_EXT_VBUS
1184 priv->ext_vbus = 1;
1185 #else
1186 priv->ext_vbus = 0;
1187 #endif
1188
1189 dwc_otg_core_init(priv);
1190 dwc_otg_core_host_init(dev, regs);
1191
1192 clrsetbits_le32(®s->hprt0, DWC2_HPRT0_PRTENA |
1193 DWC2_HPRT0_PRTCONNDET | DWC2_HPRT0_PRTENCHNG |
1194 DWC2_HPRT0_PRTOVRCURRCHNG,
1195 DWC2_HPRT0_PRTRST);
1196 mdelay(50);
1197 clrbits_le32(®s->hprt0, DWC2_HPRT0_PRTENA | DWC2_HPRT0_PRTCONNDET |
1198 DWC2_HPRT0_PRTENCHNG | DWC2_HPRT0_PRTOVRCURRCHNG |
1199 DWC2_HPRT0_PRTRST);
1200
1201 for (i = 0; i < MAX_DEVICE; i++) {
1202 for (j = 0; j < MAX_ENDPOINT; j++) {
1203 priv->in_data_toggle[i][j] = DWC2_HC_PID_DATA0;
1204 priv->out_data_toggle[i][j] = DWC2_HC_PID_DATA0;
1205 }
1206 }
1207
1208 /*
1209 * Add a 1 second delay here. This gives the host controller
1210 * a bit time before the comminucation with the USB devices
1211 * is started (the bus is scanned) and fixes the USB detection
1212 * problems with some problematic USB keys.
1213 */
1214 if (readl(®s->gintsts) & DWC2_GINTSTS_CURMODE_HOST)
1215 mdelay(1000);
1216
1217 return 0;
1218 }
1219
dwc2_uninit_common(struct dwc2_core_regs * regs)1220 static void dwc2_uninit_common(struct dwc2_core_regs *regs)
1221 {
1222 /* Put everything in reset. */
1223 clrsetbits_le32(®s->hprt0, DWC2_HPRT0_PRTENA |
1224 DWC2_HPRT0_PRTCONNDET | DWC2_HPRT0_PRTENCHNG |
1225 DWC2_HPRT0_PRTOVRCURRCHNG,
1226 DWC2_HPRT0_PRTRST);
1227 }
1228
1229 #if !CONFIG_IS_ENABLED(DM_USB)
submit_control_msg(struct usb_device * dev,unsigned long pipe,void * buffer,int len,struct devrequest * setup)1230 int submit_control_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
1231 int len, struct devrequest *setup)
1232 {
1233 return _submit_control_msg(&local, dev, pipe, buffer, len, setup);
1234 }
1235
submit_bulk_msg(struct usb_device * dev,unsigned long pipe,void * buffer,int len)1236 int submit_bulk_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
1237 int len)
1238 {
1239 return _submit_bulk_msg(&local, dev, pipe, buffer, len);
1240 }
1241
submit_int_msg(struct usb_device * dev,unsigned long pipe,void * buffer,int len,int interval,bool nonblock)1242 int submit_int_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
1243 int len, int interval, bool nonblock)
1244 {
1245 return _submit_int_msg(&local, dev, pipe, buffer, len, interval,
1246 nonblock);
1247 }
1248
1249 /* U-Boot USB control interface */
usb_lowlevel_init(int index,enum usb_init_type init,void ** controller)1250 int usb_lowlevel_init(int index, enum usb_init_type init, void **controller)
1251 {
1252 struct dwc2_priv *priv = &local;
1253
1254 memset(priv, '\0', sizeof(*priv));
1255 priv->root_hub_devnum = 0;
1256 priv->regs = (struct dwc2_core_regs *)CONFIG_USB_DWC2_REG_ADDR;
1257 priv->aligned_buffer = aligned_buffer_addr;
1258 priv->status_buffer = status_buffer_addr;
1259
1260 /* board-dependant init */
1261 if (board_usb_init(index, USB_INIT_HOST))
1262 return -1;
1263
1264 return dwc2_init_common(NULL, priv);
1265 }
1266
usb_lowlevel_stop(int index)1267 int usb_lowlevel_stop(int index)
1268 {
1269 dwc2_uninit_common(local.regs);
1270
1271 return 0;
1272 }
1273 #endif
1274
1275 #if CONFIG_IS_ENABLED(DM_USB)
dwc2_submit_control_msg(struct udevice * dev,struct usb_device * udev,unsigned long pipe,void * buffer,int length,struct devrequest * setup)1276 static int dwc2_submit_control_msg(struct udevice *dev, struct usb_device *udev,
1277 unsigned long pipe, void *buffer, int length,
1278 struct devrequest *setup)
1279 {
1280 struct dwc2_priv *priv = dev_get_priv(dev);
1281
1282 debug("%s: dev='%s', udev=%p, udev->dev='%s', portnr=%d\n", __func__,
1283 dev->name, udev, udev->dev->name, udev->portnr);
1284
1285 return _submit_control_msg(priv, udev, pipe, buffer, length, setup);
1286 }
1287
dwc2_submit_bulk_msg(struct udevice * dev,struct usb_device * udev,unsigned long pipe,void * buffer,int length)1288 static int dwc2_submit_bulk_msg(struct udevice *dev, struct usb_device *udev,
1289 unsigned long pipe, void *buffer, int length)
1290 {
1291 struct dwc2_priv *priv = dev_get_priv(dev);
1292
1293 debug("%s: dev='%s', udev=%p\n", __func__, dev->name, udev);
1294
1295 return _submit_bulk_msg(priv, udev, pipe, buffer, length);
1296 }
1297
dwc2_submit_int_msg(struct udevice * dev,struct usb_device * udev,unsigned long pipe,void * buffer,int length,int interval,bool nonblock)1298 static int dwc2_submit_int_msg(struct udevice *dev, struct usb_device *udev,
1299 unsigned long pipe, void *buffer, int length,
1300 int interval, bool nonblock)
1301 {
1302 struct dwc2_priv *priv = dev_get_priv(dev);
1303
1304 debug("%s: dev='%s', udev=%p\n", __func__, dev->name, udev);
1305
1306 return _submit_int_msg(priv, udev, pipe, buffer, length, interval,
1307 nonblock);
1308 }
1309
dwc2_usb_ofdata_to_platdata(struct udevice * dev)1310 static int dwc2_usb_ofdata_to_platdata(struct udevice *dev)
1311 {
1312 struct dwc2_priv *priv = dev_get_priv(dev);
1313 fdt_addr_t addr;
1314
1315 addr = dev_read_addr(dev);
1316 if (addr == FDT_ADDR_T_NONE)
1317 return -EINVAL;
1318 priv->regs = (struct dwc2_core_regs *)addr;
1319
1320 priv->oc_disable = dev_read_bool(dev, "disable-over-current");
1321 priv->hnp_srp_disable = dev_read_bool(dev, "hnp-srp-disable");
1322
1323 return 0;
1324 }
1325
dwc2_usb_probe(struct udevice * dev)1326 static int dwc2_usb_probe(struct udevice *dev)
1327 {
1328 struct dwc2_priv *priv = dev_get_priv(dev);
1329 struct usb_bus_priv *bus_priv = dev_get_uclass_priv(dev);
1330
1331 bus_priv->desc_before_addr = true;
1332
1333 #ifdef CONFIG_ARCH_ROCKCHIP
1334 priv->hnp_srp_disable = true;
1335 #endif
1336
1337 return dwc2_init_common(dev, priv);
1338 }
1339
dwc2_usb_remove(struct udevice * dev)1340 static int dwc2_usb_remove(struct udevice *dev)
1341 {
1342 struct dwc2_priv *priv = dev_get_priv(dev);
1343 int ret;
1344
1345 ret = dwc_vbus_supply_exit(dev);
1346 if (ret)
1347 return ret;
1348
1349 dwc2_uninit_common(priv->regs);
1350
1351 reset_release_bulk(&priv->resets);
1352
1353 return 0;
1354 }
1355
1356 struct dm_usb_ops dwc2_usb_ops = {
1357 .control = dwc2_submit_control_msg,
1358 .bulk = dwc2_submit_bulk_msg,
1359 .interrupt = dwc2_submit_int_msg,
1360 };
1361
1362 static const struct udevice_id dwc2_usb_ids[] = {
1363 { .compatible = "brcm,bcm2835-usb" },
1364 { .compatible = "brcm,bcm2708-usb" },
1365 { .compatible = "snps,dwc2" },
1366 { }
1367 };
1368
1369 U_BOOT_DRIVER(usb_dwc2) = {
1370 .name = "dwc2_usb",
1371 .id = UCLASS_USB,
1372 .of_match = dwc2_usb_ids,
1373 .ofdata_to_platdata = dwc2_usb_ofdata_to_platdata,
1374 .probe = dwc2_usb_probe,
1375 .remove = dwc2_usb_remove,
1376 .ops = &dwc2_usb_ops,
1377 .priv_auto_alloc_size = sizeof(struct dwc2_priv),
1378 .flags = DM_FLAG_ALLOC_PRIV_DMA,
1379 };
1380 #endif
1381