1 /* linux/arch/arm/plat-s3c/include/plat/regs-otg.h 2 * 3 * Copyright (C) 2004 Herbert Poetzl <herbert@13thfloor.at> 4 * 5 * Registers remapping: 6 * Lukasz Majewski <l.majewski@samsumg.com> 7 * 8 * SPDX-License-Identifier: GPL-2.0+ 9 */ 10 11 #ifndef __ASM_ARCH_REGS_USB_OTG_HS_H 12 #define __ASM_ARCH_REGS_USB_OTG_HS_H 13 14 /* USB2.0 OTG Controller register */ 15 struct dwc2_usbotg_phy { 16 u32 phypwr; 17 u32 phyclk; 18 u32 rstcon; 19 }; 20 21 /* Device Logical IN Endpoint-Specific Registers */ 22 struct dwc2_dev_in_endp { 23 u32 diepctl; 24 u8 res1[4]; 25 u32 diepint; 26 u8 res2[4]; 27 u32 dieptsiz; 28 u32 diepdma; 29 u8 res3[4]; 30 u32 diepdmab; 31 }; 32 33 /* Device Logical OUT Endpoint-Specific Registers */ 34 struct dwc2_dev_out_endp { 35 u32 doepctl; 36 u8 res1[4]; 37 u32 doepint; 38 u8 res2[4]; 39 u32 doeptsiz; 40 u32 doepdma; 41 u8 res3[4]; 42 u32 doepdmab; 43 }; 44 45 struct ep_fifo { 46 u32 fifo; 47 u8 res[4092]; 48 }; 49 50 /* USB2.0 OTG Controller register */ 51 struct dwc2_usbotg_reg { 52 /* Core Global Registers */ 53 u32 gotgctl; /* OTG Control & Status */ 54 u32 gotgint; /* OTG Interrupt */ 55 u32 gahbcfg; /* Core AHB Configuration */ 56 u32 gusbcfg; /* Core USB Configuration */ 57 u32 grstctl; /* Core Reset */ 58 u32 gintsts; /* Core Interrupt */ 59 u32 gintmsk; /* Core Interrupt Mask */ 60 u32 grxstsr; /* Receive Status Debug Read/Status Read */ 61 u32 grxstsp; /* Receive Status Debug Pop/Status Pop */ 62 u32 grxfsiz; /* Receive FIFO Size */ 63 u32 gnptxfsiz; /* Non-Periodic Transmit FIFO Size */ 64 u8 res0[12]; 65 u32 ggpio; /* 0x038 */ 66 u8 res1[20]; 67 u32 ghwcfg4; /* User HW Config4 */ 68 u8 res2[176]; 69 u32 dieptxf[15]; /* Device Periodic Transmit FIFO size register */ 70 u8 res3[1728]; 71 /* Device Configuration */ 72 u32 dcfg; /* Device Configuration Register */ 73 u32 dctl; /* Device Control */ 74 u32 dsts; /* Device Status */ 75 u8 res4[4]; 76 u32 diepmsk; /* Device IN Endpoint Common Interrupt Mask */ 77 u32 doepmsk; /* Device OUT Endpoint Common Interrupt Mask */ 78 u32 daint; /* Device All Endpoints Interrupt */ 79 u32 daintmsk; /* Device All Endpoints Interrupt Mask */ 80 u8 res5[224]; 81 struct dwc2_dev_in_endp in_endp[16]; 82 struct dwc2_dev_out_endp out_endp[16]; 83 u8 res6[768]; 84 struct ep_fifo ep[16]; 85 }; 86 87 /*===================================================================== */ 88 /*definitions related to CSR setting */ 89 90 /* DWC2_UDC_OTG_GOTGCTL */ 91 #define B_SESSION_VALID BIT(19) 92 #define A_SESSION_VALID BIT(18) 93 #define B_VALOVAL BIT(7) 94 #define B_VALOEN BIT(6) 95 #define A_VALOVAL BIT(5) 96 #define A_VALOEN BIT(4) 97 98 /* DWC2_UDC_OTG_GOTINT */ 99 #define GOTGINT_SES_END_DET (1<<2) 100 101 /* DWC2_UDC_OTG_GAHBCFG */ 102 #define PTXFE_HALF (0<<8) 103 #define PTXFE_ZERO (1<<8) 104 #define NPTXFE_HALF (0<<7) 105 #define NPTXFE_ZERO (1<<7) 106 #define MODE_SLAVE (0<<5) 107 #define MODE_DMA (1<<5) 108 #define BURST_SINGLE (0<<1) 109 #define BURST_INCR (1<<1) 110 #define BURST_INCR4 (3<<1) 111 #define BURST_INCR8 (5<<1) 112 #define BURST_INCR16 (7<<1) 113 #define GBL_INT_UNMASK (1<<0) 114 #define GBL_INT_MASK (0<<0) 115 116 /* DWC2_UDC_OTG_GRSTCTL */ 117 #define AHB_MASTER_IDLE (1u<<31) 118 #define CORE_SOFT_RESET (0x1<<0) 119 120 /* DWC2_UDC_OTG_GINTSTS/DWC2_UDC_OTG_GINTMSK core interrupt register */ 121 #define INT_RESUME (1u<<31) 122 #define INT_DISCONN (0x1<<29) 123 #define INT_CONN_ID_STS_CNG (0x1<<28) 124 #define INT_OUT_EP (0x1<<19) 125 #define INT_IN_EP (0x1<<18) 126 #define INT_ENUMDONE (0x1<<13) 127 #define INT_RESET (0x1<<12) 128 #define INT_SUSPEND (0x1<<11) 129 #define INT_EARLY_SUSPEND (0x1<<10) 130 #define INT_NP_TX_FIFO_EMPTY (0x1<<5) 131 #define INT_RX_FIFO_NOT_EMPTY (0x1<<4) 132 #define INT_SOF (0x1<<3) 133 #define INT_OTG (0x1<<2) 134 #define INT_DEV_MODE (0x0<<0) 135 #define INT_HOST_MODE (0x1<<1) 136 #define INT_GOUTNakEff (0x01<<7) 137 #define INT_GINNakEff (0x01<<6) 138 139 #define FULL_SPEED_CONTROL_PKT_SIZE 8 140 #define FULL_SPEED_BULK_PKT_SIZE 64 141 142 #define HIGH_SPEED_CONTROL_PKT_SIZE 64 143 #define HIGH_SPEED_BULK_PKT_SIZE 512 144 145 #define RX_FIFO_SIZE (1024) 146 #define NPTX_FIFO_SIZE (1024) 147 #define PTX_FIFO_SIZE (384) 148 149 #define DEPCTL_TXFNUM_0 (0x0<<22) 150 #define DEPCTL_TXFNUM_1 (0x1<<22) 151 #define DEPCTL_TXFNUM_2 (0x2<<22) 152 #define DEPCTL_TXFNUM_3 (0x3<<22) 153 #define DEPCTL_TXFNUM_4 (0x4<<22) 154 155 /* Enumeration speed */ 156 #define USB_HIGH_30_60MHZ (0x0<<1) 157 #define USB_FULL_30_60MHZ (0x1<<1) 158 #define USB_LOW_6MHZ (0x2<<1) 159 #define USB_FULL_48MHZ (0x3<<1) 160 161 /* DWC2_UDC_OTG_GRXSTSP STATUS */ 162 #define OUT_PKT_RECEIVED (0x2<<17) 163 #define OUT_TRANSFER_COMPLELTED (0x3<<17) 164 #define SETUP_TRANSACTION_COMPLETED (0x4<<17) 165 #define SETUP_PKT_RECEIVED (0x6<<17) 166 #define GLOBAL_OUT_NAK (0x1<<17) 167 168 /* DWC2_UDC_OTG_DCTL device control register */ 169 #define NORMAL_OPERATION (0x1<<0) 170 #define SOFT_DISCONNECT (0x1<<1) 171 172 /* DWC2_UDC_OTG_DAINT device all endpoint interrupt register */ 173 #define DAINT_OUT_BIT (16) 174 #define DAINT_MASK (0xFFFF) 175 176 /* DWC2_UDC_OTG_DIEPCTL0/DOEPCTL0 device 177 control IN/OUT endpoint 0 control register */ 178 #define DEPCTL_EPENA (0x1<<31) 179 #define DEPCTL_EPDIS (0x1<<30) 180 #define DEPCTL_SETD1PID (0x1<<29) 181 #define DEPCTL_SETD0PID (0x1<<28) 182 #define DEPCTL_SNAK (0x1<<27) 183 #define DEPCTL_CNAK (0x1<<26) 184 #define DEPCTL_STALL (0x1<<21) 185 #define DEPCTL_TYPE_BIT (18) 186 #define DEPCTL_TYPE_MASK (0x3<<18) 187 #define DEPCTL_CTRL_TYPE (0x0<<18) 188 #define DEPCTL_ISO_TYPE (0x1<<18) 189 #define DEPCTL_BULK_TYPE (0x2<<18) 190 #define DEPCTL_INTR_TYPE (0x3<<18) 191 #define DEPCTL_USBACTEP (0x1<<15) 192 #define DEPCTL_NEXT_EP_BIT (11) 193 #define DEPCTL_MPS_BIT (0) 194 #define DEPCTL_MPS_MASK (0x7FF) 195 196 #define DEPCTL0_MPS_64 (0x0<<0) 197 #define DEPCTL0_MPS_32 (0x1<<0) 198 #define DEPCTL0_MPS_16 (0x2<<0) 199 #define DEPCTL0_MPS_8 (0x3<<0) 200 #define DEPCTL_MPS_BULK_512 (512<<0) 201 #define DEPCTL_MPS_INT_MPS_16 (16<<0) 202 203 #define DIEPCTL0_NEXT_EP_BIT (11) 204 205 206 /* DWC2_UDC_OTG_DIEPMSK/DOEPMSK device IN/OUT endpoint 207 common interrupt mask register */ 208 /* DWC2_UDC_OTG_DIEPINTn/DOEPINTn device IN/OUT endpoint interrupt register */ 209 #define BACK2BACK_SETUP_RECEIVED (0x1<<6) 210 #define INTKNEPMIS (0x1<<5) 211 #define INTKN_TXFEMP (0x1<<4) 212 #define NON_ISO_IN_EP_TIMEOUT (0x1<<3) 213 #define CTRL_OUT_EP_SETUP_PHASE_DONE (0x1<<3) 214 #define AHB_ERROR (0x1<<2) 215 #define EPDISBLD (0x1<<1) 216 #define TRANSFER_DONE (0x1<<0) 217 218 #define USB_PHY_CTRL_EN0 (0x1 << 0) 219 220 /* OPHYPWR */ 221 #define PHY_0_SLEEP (0x1 << 5) 222 #define OTG_DISABLE_0 (0x1 << 4) 223 #define ANALOG_PWRDOWN (0x1 << 3) 224 #define FORCE_SUSPEND_0 (0x1 << 0) 225 226 /* URSTCON */ 227 #define HOST_SW_RST (0x1 << 4) 228 #define PHY_SW_RST1 (0x1 << 3) 229 #define PHYLNK_SW_RST (0x1 << 2) 230 #define LINK_SW_RST (0x1 << 1) 231 #define PHY_SW_RST0 (0x1 << 0) 232 233 /* OPHYCLK */ 234 #define COMMON_ON_N1 (0x1 << 7) 235 #define COMMON_ON_N0 (0x1 << 4) 236 #define ID_PULLUP0 (0x1 << 2) 237 #define CLK_SEL_24MHZ (0x3 << 0) 238 #define CLK_SEL_12MHZ (0x2 << 0) 239 #define CLK_SEL_48MHZ (0x0 << 0) 240 241 #define EXYNOS4X12_ID_PULLUP0 (0x01 << 3) 242 #define EXYNOS4X12_COMMON_ON_N0 (0x01 << 4) 243 #define EXYNOS4X12_CLK_SEL_12MHZ (0x02 << 0) 244 #define EXYNOS4X12_CLK_SEL_24MHZ (0x05 << 0) 245 246 /* Device Configuration Register DCFG */ 247 #define DEV_SPEED_HIGH_SPEED_20 (0x0 << 0) 248 #define DEV_SPEED_FULL_SPEED_20 (0x1 << 0) 249 #define DEV_SPEED_LOW_SPEED_11 (0x2 << 0) 250 #define DEV_SPEED_FULL_SPEED_11 (0x3 << 0) 251 #define EP_MISS_CNT(x) (x << 18) 252 #define DEVICE_ADDRESS(x) (x << 4) 253 #define DCFG_DEVADDR_MASK (0x7f << 4) 254 255 /* Core Reset Register (GRSTCTL) */ 256 #define TX_FIFO_FLUSH (0x1 << 5) 257 #define RX_FIFO_FLUSH (0x1 << 4) 258 #define TX_FIFO_NUMBER(x) (x << 6) 259 #define TX_FIFO_FLUSH_ALL TX_FIFO_NUMBER(0x10) 260 261 /* Masks definitions */ 262 #define GINTMSK_INIT (INT_OUT_EP | INT_IN_EP | INT_RESUME | INT_ENUMDONE\ 263 | INT_RESET | INT_SUSPEND | INT_OTG) 264 #define DOEPMSK_INIT (CTRL_OUT_EP_SETUP_PHASE_DONE | AHB_ERROR|TRANSFER_DONE) 265 #define DIEPMSK_INIT (NON_ISO_IN_EP_TIMEOUT|AHB_ERROR|TRANSFER_DONE) 266 #define GAHBCFG_INIT (PTXFE_HALF | NPTXFE_HALF | MODE_DMA | BURST_INCR4\ 267 | GBL_INT_UNMASK) 268 269 /* Device Endpoint X Transfer Size Register (DIEPTSIZX) */ 270 #define DIEPT_SIZ_PKT_CNT(x) (x << 19) 271 #define DIEPT_SIZ_XFER_SIZE(x) (x << 0) 272 273 /* Device OUT Endpoint X Transfer Size Register (DOEPTSIZX) */ 274 #define DOEPT_SIZ_PKT_CNT(x) (x << 19) 275 #define DOEPT_SIZ_XFER_SIZE(x) (x << 0) 276 #define DOEPT_SIZ_XFER_SIZE_MAX_EP0 (0x7F << 0) 277 #define DOEPT_SIZ_XFER_SIZE_MAX_EP (0x7FFFF << 0) 278 279 /* Device Endpoint-N Control Register (DIEPCTLn/DOEPCTLn) */ 280 #define DIEPCTL_TX_FIFO_NUM(x) (x << 22) 281 #define DIEPCTL_TX_FIFO_NUM_MASK (~DIEPCTL_TX_FIFO_NUM(0xF)) 282 283 /* Device ALL Endpoints Interrupt Register (DAINT) */ 284 #define DAINT_IN_EP_INT(x) (x << 0) 285 #define DAINT_OUT_EP_INT(x) (x << 16) 286 287 /* User HW Config4 */ 288 #define GHWCFG4_NUM_IN_EPS_MASK (0xf << 26) 289 #define GHWCFG4_NUM_IN_EPS_SHIFT 26 290 291 /* OTG general core configuration register (OTG_GCCFG:0x38) for STM32MP1 */ 292 #define GGPIO_STM32_OTG_GCCFG_VBDEN BIT(21) 293 #define GGPIO_STM32_OTG_GCCFG_IDEN BIT(22) 294 295 #endif 296