1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright (c) 2018 Fuzhou Rockchip Electronics Co., Ltd
4 */
5
6 #include <common.h>
7 #include <bitfield.h>
8 #include <thermal.h>
9 #include <dm.h>
10 #include <dm/pinctrl.h>
11 #include <div64.h>
12 #include <errno.h>
13 #include <syscon.h>
14 #include <asm/arch/clock.h>
15 #include <asm/arch/cpu.h>
16 #include <asm/arch/hardware.h>
17 #include <asm/io.h>
18 #include <dm/lists.h>
19 #include <clk.h>
20 #include <clk-uclass.h>
21 #include <reset.h>
22
23 DECLARE_GLOBAL_DATA_PTR;
24
25 /**
26 * If the temperature over a period of time High,
27 * the resulting TSHUT gave CRU module,let it reset the entire chip,
28 * or via GPIO give PMIC.
29 */
30 enum tshut_mode {
31 TSHUT_MODE_CRU = 0,
32 TSHUT_MODE_GPIO,
33 };
34
35 /**
36 * The system Temperature Sensors tshut(tshut) polarity
37 * the bit 8 is tshut polarity.
38 * 0: low active, 1: high active
39 */
40 enum tshut_polarity {
41 TSHUT_LOW_ACTIVE = 0,
42 TSHUT_HIGH_ACTIVE,
43 };
44
45 /**
46 * The conversion table has the adc value and temperature.
47 * ADC_DECREMENT: the adc value is of diminishing.(e.g. rk3288_code_table)
48 * ADC_INCREMENT: the adc value is incremental.(e.g. rk3368_code_table)
49 */
50 enum adc_sort_mode {
51 ADC_DECREMENT = 0,
52 ADC_INCREMENT,
53 };
54
55 #define SOC_MAX_SENSORS 7
56
57 #define TSADCV2_USER_CON 0x00
58 #define TSADCV2_AUTO_CON 0x04
59 #define TSADCV2_INT_EN 0x08
60 #define TSADCV2_INT_PD 0x0c
61 #define TSADCV3_AUTO_SRC_CON 0x0c
62 #define TSADCV3_HT_INT_EN 0x14
63 #define TSADCV3_HSHUT_GPIO_INT_EN 0x18
64 #define TSADCV3_HSHUT_CRU_INT_EN 0x1c
65 #define TSADCV3_INT_PD 0x24
66 #define TSADCV3_HSHUT_PD 0x28
67 #define TSADCV2_DATA(chn) (0x20 + (chn) * 0x04)
68 #define TSADCV2_COMP_INT(chn) (0x30 + (chn) * 0x04)
69 #define TSADCV2_COMP_SHUT(chn) (0x40 + (chn) * 0x04)
70 #define TSADCV3_DATA(chn) (0x2c + (chn) * 0x04)
71 #define TSADCV3_COMP_INT(chn) (0x6c + (chn) * 0x04)
72 #define TSADCV3_COMP_SHUT(chn) (0x10c + (chn) * 0x04)
73 #define TSADCV2_HIGHT_INT_DEBOUNCE 0x60
74 #define TSADCV2_HIGHT_TSHUT_DEBOUNCE 0x64
75 #define TSADCV3_HIGHT_INT_DEBOUNCE 0x14c
76 #define TSADCV3_HIGHT_TSHUT_DEBOUNCE 0x150
77 #define TSADCV2_AUTO_PERIOD 0x68
78 #define TSADCV2_AUTO_PERIOD_HT 0x6c
79 #define TSADCV3_AUTO_PERIOD 0x154
80 #define TSADCV3_AUTO_PERIOD_HT 0x158
81 #define TSADCV3_Q_MAX 0x210
82
83 #define TSADCV2_AUTO_EN BIT(0)
84 #define TSADCV2_AUTO_EN_MASK BIT(16)
85 #define TSADCV2_AUTO_SRC_EN(chn) BIT(4 + (chn))
86 #define TSADCV3_AUTO_SRC_EN(chn) BIT(chn)
87 #define TSADCV3_AUTO_SRC_EN_MASK(chn) BIT(16 + (chn))
88 #define TSADCV2_AUTO_TSHUT_POLARITY_HIGH BIT(8)
89 #define TSADCV2_AUTO_TSHUT_POLARITY_MASK BIT(24)
90
91 #define TSADCV3_AUTO_Q_SEL_EN BIT(1)
92 #define TSADCV3_AUTO_Q_SEL_EN_MASK BIT(17)
93
94 #define TSADCV2_INT_SRC_EN(chn) BIT(chn)
95 #define TSADCV2_INT_SRC_EN_MASK(chn) BIT(16 + (chn))
96 #define TSADCV2_SHUT_2GPIO_SRC_EN(chn) BIT(4 + (chn))
97 #define TSADCV2_SHUT_2CRU_SRC_EN(chn) BIT(8 + (chn))
98
99 #define TSADCV2_INT_PD_CLEAR_MASK ~BIT(8)
100 #define TSADCV3_INT_PD_CLEAR_MASK ~BIT(16)
101 #define TSADCV4_INT_PD_CLEAR_MASK 0xffffffff
102
103 #define TSADCV2_DATA_MASK 0xfff
104 #define TSADCV3_DATA_MASK 0x3ff
105 #define TSADCV4_DATA_MASK 0x1ff
106 #define TSADCV5_DATA_MASK 0x7ff
107
108 #define TSADCV2_HIGHT_INT_DEBOUNCE_COUNT 4
109 #define TSADCV2_HIGHT_TSHUT_DEBOUNCE_COUNT 4
110 #define TSADCV2_AUTO_PERIOD_TIME 250
111 #define TSADCV2_AUTO_PERIOD_HT_TIME 50
112 #define TSADCV3_AUTO_PERIOD_TIME 1875
113 #define TSADCV3_AUTO_PERIOD_HT_TIME 1875
114 #define TSADCV5_AUTO_PERIOD_TIME 1622 /* 2.5ms */
115 #define TSADCV5_AUTO_PERIOD_HT_TIME 1622 /* 2.5ms */
116 #define TSADCV6_AUTO_PERIOD_TIME 5000 /* 2.5ms */
117 #define TSADCV6_AUTO_PERIOD_HT_TIME 5000 /* 2.5ms */
118 #define TSADCV7_AUTO_PERIOD_TIME 3000 /* 2.5ms */
119 #define TSADCV7_AUTO_PERIOD_HT_TIME 3000 /* 2.5ms */
120 #define TSADCV3_Q_MAX_VAL 0x7ff /* 11bit 2047 */
121 #define TSADCV12_AUTO_PERIOD_TIME 3000 /* 2.5ms */
122 #define TSADCV12_AUTO_PERIOD_HT_TIME 3000 /* 2.5ms */
123 #define TSADCV12_Q_MAX_VAL 0xfff /* 12bit 4095 */
124 #define TSADCV9_Q_MAX 0x210
125 #define TSADCV9_Q_MAX_VAL (0xffff0400 << 0)
126
127 #define TSADCV2_USER_INTER_PD_SOC 0x340 /* 13 clocks */
128 #define TSADCV5_USER_INTER_PD_SOC 0xfc0 /* 97us, at least 90us */
129
130 #define GRF_SARADC_TESTBIT 0x0e644
131 #define GRF_TSADC_TESTBIT_L 0x0e648
132 #define GRF_TSADC_TESTBIT_H 0x0e64c
133
134 #define PX30_GRF_SOC_CON0 0x0400
135 #define PX30_GRF_SOC_CON2 0x0408
136
137 #define RK3562_GRF_TSADC_CON 0x0580
138
139 #define RK3568_GRF_TSADC_CON 0x0600
140 #define RK3528_GRF_TSADC_CON 0x40030
141 #define RK3568_GRF_TSADC_ANA_REG0 (0x10001 << 0)
142 #define RK3568_GRF_TSADC_ANA_REG1 (0x10001 << 1)
143 #define RK3568_GRF_TSADC_ANA_REG2 (0x10001 << 2)
144 #define RK3568_GRF_TSADC_TSEN (0x10001 << 8)
145
146 #define GRF_SARADC_TESTBIT_ON (0x10001 << 2)
147 #define GRF_TSADC_TESTBIT_H_ON (0x10001 << 2)
148 #define GRF_TSADC_VCM_EN_L (0x10001 << 7)
149 #define GRF_TSADC_VCM_EN_H (0x10001 << 7)
150
151 #define GRF_CON_TSADC_CH_INV (0x10001 << 1)
152 #define PX30S_TSADC_TDC_MODE (0x10001 << 4)
153
154 /* -40 to 125 is reliable, outside the range existed unreliability */
155 #define MIN_TEMP (-60000)
156 #define LOWEST_TEMP (-273000)
157 #define MAX_TEMP (180000)
158 #define MAX_ENV_TEMP (85000)
159
160 #define BASE (1024)
161 #define BASE_SHIFT (10)
162 #define START_DEBOUNCE_COUNT (100)
163 #define HIGHER_DEBOUNCE_TEMP (30000)
164 #define LOWER_DEBOUNCE_TEMP (15000)
165
166 /**
167 * struct tsadc_table - hold information about code and temp mapping
168 * @code: raw code from tsadc ip
169 * @temp: the mapping temperature
170 */
171
172 struct tsadc_table {
173 unsigned long code;
174 int temp;
175 };
176
177 struct chip_tsadc_table {
178 const struct tsadc_table *id;
179 unsigned int length;
180 u32 data_mask;
181 /* Tsadc is linear, using linear parameters */
182 int knum;
183 int bnum;
184 enum adc_sort_mode mode;
185 };
186
187 enum sensor_id {
188 SENSOR_CPU = 0,
189 SENSOR_GPU,
190 };
191
192 struct rockchip_tsadc_chip {
193 /* The sensor id of chip correspond to the ADC channel */
194 int chn_id[SOC_MAX_SENSORS];
195 int chn_num;
196 fdt_addr_t base;
197 fdt_addr_t grf;
198
199 /* The hardware-controlled tshut property */
200 int tshut_temp;
201 enum tshut_mode tshut_mode;
202 enum tshut_polarity tshut_polarity;
203
204 void (*tsadc_control)(struct udevice *dev, bool enable);
205 void (*tsadc_init)(struct udevice *dev);
206 int (*tsadc_get_temp)(struct udevice *dev, int chn,
207 int *temp);
208 void (*irq_ack)(struct udevice *dev);
209 void (*set_alarm_temp)(struct udevice *dev,
210 int chn, int temp);
211 void (*set_tshut_temp)(struct udevice *dev,
212 int chn, int temp);
213 void (*set_tshut_mode)(struct udevice *dev, int chn, enum tshut_mode m);
214 struct chip_tsadc_table table;
215 };
216
217 struct rockchip_thermal_priv {
218 void *base;
219 void *grf;
220 enum tshut_mode tshut_mode;
221 enum tshut_polarity tshut_polarity;
222 const struct rockchip_tsadc_chip *data;
223 };
224
225 static const struct tsadc_table rk1808_code_table[] = {
226 {0, MIN_TEMP},
227 {3423, MIN_TEMP},
228 {3455, -40000},
229 {3463, -35000},
230 {3471, -30000},
231 {3479, -25000},
232 {3487, -20000},
233 {3495, -15000},
234 {3503, -10000},
235 {3511, -5000},
236 {3519, 0},
237 {3527, 5000},
238 {3535, 10000},
239 {3543, 15000},
240 {3551, 20000},
241 {3559, 25000},
242 {3567, 30000},
243 {3576, 35000},
244 {3584, 40000},
245 {3592, 45000},
246 {3600, 50000},
247 {3609, 55000},
248 {3617, 60000},
249 {3625, 65000},
250 {3633, 70000},
251 {3642, 75000},
252 {3650, 80000},
253 {3659, 85000},
254 {3667, 90000},
255 {3675, 95000},
256 {3684, 100000},
257 {3692, 105000},
258 {3701, 110000},
259 {3709, 115000},
260 {3718, 120000},
261 {3726, 125000},
262 {3820, MAX_TEMP},
263 {TSADCV2_DATA_MASK, MAX_TEMP},
264 };
265
266 static const struct tsadc_table rk3228_code_table[] = {
267 {0, MIN_TEMP},
268 {568, MIN_TEMP},
269 {588, -40000},
270 {593, -35000},
271 {598, -30000},
272 {603, -25000},
273 {608, -20000},
274 {613, -15000},
275 {618, -10000},
276 {623, -5000},
277 {629, 0},
278 {634, 5000},
279 {639, 10000},
280 {644, 15000},
281 {649, 20000},
282 {654, 25000},
283 {660, 30000},
284 {665, 35000},
285 {670, 40000},
286 {675, 45000},
287 {681, 50000},
288 {686, 55000},
289 {691, 60000},
290 {696, 65000},
291 {702, 70000},
292 {707, 75000},
293 {712, 80000},
294 {717, 85000},
295 {723, 90000},
296 {728, 95000},
297 {733, 100000},
298 {738, 105000},
299 {744, 110000},
300 {749, 115000},
301 {754, 120000},
302 {760, 125000},
303 {821, MAX_TEMP},
304 {TSADCV2_DATA_MASK, MAX_TEMP},
305 };
306
307 static const struct tsadc_table rk3288_code_table[] = {
308 {TSADCV2_DATA_MASK, MIN_TEMP},
309 {3833, MIN_TEMP},
310 {3800, -40000},
311 {3792, -35000},
312 {3783, -30000},
313 {3774, -25000},
314 {3765, -20000},
315 {3756, -15000},
316 {3747, -10000},
317 {3737, -5000},
318 {3728, 0},
319 {3718, 5000},
320 {3708, 10000},
321 {3698, 15000},
322 {3688, 20000},
323 {3678, 25000},
324 {3667, 30000},
325 {3656, 35000},
326 {3645, 40000},
327 {3634, 45000},
328 {3623, 50000},
329 {3611, 55000},
330 {3600, 60000},
331 {3588, 65000},
332 {3575, 70000},
333 {3563, 75000},
334 {3550, 80000},
335 {3537, 85000},
336 {3524, 90000},
337 {3510, 95000},
338 {3496, 100000},
339 {3482, 105000},
340 {3467, 110000},
341 {3452, 115000},
342 {3437, 120000},
343 {3421, 125000},
344 {3350, 145000},
345 {3270, 165000},
346 {3195, MAX_TEMP},
347 {0, MAX_TEMP},
348 };
349
350 static const struct tsadc_table rk3328_code_table[] = {
351 {0, MIN_TEMP},
352 {261, MIN_TEMP},
353 {296, -40000},
354 {304, -35000},
355 {313, -30000},
356 {331, -20000},
357 {340, -15000},
358 {349, -10000},
359 {359, -5000},
360 {368, 0},
361 {378, 5000},
362 {388, 10000},
363 {398, 15000},
364 {408, 20000},
365 {418, 25000},
366 {429, 30000},
367 {440, 35000},
368 {451, 40000},
369 {462, 45000},
370 {473, 50000},
371 {485, 55000},
372 {496, 60000},
373 {508, 65000},
374 {521, 70000},
375 {533, 75000},
376 {546, 80000},
377 {559, 85000},
378 {572, 90000},
379 {586, 95000},
380 {600, 100000},
381 {614, 105000},
382 {629, 110000},
383 {644, 115000},
384 {659, 120000},
385 {675, 125000},
386 {745, 145000},
387 {825, 165000},
388 {900, MAX_TEMP},
389 {TSADCV2_DATA_MASK, MAX_TEMP},
390 };
391
392 static const struct tsadc_table rk3368_code_table[] = {
393 {0, MIN_TEMP},
394 {98, MIN_TEMP},
395 {106, -40000},
396 {108, -35000},
397 {110, -30000},
398 {112, -25000},
399 {114, -20000},
400 {116, -15000},
401 {118, -10000},
402 {120, -5000},
403 {122, 0},
404 {124, 5000},
405 {126, 10000},
406 {128, 15000},
407 {130, 20000},
408 {132, 25000},
409 {134, 30000},
410 {136, 35000},
411 {138, 40000},
412 {140, 45000},
413 {142, 50000},
414 {144, 55000},
415 {146, 60000},
416 {148, 65000},
417 {150, 70000},
418 {152, 75000},
419 {154, 80000},
420 {156, 85000},
421 {158, 90000},
422 {160, 95000},
423 {162, 100000},
424 {163, 105000},
425 {165, 110000},
426 {167, 115000},
427 {169, 120000},
428 {171, 125000},
429 {193, MAX_TEMP},
430 {TSADCV3_DATA_MASK, MAX_TEMP},
431 };
432
433 static const struct tsadc_table rk3399_code_table[] = {
434 {0, MIN_TEMP},
435 {368, MIN_TEMP},
436 {402, -40000},
437 {410, -35000},
438 {419, -30000},
439 {427, -25000},
440 {436, -20000},
441 {444, -15000},
442 {453, -10000},
443 {461, -5000},
444 {470, 0},
445 {478, 5000},
446 {487, 10000},
447 {496, 15000},
448 {504, 20000},
449 {513, 25000},
450 {521, 30000},
451 {530, 35000},
452 {538, 40000},
453 {547, 45000},
454 {555, 50000},
455 {564, 55000},
456 {573, 60000},
457 {581, 65000},
458 {590, 70000},
459 {599, 75000},
460 {607, 80000},
461 {616, 85000},
462 {624, 90000},
463 {633, 95000},
464 {642, 100000},
465 {650, 105000},
466 {659, 110000},
467 {668, 115000},
468 {677, 120000},
469 {685, 125000},
470 {782, MAX_TEMP},
471 {TSADCV3_DATA_MASK, MAX_TEMP},
472 };
473
474 static const struct tsadc_table rk3528_code_table[] = {
475 {0, MIN_TEMP},
476 {1386, MIN_TEMP},
477 {1419, -40000},
478 {1427, -35000},
479 {1435, -30000},
480 {1443, -25000},
481 {1452, -20000},
482 {1460, -15000},
483 {1468, -10000},
484 {1477, -5000},
485 {1486, 0},
486 {1494, 5000},
487 {1502, 10000},
488 {1510, 15000},
489 {1519, 20000},
490 {1527, 25000},
491 {1535, 30000},
492 {1544, 35000},
493 {1552, 40000},
494 {1561, 45000},
495 {1569, 50000},
496 {1578, 55000},
497 {1586, 60000},
498 {1594, 65000},
499 {1603, 70000},
500 {1612, 75000},
501 {1620, 80000},
502 {1628, 85000},
503 {1637, 90000},
504 {1646, 95000},
505 {1654, 100000},
506 {1662, 105000},
507 {1671, 110000},
508 {1679, 115000},
509 {1688, 120000},
510 {1696, 125000},
511 {1790, MAX_TEMP},
512 {TSADCV5_DATA_MASK, MAX_TEMP},
513 };
514
515 static const struct tsadc_table rk3562_code_table[] = {
516 {0, MIN_TEMP},
517 {1385, MIN_TEMP},
518 {1419, -40000},
519 {1428, -35000},
520 {1436, -30000},
521 {1445, -25000},
522 {1453, -20000},
523 {1462, -15000},
524 {1470, -10000},
525 {1479, -5000},
526 {1487, 0},
527 {1496, 5000},
528 {1504, 10000},
529 {1512, 15000},
530 {1521, 20000},
531 {1529, 25000},
532 {1538, 30000},
533 {1546, 35000},
534 {1555, 40000},
535 {1563, 45000},
536 {1572, 50000},
537 {1580, 55000},
538 {1589, 60000},
539 {1598, 65000},
540 {1606, 70000},
541 {1615, 75000},
542 {1623, 80000},
543 {1632, 85000},
544 {1640, 90000},
545 {1648, 95000},
546 {1657, 100000},
547 {1666, 105000},
548 {1674, 110000},
549 {1682, 115000},
550 {1691, 120000},
551 {1699, 125000},
552 {1793, MAX_TEMP},
553 {TSADCV2_DATA_MASK, MAX_TEMP},
554 };
555
556 static const struct tsadc_table rk3568_code_table[] = {
557 {0, MIN_TEMP},
558 {1448, MIN_TEMP},
559 {1584, -40000},
560 {1620, -35000},
561 {1652, -30000},
562 {1688, -25000},
563 {1720, -20000},
564 {1756, -15000},
565 {1788, -10000},
566 {1824, -5000},
567 {1856, 0},
568 {1892, 5000},
569 {1924, 10000},
570 {1956, 15000},
571 {1992, 20000},
572 {2024, 25000},
573 {2060, 30000},
574 {2092, 35000},
575 {2128, 40000},
576 {2160, 45000},
577 {2196, 50000},
578 {2228, 55000},
579 {2264, 60000},
580 {2300, 65000},
581 {2332, 70000},
582 {2368, 75000},
583 {2400, 80000},
584 {2436, 85000},
585 {2468, 90000},
586 {2500, 95000},
587 {2536, 100000},
588 {2572, 105000},
589 {2604, 110000},
590 {2636, 115000},
591 {2672, 120000},
592 {2704, 125000},
593 {3076, MAX_TEMP},
594 {TSADCV2_DATA_MASK, MAX_TEMP},
595 };
596
597 static const struct tsadc_table rk3588_code_table[] = {
598 {0, MIN_TEMP},
599 {194, MIN_TEMP},
600 {215, -40000},
601 {285, 25000},
602 {350, 85000},
603 {395, 125000},
604 {455, MAX_TEMP},
605 {TSADCV4_DATA_MASK, MAX_TEMP},
606 };
607
608 /*
609 * Struct used for matching a device
610 */
611 struct of_device_id {
612 char compatible[32];
613 const void *data;
614 };
615
tsadc_code_to_temp(struct chip_tsadc_table * table,u32 code,int * temp)616 static int tsadc_code_to_temp(struct chip_tsadc_table *table, u32 code,
617 int *temp)
618 {
619 unsigned int low = 1;
620 unsigned int high = table->length - 1;
621 unsigned int mid = (low + high) / 2;
622 unsigned int num;
623 unsigned long denom;
624
625 if (table->knum) {
626 *temp = (((int)code - table->bnum) * 10000 / table->knum) * 100;
627 if (*temp < MIN_TEMP || *temp > MAX_TEMP)
628 return -EAGAIN;
629 return 0;
630 }
631
632 switch (table->mode) {
633 case ADC_DECREMENT:
634 code &= table->data_mask;
635 if (code < table->id[high].code)
636 return -EAGAIN; /* Incorrect reading */
637
638 while (low <= high) {
639 if (code >= table->id[mid].code &&
640 code < table->id[mid - 1].code)
641 break;
642 else if (code < table->id[mid].code)
643 low = mid + 1;
644 else
645 high = mid - 1;
646
647 mid = (low + high) / 2;
648 }
649 break;
650 case ADC_INCREMENT:
651 code &= table->data_mask;
652 if (code < table->id[low].code)
653 return -EAGAIN; /* Incorrect reading */
654
655 while (low <= high) {
656 if (code <= table->id[mid].code &&
657 code > table->id[mid - 1].code)
658 break;
659 else if (code > table->id[mid].code)
660 low = mid + 1;
661 else
662 high = mid - 1;
663
664 mid = (low + high) / 2;
665 }
666 break;
667 default:
668 printf("%s: Invalid the conversion table mode=%d\n",
669 __func__, table->mode);
670 return -EINVAL;
671 }
672
673 /*
674 * The 5C granularity provided by the table is too much. Let's
675 * assume that the relationship between sensor readings and
676 * temperature between 2 table entries is linear and interpolate
677 * to produce less granular result.
678 */
679 num = table->id[mid].temp - table->id[mid - 1].temp;
680 num *= abs(table->id[mid - 1].code - code);
681 denom = abs(table->id[mid - 1].code - table->id[mid].code);
682 *temp = table->id[mid - 1].temp + (num / denom);
683
684 return 0;
685 }
686
tsadc_temp_to_code_v2(struct chip_tsadc_table table,int temp)687 static u32 tsadc_temp_to_code_v2(struct chip_tsadc_table table,
688 int temp)
689 {
690 int high, low, mid;
691 unsigned long num;
692 unsigned int denom;
693 u32 error = table.data_mask;
694
695 if (table.knum)
696 return (((temp / 1000) * table.knum) / 1000 + table.bnum);
697
698 low = 0;
699 high = table.length - 1;
700 mid = (high + low) / 2;
701
702 /* Return mask code data when the temp is over table range */
703 if (temp < table.id[low].temp || temp > table.id[high].temp)
704 goto exit;
705
706 while (low <= high) {
707 if (temp == table.id[mid].temp)
708 return table.id[mid].code;
709 else if (temp < table.id[mid].temp)
710 high = mid - 1;
711 else
712 low = mid + 1;
713 mid = (low + high) / 2;
714 }
715
716 num = abs(table.id[mid + 1].code - table.id[mid].code);
717 num *= temp - table.id[mid].temp;
718 denom = table.id[mid + 1].temp - table.id[mid].temp;
719
720 switch (table.mode) {
721 case ADC_DECREMENT:
722 return table.id[mid].code - (num / denom);
723 case ADC_INCREMENT:
724 return table.id[mid].code + (num / denom);
725 default:
726 pr_err("%s: unknown table mode: %d\n", __func__, table.mode);
727 return error;
728 }
729
730 exit:
731 pr_err("%s: Invalid conversion table: code=%d, temperature=%d\n",
732 __func__, error, temp);
733
734 return error;
735 }
736
tsadc_irq_ack_v2(struct udevice * dev)737 static void tsadc_irq_ack_v2(struct udevice *dev)
738 {
739 struct rockchip_thermal_priv *priv = dev_get_priv(dev);
740 u32 val;
741
742 val = readl(priv->base + TSADCV2_INT_PD);
743 writel(val & TSADCV2_INT_PD_CLEAR_MASK, priv->base + TSADCV2_INT_PD);
744 }
745
tsadc_irq_ack_v3(struct udevice * dev)746 static void tsadc_irq_ack_v3(struct udevice *dev)
747 {
748 struct rockchip_thermal_priv *priv = dev_get_priv(dev);
749 u32 val;
750
751 val = readl(priv->base + TSADCV2_INT_PD);
752 writel(val & TSADCV3_INT_PD_CLEAR_MASK, priv->base + TSADCV2_INT_PD);
753 }
754
tsadc_irq_ack_v4(struct udevice * dev)755 static void tsadc_irq_ack_v4(struct udevice *dev)
756 {
757 struct rockchip_thermal_priv *priv = dev_get_priv(dev);
758 u32 val;
759
760 val = readl(priv->base + TSADCV3_INT_PD);
761 writel(val & TSADCV4_INT_PD_CLEAR_MASK, priv->base + TSADCV3_INT_PD);
762 val = readl(priv->base + TSADCV3_HSHUT_PD);
763 writel(val & TSADCV3_INT_PD_CLEAR_MASK, priv->base + TSADCV3_HSHUT_PD);
764 }
765
tsadc_control_v2(struct udevice * dev,bool enable)766 static void tsadc_control_v2(struct udevice *dev, bool enable)
767 {
768 struct rockchip_thermal_priv *priv = dev_get_priv(dev);
769 u32 val;
770
771 val = readl(priv->base + TSADCV2_AUTO_CON);
772 if (enable)
773 val |= TSADCV2_AUTO_EN;
774 else
775 val &= ~TSADCV2_AUTO_EN;
776
777 writel(val, priv->base + TSADCV2_AUTO_CON);
778 }
779
tsadc_control_v3(struct udevice * dev,bool enable)780 static void tsadc_control_v3(struct udevice *dev, bool enable)
781 {
782 struct rockchip_thermal_priv *priv = dev_get_priv(dev);
783 u32 val;
784
785 val = readl(priv->base + TSADCV2_AUTO_CON);
786 if (enable)
787 val |= TSADCV2_AUTO_EN | TSADCV3_AUTO_Q_SEL_EN;
788 else
789 val &= ~TSADCV2_AUTO_EN;
790
791 writel(val, priv->base + TSADCV2_AUTO_CON);
792 }
793
tsadc_control_v4(struct udevice * dev,bool enable)794 static void tsadc_control_v4(struct udevice *dev, bool enable)
795 {
796 struct rockchip_thermal_priv *priv = dev_get_priv(dev);
797 u32 val;
798
799 if (enable)
800 val = TSADCV2_AUTO_EN | TSADCV2_AUTO_EN_MASK;
801 else
802 val = TSADCV2_AUTO_EN_MASK;
803
804 writel(val, priv->base + TSADCV2_AUTO_CON);
805 }
806
tsadc_init_v2(struct udevice * dev)807 static void tsadc_init_v2(struct udevice *dev)
808 {
809 struct rockchip_thermal_priv *priv = dev_get_priv(dev);
810
811 writel(TSADCV2_AUTO_PERIOD_TIME,
812 priv->base + TSADCV2_AUTO_PERIOD);
813 writel(TSADCV2_HIGHT_INT_DEBOUNCE_COUNT,
814 priv->base + TSADCV2_HIGHT_INT_DEBOUNCE);
815 writel(TSADCV2_AUTO_PERIOD_HT_TIME,
816 priv->base + TSADCV2_AUTO_PERIOD_HT);
817 writel(TSADCV2_HIGHT_TSHUT_DEBOUNCE_COUNT,
818 priv->base + TSADCV2_HIGHT_TSHUT_DEBOUNCE);
819
820 if (priv->tshut_polarity == TSHUT_HIGH_ACTIVE)
821 writel(0U | TSADCV2_AUTO_TSHUT_POLARITY_HIGH,
822 priv->base + TSADCV2_AUTO_CON);
823 else
824 writel(0U & ~TSADCV2_AUTO_TSHUT_POLARITY_HIGH,
825 priv->base + TSADCV2_AUTO_CON);
826 }
827
tsadc_init_v3(struct udevice * dev)828 static void tsadc_init_v3(struct udevice *dev)
829 {
830 struct rockchip_thermal_priv *priv = dev_get_priv(dev);
831
832 if (!IS_ERR(priv->grf)) {
833 writel(GRF_TSADC_VCM_EN_L, priv->grf + GRF_TSADC_TESTBIT_L);
834 writel(GRF_TSADC_VCM_EN_H, priv->grf + GRF_TSADC_TESTBIT_H);
835
836 udelay(100);/* The spec note says at least 15 us */
837 writel(GRF_SARADC_TESTBIT_ON, priv->grf + GRF_SARADC_TESTBIT);
838 writel(GRF_TSADC_TESTBIT_H_ON, priv->grf + GRF_TSADC_TESTBIT_H);
839 udelay(200);/* The spec note says at least 90 us */
840 }
841 tsadc_init_v2(dev);
842 }
843
tsadc_init_v5(struct udevice * dev)844 static void __maybe_unused tsadc_init_v5(struct udevice *dev)
845 {
846 struct rockchip_thermal_priv *priv = dev_get_priv(dev);
847
848 /* Set interleave value to workround ic time sync issue */
849 writel(TSADCV2_USER_INTER_PD_SOC, priv->base +
850 TSADCV2_USER_CON);
851 tsadc_init_v2(dev);
852 }
853
tsadc_init_v4(struct udevice * dev)854 static void tsadc_init_v4(struct udevice *dev)
855 {
856 struct rockchip_thermal_priv *priv = dev_get_priv(dev);
857
858 tsadc_init_v2(dev);
859 if (!IS_ERR(priv->grf))
860 writel(GRF_CON_TSADC_CH_INV, priv->grf + PX30_GRF_SOC_CON2);
861 }
862
tsadc_init_v7(struct udevice * dev)863 static void tsadc_init_v7(struct udevice *dev)
864 {
865 struct rockchip_thermal_priv *priv = dev_get_priv(dev);
866
867 writel(TSADCV5_USER_INTER_PD_SOC,
868 priv->base + TSADCV2_USER_CON);
869 writel(TSADCV5_AUTO_PERIOD_TIME,
870 priv->base + TSADCV2_AUTO_PERIOD);
871 writel(TSADCV2_HIGHT_INT_DEBOUNCE_COUNT,
872 priv->base + TSADCV2_HIGHT_INT_DEBOUNCE);
873 writel(TSADCV5_AUTO_PERIOD_HT_TIME,
874 priv->base + TSADCV2_AUTO_PERIOD_HT);
875 writel(TSADCV2_HIGHT_TSHUT_DEBOUNCE_COUNT,
876 priv->base + TSADCV2_HIGHT_TSHUT_DEBOUNCE);
877
878 if (priv->tshut_polarity == TSHUT_HIGH_ACTIVE)
879 writel(0U | TSADCV2_AUTO_TSHUT_POLARITY_HIGH,
880 priv->base + TSADCV2_AUTO_CON);
881 else
882 writel(0U & ~TSADCV2_AUTO_TSHUT_POLARITY_HIGH,
883 priv->base + TSADCV2_AUTO_CON);
884
885 if (!IS_ERR(priv->grf)) {
886 writel(RK3568_GRF_TSADC_TSEN,
887 priv->grf + RK3568_GRF_TSADC_CON);
888 udelay(15);
889 writel(RK3568_GRF_TSADC_ANA_REG0,
890 priv->grf + RK3568_GRF_TSADC_CON);
891 writel(RK3568_GRF_TSADC_ANA_REG1,
892 priv->grf + RK3568_GRF_TSADC_CON);
893 writel(RK3568_GRF_TSADC_ANA_REG2,
894 priv->grf + RK3568_GRF_TSADC_CON);
895 udelay(200);
896 }
897 }
898
tsadc_init_v8(struct udevice * dev)899 static void tsadc_init_v8(struct udevice *dev)
900 {
901 struct rockchip_thermal_priv *priv = dev_get_priv(dev);
902
903 writel(TSADCV6_AUTO_PERIOD_TIME, priv->base + TSADCV3_AUTO_PERIOD);
904 writel(TSADCV6_AUTO_PERIOD_HT_TIME,
905 priv->base + TSADCV3_AUTO_PERIOD_HT);
906 writel(TSADCV2_HIGHT_INT_DEBOUNCE_COUNT,
907 priv->base + TSADCV3_HIGHT_INT_DEBOUNCE);
908 writel(TSADCV2_HIGHT_TSHUT_DEBOUNCE_COUNT,
909 priv->base + TSADCV3_HIGHT_TSHUT_DEBOUNCE);
910
911 if (priv->tshut_polarity == TSHUT_HIGH_ACTIVE)
912 writel(TSADCV2_AUTO_TSHUT_POLARITY_HIGH |
913 TSADCV2_AUTO_TSHUT_POLARITY_MASK,
914 priv->base + TSADCV2_AUTO_CON);
915 else
916 writel(TSADCV2_AUTO_TSHUT_POLARITY_MASK,
917 priv->base + TSADCV2_AUTO_CON);
918 };
919
tsadc_init_v9(struct udevice * dev)920 static void tsadc_init_v9(struct udevice *dev)
921 {
922 struct rockchip_thermal_priv *priv = dev_get_priv(dev);
923
924 tsadc_init_v2(dev);
925 if (!IS_ERR(priv->grf))
926 writel(PX30S_TSADC_TDC_MODE, priv->grf + PX30_GRF_SOC_CON0);
927 }
928
tsadc_init_v11(struct udevice * dev)929 static void tsadc_init_v11(struct udevice *dev)
930 {
931 struct rockchip_thermal_priv *priv = dev_get_priv(dev);
932
933 writel(TSADCV7_AUTO_PERIOD_TIME, priv->base + TSADCV3_AUTO_PERIOD);
934 writel(TSADCV7_AUTO_PERIOD_HT_TIME,
935 priv->base + TSADCV3_AUTO_PERIOD_HT);
936 writel(TSADCV2_HIGHT_INT_DEBOUNCE_COUNT,
937 priv->base + TSADCV3_HIGHT_INT_DEBOUNCE);
938 writel(TSADCV2_HIGHT_TSHUT_DEBOUNCE_COUNT,
939 priv->base + TSADCV3_HIGHT_TSHUT_DEBOUNCE);
940 writel(TSADCV3_Q_MAX_VAL, priv->base + TSADCV3_Q_MAX);
941 writel(TSADCV3_AUTO_Q_SEL_EN | TSADCV3_AUTO_Q_SEL_EN_MASK,
942 priv->base + TSADCV2_AUTO_CON);
943
944 if (priv->tshut_polarity == TSHUT_HIGH_ACTIVE)
945 writel(TSADCV2_AUTO_TSHUT_POLARITY_HIGH |
946 TSADCV2_AUTO_TSHUT_POLARITY_MASK,
947 priv->base + TSADCV2_AUTO_CON);
948 else
949 writel(TSADCV2_AUTO_TSHUT_POLARITY_MASK,
950 priv->base + TSADCV2_AUTO_CON);
951
952 if (!IS_ERR(priv->grf)) {
953 writel(RK3568_GRF_TSADC_TSEN,
954 priv->grf + RK3528_GRF_TSADC_CON);
955 udelay(15);
956 writel(RK3568_GRF_TSADC_ANA_REG0,
957 priv->grf + RK3528_GRF_TSADC_CON);
958 writel(RK3568_GRF_TSADC_ANA_REG1,
959 priv->grf + RK3528_GRF_TSADC_CON);
960 writel(RK3568_GRF_TSADC_ANA_REG2,
961 priv->grf + RK3528_GRF_TSADC_CON);
962 udelay(200);
963 }
964 }
965
tsadc_init_v12(struct udevice * dev)966 static void tsadc_init_v12(struct udevice *dev)
967 {
968 struct rockchip_thermal_priv *priv = dev_get_priv(dev);
969
970 writel(TSADCV12_AUTO_PERIOD_TIME,
971 priv->base + TSADCV3_AUTO_PERIOD);
972 writel(TSADCV12_AUTO_PERIOD_HT_TIME,
973 priv->base + TSADCV3_AUTO_PERIOD_HT);
974 writel(TSADCV2_HIGHT_INT_DEBOUNCE_COUNT,
975 priv->base + TSADCV3_HIGHT_INT_DEBOUNCE);
976 writel(TSADCV2_HIGHT_TSHUT_DEBOUNCE_COUNT,
977 priv->base + TSADCV3_HIGHT_TSHUT_DEBOUNCE);
978 writel(TSADCV12_Q_MAX_VAL,
979 priv->base + TSADCV9_Q_MAX);
980 writel(TSADCV3_AUTO_Q_SEL_EN | TSADCV3_AUTO_Q_SEL_EN_MASK,
981 priv->base + TSADCV2_AUTO_CON);
982 if (priv->tshut_polarity == TSHUT_HIGH_ACTIVE)
983 writel(TSADCV2_AUTO_TSHUT_POLARITY_HIGH |
984 TSADCV2_AUTO_TSHUT_POLARITY_MASK,
985 priv->base + TSADCV2_AUTO_CON);
986 else
987 writel(TSADCV2_AUTO_TSHUT_POLARITY_MASK,
988 priv->base + TSADCV2_AUTO_CON);
989
990 if (!IS_ERR(priv->grf)) {
991 writel(RK3568_GRF_TSADC_TSEN,
992 priv->grf + RK3562_GRF_TSADC_CON);
993 udelay(15);
994 writel(RK3568_GRF_TSADC_ANA_REG0,
995 priv->grf + RK3562_GRF_TSADC_CON);
996 writel(RK3568_GRF_TSADC_ANA_REG1,
997 priv->grf + RK3562_GRF_TSADC_CON);
998 writel(RK3568_GRF_TSADC_ANA_REG2,
999 priv->grf + RK3562_GRF_TSADC_CON);
1000 udelay(200);
1001 }
1002 }
1003
tsadc_get_temp_v2(struct udevice * dev,int chn,int * temp)1004 static int tsadc_get_temp_v2(struct udevice *dev,
1005 int chn, int *temp)
1006 {
1007 struct rockchip_thermal_priv *priv = dev_get_priv(dev);
1008 struct chip_tsadc_table table = priv->data->table;
1009 u32 val;
1010
1011 val = readl(priv->base + TSADCV2_DATA(chn));
1012
1013 return tsadc_code_to_temp(&table, val, temp);
1014 }
1015
predict_temp(int temp)1016 static int predict_temp(int temp)
1017 {
1018 /*
1019 * The deviation of prediction. the temperature will not change rapidly,
1020 * so this cov_q is small
1021 */
1022 int cov_q = 18;
1023 /*
1024 * The deviation of tsadc's reading, deviation of tsadc is very big when
1025 * abnormal temperature is get
1026 */
1027 int cov_r = 542;
1028
1029 int gain;
1030 int temp_mid;
1031 int temp_now;
1032 int prob_mid;
1033 int prob_now;
1034 static int temp_last = LOWEST_TEMP;
1035 static int prob_last = 160;
1036 static int bounding_cnt;
1037
1038 /*
1039 * init temp_last with a more suitable value, which mostly equals to
1040 * temp reading from tsadc, but not higher than MAX_ENV_TEMP. If the
1041 * temp is higher than MAX_ENV_TEMP, it is assumed to be abnormal
1042 * value and temp_last is adjusted to MAX_ENV_TEMP.
1043 */
1044 if (temp_last == LOWEST_TEMP)
1045 temp_last = min(temp, MAX_ENV_TEMP);
1046
1047 /*
1048 * Before START_DEBOUNCE_COUNT's samples of temperature, we consider
1049 * tsadc is stable, i.e. after that, the temperature may be not stable
1050 * and may have abnormal reading, so we set a bounding temperature. If
1051 * the reading from tsadc is too big, we set the delta temperature of
1052 * DEBOUNCE_TEMP/3 comparing to the last temperature.
1053 */
1054
1055 if (bounding_cnt++ > START_DEBOUNCE_COUNT) {
1056 bounding_cnt = START_DEBOUNCE_COUNT;
1057 if (temp - temp_last > HIGHER_DEBOUNCE_TEMP)
1058 temp = temp_last + HIGHER_DEBOUNCE_TEMP / 3;
1059 if (temp_last - temp > LOWER_DEBOUNCE_TEMP)
1060 temp = temp_last - LOWER_DEBOUNCE_TEMP / 3;
1061 }
1062
1063 temp_mid = temp_last;
1064
1065 /* calculate the probability of this time's prediction */
1066 prob_mid = prob_last + cov_q;
1067
1068 /* calculate the Kalman Gain */
1069 gain = (prob_mid * BASE) / (prob_mid + cov_r);
1070
1071 /* calculate the prediction of temperature */
1072 temp_now = (temp_mid * BASE + gain * (temp - temp_mid)) >> BASE_SHIFT;
1073
1074 /*
1075 * Base on this time's Kalman Gain, ajust our probability of prediction
1076 * for next time calculation
1077 */
1078 prob_now = ((BASE - gain) * prob_mid) >> BASE_SHIFT;
1079
1080 prob_last = prob_now;
1081 temp_last = temp_now;
1082
1083 return temp_last;
1084 }
1085
tsadc_get_temp_v3(struct udevice * dev,int chn,int * temp)1086 static int tsadc_get_temp_v3(struct udevice *dev,
1087 int chn, int *temp)
1088 {
1089 int ret;
1090
1091 ret = tsadc_get_temp_v2(dev, chn, temp);
1092 if (!ret)
1093 *temp = predict_temp(*temp);
1094
1095 return ret;
1096 }
1097
tsadc_get_temp_v4(struct udevice * dev,int chn,int * temp)1098 static int tsadc_get_temp_v4(struct udevice *dev, int chn, int *temp)
1099 {
1100 struct rockchip_thermal_priv *priv = dev_get_priv(dev);
1101 struct chip_tsadc_table table = priv->data->table;
1102 u32 val;
1103
1104 val = readl(priv->base + TSADCV3_DATA(chn));
1105
1106 return tsadc_code_to_temp(&table, val, temp);
1107 }
1108
tsadc_alarm_temp_v2(struct udevice * dev,int chn,int temp)1109 static void tsadc_alarm_temp_v2(struct udevice *dev,
1110 int chn, int temp)
1111 {
1112 struct rockchip_thermal_priv *priv = dev_get_priv(dev);
1113 struct chip_tsadc_table table = priv->data->table;
1114 u32 alarm_value, int_en;
1115
1116 alarm_value = tsadc_temp_to_code_v2(table, temp);
1117 if (alarm_value == table.data_mask)
1118 return;
1119
1120 writel(alarm_value, priv->base + TSADCV2_COMP_INT(chn));
1121
1122 int_en = readl(priv->base + TSADCV2_INT_EN);
1123 int_en |= TSADCV2_INT_SRC_EN(chn);
1124 writel(int_en, priv->base + TSADCV2_INT_EN);
1125 }
1126
tsadc_alarm_temp_v3(struct udevice * dev,int chn,int temp)1127 static void tsadc_alarm_temp_v3(struct udevice *dev, int chn, int temp)
1128 {
1129 struct rockchip_thermal_priv *priv = dev_get_priv(dev);
1130 struct chip_tsadc_table table = priv->data->table;
1131 u32 alarm_value;
1132
1133 alarm_value = tsadc_temp_to_code_v2(table, temp);
1134 if (alarm_value == table.data_mask)
1135 return;
1136
1137 writel(alarm_value, priv->base + TSADCV3_COMP_INT(chn));
1138 writel(TSADCV2_INT_SRC_EN(chn) | TSADCV2_INT_SRC_EN_MASK(chn),
1139 priv->base + TSADCV3_HT_INT_EN);
1140 }
1141
tsadc_tshut_temp_v2(struct udevice * dev,int chn,int temp)1142 static void tsadc_tshut_temp_v2(struct udevice *dev,
1143 int chn, int temp)
1144 {
1145 struct rockchip_thermal_priv *priv = dev_get_priv(dev);
1146 struct chip_tsadc_table table = priv->data->table;
1147 u32 tshut_value, val;
1148
1149 tshut_value = tsadc_temp_to_code_v2(table, temp);
1150 if (tshut_value == table.data_mask)
1151 return;
1152
1153 writel(tshut_value, priv->base + TSADCV2_COMP_SHUT(chn));
1154
1155 /* TSHUT will be valid */
1156 val = readl(priv->base + TSADCV2_AUTO_CON);
1157 writel(val | TSADCV2_AUTO_SRC_EN(chn), priv->base + TSADCV2_AUTO_CON);
1158 }
1159
tsadc_tshut_temp_v3(struct udevice * dev,int chn,int temp)1160 static void tsadc_tshut_temp_v3(struct udevice *dev, int chn, int temp)
1161 {
1162 struct rockchip_thermal_priv *priv = dev_get_priv(dev);
1163 struct chip_tsadc_table table = priv->data->table;
1164 u32 tshut_value;
1165
1166 tshut_value = tsadc_temp_to_code_v2(table, temp);
1167 if (tshut_value == table.data_mask)
1168 return;
1169
1170 writel(tshut_value, priv->base + TSADCV3_COMP_SHUT(chn));
1171 writel(TSADCV3_AUTO_SRC_EN(chn) | TSADCV3_AUTO_SRC_EN_MASK(chn),
1172 priv->base + TSADCV3_AUTO_SRC_CON);
1173 }
1174
tsadc_tshut_mode_v2(struct udevice * dev,int chn,enum tshut_mode mode)1175 static void tsadc_tshut_mode_v2(struct udevice *dev, int chn,
1176 enum tshut_mode mode)
1177 {
1178 struct rockchip_thermal_priv *priv = dev_get_priv(dev);
1179 u32 val;
1180
1181 val = readl(priv->base + TSADCV2_INT_EN);
1182 if (mode == TSHUT_MODE_GPIO) {
1183 val &= ~TSADCV2_SHUT_2CRU_SRC_EN(chn);
1184 val |= TSADCV2_SHUT_2GPIO_SRC_EN(chn);
1185 } else {
1186 val &= ~TSADCV2_SHUT_2GPIO_SRC_EN(chn);
1187 val |= TSADCV2_SHUT_2CRU_SRC_EN(chn);
1188 }
1189
1190 writel(val, priv->base + TSADCV2_INT_EN);
1191 }
1192
tsadc_tshut_mode_v4(struct udevice * dev,int chn,enum tshut_mode mode)1193 static void tsadc_tshut_mode_v4(struct udevice *dev, int chn,
1194 enum tshut_mode mode)
1195 {
1196 struct rockchip_thermal_priv *priv = dev_get_priv(dev);
1197 u32 val_gpio, val_cru;
1198
1199 if (mode == TSHUT_MODE_GPIO) {
1200 val_gpio = TSADCV2_INT_SRC_EN(chn) | TSADCV2_INT_SRC_EN_MASK(chn);
1201 val_cru = TSADCV2_INT_SRC_EN_MASK(chn);
1202 } else {
1203 val_cru = TSADCV2_INT_SRC_EN(chn) | TSADCV2_INT_SRC_EN_MASK(chn);
1204 val_gpio = TSADCV2_INT_SRC_EN_MASK(chn);
1205 }
1206 writel(val_gpio, priv->base + TSADCV3_HSHUT_GPIO_INT_EN);
1207 writel(val_cru, priv->base + TSADCV3_HSHUT_CRU_INT_EN);
1208 }
1209
rockchip_thermal_get_temp(struct udevice * dev,int * temp)1210 int rockchip_thermal_get_temp(struct udevice *dev, int *temp)
1211 {
1212 struct rockchip_thermal_priv *priv = dev_get_priv(dev);
1213
1214 priv->data->tsadc_get_temp(dev, 0, temp);
1215
1216 return 0;
1217 }
1218
1219 static const struct dm_thermal_ops rockchip_thermal_ops = {
1220 .get_temp = rockchip_thermal_get_temp,
1221 };
1222
1223 static const struct rockchip_tsadc_chip px30s_tsadc_data = {
1224 .chn_id[SENSOR_CPU] = 0, /* cpu sensor is channel 0 */
1225 .chn_id[SENSOR_GPU] = 1, /* gpu sensor is channel 1 */
1226 .chn_num = 2, /* 2 channels for tsadc */
1227
1228 .tshut_mode = TSHUT_MODE_CRU, /* default TSHUT via CRU */
1229 .tshut_temp = 95000,
1230
1231 .tsadc_init = tsadc_init_v9,
1232 .tsadc_control = tsadc_control_v2,
1233 .tsadc_get_temp = tsadc_get_temp_v2,
1234 .irq_ack = tsadc_irq_ack_v3,
1235 .set_alarm_temp = tsadc_alarm_temp_v2,
1236 .set_tshut_temp = tsadc_tshut_temp_v2,
1237 .set_tshut_mode = tsadc_tshut_mode_v2,
1238
1239 .table = {
1240 .knum = 2699,
1241 .bnum = 2796,
1242 .data_mask = TSADCV2_DATA_MASK,
1243 .mode = ADC_INCREMENT,
1244 },
1245 };
1246
1247 static const struct rockchip_tsadc_chip rk3308bs_tsadc_data = {
1248 .chn_id[SENSOR_CPU] = 0, /* cpu sensor is channel 0 */
1249 .chn_num = 1, /* 1 channels for tsadc */
1250
1251 .tshut_mode = TSHUT_MODE_CRU, /* default TSHUT via CRU */
1252 .tshut_temp = 95000,
1253
1254 .tsadc_init = tsadc_init_v2,
1255 .tsadc_control = tsadc_control_v2,
1256 .tsadc_get_temp = tsadc_get_temp_v2,
1257 .irq_ack = tsadc_irq_ack_v3,
1258 .set_alarm_temp = tsadc_alarm_temp_v2,
1259 .set_tshut_temp = tsadc_tshut_temp_v2,
1260 .set_tshut_mode = tsadc_tshut_mode_v2,
1261
1262 .table = {
1263 .knum = 2699,
1264 .bnum = 2796,
1265 .data_mask = TSADCV2_DATA_MASK,
1266 .mode = ADC_INCREMENT,
1267 },
1268 };
1269
rockchip_thermal_probe(struct udevice * dev)1270 static int rockchip_thermal_probe(struct udevice *dev)
1271 {
1272 struct rockchip_thermal_priv *priv = dev_get_priv(dev);
1273 struct rockchip_tsadc_chip *tsadc;
1274 struct clk clk;
1275 int ret, i, shut_temp;
1276
1277 /* Process 'assigned-{clocks/clock-parents/clock-rates}' properties */
1278 ret = clk_set_defaults(dev);
1279 if (ret)
1280 printf("%s clk_set_defaults failed %d\n", __func__, ret);
1281
1282 if (soc_is_rk3308bs() || soc_is_px30s()) {
1283 ret = clk_get_by_name(dev, "tsadc", &clk);
1284 if (ret) {
1285 printf("%s get tsadc clk fail\n", __func__);
1286 return -EINVAL;
1287 }
1288 ret = clk_set_rate(&clk, 4000000);
1289 if (ret < 0) {
1290 printf("%s: failed to set tsadc clk rate for %s\n",
1291 __func__, dev_read_name(dev));
1292 return -EINVAL;
1293 }
1294 }
1295 if (soc_is_rk3308bs())
1296 tsadc = (struct rockchip_tsadc_chip *)&rk3308bs_tsadc_data;
1297 else if (soc_is_px30s())
1298 tsadc = (struct rockchip_tsadc_chip *)&px30s_tsadc_data;
1299 else
1300 tsadc = (struct rockchip_tsadc_chip *)dev_get_driver_data(dev);
1301
1302 priv->data = tsadc;
1303
1304 priv->tshut_mode = dev_read_u32_default(dev,
1305 "rockchip,hw-tshut-mode",
1306 -1);
1307 if (priv->tshut_mode < 0)
1308 priv->tshut_mode = priv->data->tshut_mode;
1309
1310 priv->tshut_polarity = dev_read_u32_default(dev,
1311 "rockchip,hw-tshut-polarity",
1312 -1);
1313 if (priv->tshut_polarity < 0)
1314 priv->tshut_polarity = tsadc->tshut_polarity;
1315
1316 if (priv->tshut_mode == TSHUT_MODE_GPIO)
1317 pinctrl_select_state(dev, "otpout");
1318 else if (soc_is_rk3308())
1319 pinctrl_select_state(dev, "gpio");
1320
1321 tsadc->tsadc_init(dev);
1322 tsadc->irq_ack(dev);
1323
1324 shut_temp = dev_read_u32_default(dev, "rockchip,hw-tshut-temp", -1);
1325 if (shut_temp < 0)
1326 shut_temp = 120000;
1327
1328 for (i = 0; i < tsadc->chn_num; i++) {
1329 tsadc->set_alarm_temp(dev, i, tsadc->tshut_temp);
1330 tsadc->set_tshut_temp(dev, i, shut_temp);
1331 if (priv->tshut_mode == TSHUT_MODE_GPIO)
1332 tsadc->set_tshut_mode(dev, i, TSHUT_MODE_GPIO);
1333 else
1334 tsadc->set_tshut_mode(dev, i, TSHUT_MODE_CRU);
1335 }
1336
1337 tsadc->tsadc_control(dev, true);
1338 if (soc_is_rk3308bs() || soc_is_px30s())
1339 mdelay(3);
1340 else
1341 udelay(1000);
1342
1343 debug("tsadc probed successfully\n");
1344
1345 return 0;
1346 }
1347
rockchip_thermal_ofdata_to_platdata(struct udevice * dev)1348 static int rockchip_thermal_ofdata_to_platdata(struct udevice *dev)
1349 {
1350 struct rockchip_thermal_priv *priv = dev_get_priv(dev);
1351
1352 priv->base = dev_read_addr_ptr(dev);
1353 priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
1354
1355 return 0;
1356 }
1357
1358 static const struct rockchip_tsadc_chip rk1808_tsadc_data = {
1359 .chn_id[SENSOR_CPU] = 0, /* cpu sensor is channel 0 */
1360 .chn_num = 1, /* one channel for tsadc */
1361
1362 .tshut_mode = TSHUT_MODE_GPIO, /* default TSHUT via GPIO give PMIC */
1363 .tshut_polarity = TSHUT_LOW_ACTIVE, /* default TSHUT LOW ACTIVE */
1364 .tshut_temp = 95000,
1365
1366 .tsadc_init = tsadc_init_v2,
1367 .tsadc_control = tsadc_control_v3,
1368 .tsadc_get_temp = tsadc_get_temp_v2,
1369 .irq_ack = tsadc_irq_ack_v3,
1370 .set_alarm_temp = tsadc_alarm_temp_v2,
1371 .set_tshut_temp = tsadc_tshut_temp_v2,
1372 .set_tshut_mode = tsadc_tshut_mode_v2,
1373
1374 .table = {
1375 .id = rk1808_code_table,
1376 .length = ARRAY_SIZE(rk1808_code_table),
1377 .data_mask = TSADCV2_DATA_MASK,
1378 .mode = ADC_INCREMENT,
1379 },
1380 };
1381
1382 static const struct rockchip_tsadc_chip rk3228_tsadc_data = {
1383 .chn_id[SENSOR_CPU] = 0, /* cpu sensor is channel 0 */
1384 .chn_num = 1, /* one channel for tsadc */
1385
1386 .tshut_mode = TSHUT_MODE_GPIO, /* default TSHUT via GPIO give PMIC */
1387 .tshut_polarity = TSHUT_LOW_ACTIVE, /* default TSHUT LOW ACTIVE */
1388 .tshut_temp = 95000,
1389
1390 .tsadc_init = tsadc_init_v2,
1391 .tsadc_control = tsadc_control_v3,
1392 .tsadc_get_temp = tsadc_get_temp_v2,
1393 .irq_ack = tsadc_irq_ack_v3,
1394 .set_alarm_temp = tsadc_alarm_temp_v2,
1395 .set_tshut_temp = tsadc_tshut_temp_v2,
1396 .set_tshut_mode = tsadc_tshut_mode_v2,
1397
1398 .table = {
1399 .id = rk3228_code_table,
1400 .length = ARRAY_SIZE(rk3228_code_table),
1401 .data_mask = TSADCV3_DATA_MASK,
1402 .mode = ADC_INCREMENT,
1403 },
1404 };
1405
1406 static const struct rockchip_tsadc_chip rk3288_tsadc_data = {
1407 .chn_id[SENSOR_CPU] = 1, /* cpu sensor is channel 1 */
1408 .chn_id[SENSOR_GPU] = 2, /* gpu sensor is channel 2 */
1409 .chn_num = 2, /* two channels for tsadc */
1410
1411 .tshut_mode = TSHUT_MODE_GPIO, /* default TSHUT via GPIO give PMIC */
1412 .tshut_polarity = TSHUT_LOW_ACTIVE, /* default TSHUT LOW ACTIVE */
1413 .tshut_temp = 95000,
1414
1415 .tsadc_init = tsadc_init_v2,
1416 .tsadc_control = tsadc_control_v2,
1417 .tsadc_get_temp = tsadc_get_temp_v3,
1418 .irq_ack = tsadc_irq_ack_v2,
1419 .set_alarm_temp = tsadc_alarm_temp_v2,
1420 .set_tshut_temp = tsadc_tshut_temp_v2,
1421 .set_tshut_mode = tsadc_tshut_mode_v2,
1422
1423 .table = {
1424 .id = rk3288_code_table,
1425 .length = ARRAY_SIZE(rk3288_code_table),
1426 .data_mask = TSADCV2_DATA_MASK,
1427 .mode = ADC_DECREMENT,
1428 },
1429 };
1430
1431 static const struct rockchip_tsadc_chip rk3308_tsadc_data = {
1432 .chn_id[SENSOR_CPU] = 0, /* cpu sensor is channel 0 */
1433 .chn_id[SENSOR_GPU] = 1, /* gpu sensor is channel 1 */
1434 .chn_num = 2, /* 2 channels for tsadc */
1435
1436 .tshut_mode = TSHUT_MODE_CRU, /* default TSHUT via CRU */
1437 .tshut_temp = 95000,
1438
1439 .tsadc_init = tsadc_init_v4,
1440 .tsadc_control = tsadc_control_v3,
1441 .tsadc_get_temp = tsadc_get_temp_v2,
1442 .irq_ack = tsadc_irq_ack_v3,
1443 .set_alarm_temp = tsadc_alarm_temp_v2,
1444 .set_tshut_temp = tsadc_tshut_temp_v2,
1445 .set_tshut_mode = tsadc_tshut_mode_v2,
1446
1447 .table = {
1448 .id = rk3328_code_table,
1449 .length = ARRAY_SIZE(rk3328_code_table),
1450 .data_mask = TSADCV2_DATA_MASK,
1451 .mode = ADC_INCREMENT,
1452 },
1453 };
1454
1455 static const struct rockchip_tsadc_chip px30_tsadc_data = {
1456 .chn_id[SENSOR_CPU] = 0, /* cpu sensor is channel 0 */
1457 .chn_id[SENSOR_GPU] = 1, /* gpu sensor is channel 1 */
1458 .chn_num = 2, /* 2 channels for tsadc */
1459
1460 .tshut_mode = TSHUT_MODE_CRU, /* default TSHUT via CRU */
1461 .tshut_temp = 95000,
1462
1463 .tsadc_init = tsadc_init_v4,
1464 .tsadc_control = tsadc_control_v3,
1465 .tsadc_get_temp = tsadc_get_temp_v2,
1466 .irq_ack = tsadc_irq_ack_v3,
1467 .set_alarm_temp = tsadc_alarm_temp_v2,
1468 .set_tshut_temp = tsadc_tshut_temp_v2,
1469 .set_tshut_mode = tsadc_tshut_mode_v2,
1470
1471 .table = {
1472 .id = rk3328_code_table,
1473 .length = ARRAY_SIZE(rk3328_code_table),
1474 .data_mask = TSADCV2_DATA_MASK,
1475 .mode = ADC_INCREMENT,
1476 },
1477 };
1478
1479 static const struct rockchip_tsadc_chip rk3328_tsadc_data = {
1480 .chn_id[SENSOR_CPU] = 0, /* cpu sensor is channel 0 */
1481 .chn_num = 1, /* one channels for tsadc */
1482
1483 .tshut_mode = TSHUT_MODE_CRU, /* default TSHUT via CRU */
1484 .tshut_temp = 95000,
1485
1486 .tsadc_init = tsadc_init_v2,
1487 .tsadc_control = tsadc_control_v3,
1488 .tsadc_get_temp = tsadc_get_temp_v2,
1489 .irq_ack = tsadc_irq_ack_v3,
1490 .set_alarm_temp = tsadc_alarm_temp_v2,
1491 .set_tshut_temp = tsadc_tshut_temp_v2,
1492 .set_tshut_mode = tsadc_tshut_mode_v2,
1493
1494 .table = {
1495 .id = rk3328_code_table,
1496 .length = ARRAY_SIZE(rk3328_code_table),
1497 .data_mask = TSADCV2_DATA_MASK,
1498 .mode = ADC_INCREMENT,
1499 },
1500 };
1501
1502 static const struct rockchip_tsadc_chip rk3366_tsadc_data = {
1503 .chn_id[SENSOR_CPU] = 0, /* cpu sensor is channel 0 */
1504 .chn_id[SENSOR_GPU] = 1, /* gpu sensor is channel 1 */
1505 .chn_num = 2, /* two channels for tsadc */
1506
1507 .tshut_mode = TSHUT_MODE_GPIO, /* default TSHUT via GPIO give PMIC */
1508 .tshut_polarity = TSHUT_LOW_ACTIVE, /* default TSHUT LOW ACTIVE */
1509 .tshut_temp = 95000,
1510
1511 .tsadc_init = tsadc_init_v3,
1512 .tsadc_control = tsadc_control_v3,
1513 .tsadc_get_temp = tsadc_get_temp_v2,
1514 .irq_ack = tsadc_irq_ack_v3,
1515 .set_alarm_temp = tsadc_alarm_temp_v2,
1516 .set_tshut_temp = tsadc_tshut_temp_v2,
1517 .set_tshut_mode = tsadc_tshut_mode_v2,
1518
1519 .table = {
1520 .id = rk3228_code_table,
1521 .length = ARRAY_SIZE(rk3228_code_table),
1522 .data_mask = TSADCV3_DATA_MASK,
1523 .mode = ADC_INCREMENT,
1524 },
1525 };
1526
1527 static const struct rockchip_tsadc_chip rk3368_tsadc_data = {
1528 .chn_id[SENSOR_CPU] = 0, /* cpu sensor is channel 0 */
1529 .chn_id[SENSOR_GPU] = 1, /* gpu sensor is channel 1 */
1530 .chn_num = 2, /* two channels for tsadc */
1531
1532 .tshut_mode = TSHUT_MODE_GPIO, /* default TSHUT via GPIO give PMIC */
1533 .tshut_polarity = TSHUT_LOW_ACTIVE, /* default TSHUT LOW ACTIVE */
1534 .tshut_temp = 95000,
1535
1536 .tsadc_init = tsadc_init_v2,
1537 .tsadc_control = tsadc_control_v2,
1538 .tsadc_get_temp = tsadc_get_temp_v2,
1539 .irq_ack = tsadc_irq_ack_v2,
1540 .set_alarm_temp = tsadc_alarm_temp_v2,
1541 .set_tshut_temp = tsadc_tshut_temp_v2,
1542 .set_tshut_mode = tsadc_tshut_mode_v2,
1543
1544 .table = {
1545 .id = rk3368_code_table,
1546 .length = ARRAY_SIZE(rk3368_code_table),
1547 .data_mask = TSADCV3_DATA_MASK,
1548 .mode = ADC_INCREMENT,
1549 },
1550 };
1551
1552 static const struct rockchip_tsadc_chip rk3399_tsadc_data = {
1553 .chn_id[SENSOR_CPU] = 0, /* cpu sensor is channel 0 */
1554 .chn_id[SENSOR_GPU] = 1, /* gpu sensor is channel 1 */
1555 .chn_num = 2, /* two channels for tsadc */
1556
1557 .tshut_mode = TSHUT_MODE_GPIO, /* default TSHUT via GPIO give PMIC */
1558 .tshut_polarity = TSHUT_LOW_ACTIVE, /* default TSHUT LOW ACTIVE */
1559 .tshut_temp = 95000,
1560
1561 .tsadc_init = tsadc_init_v3,
1562 .tsadc_control = tsadc_control_v3,
1563 .tsadc_get_temp = tsadc_get_temp_v2,
1564 .irq_ack = tsadc_irq_ack_v3,
1565 .set_alarm_temp = tsadc_alarm_temp_v2,
1566 .set_tshut_temp = tsadc_tshut_temp_v2,
1567 .set_tshut_mode = tsadc_tshut_mode_v2,
1568
1569 .table = {
1570 .id = rk3399_code_table,
1571 .length = ARRAY_SIZE(rk3399_code_table),
1572 .data_mask = TSADCV3_DATA_MASK,
1573 .mode = ADC_INCREMENT,
1574 },
1575 };
1576
1577 static const struct rockchip_tsadc_chip rk3528_tsadc_data = {
1578 .chn_id[SENSOR_CPU] = 0, /* cpu sensor is channel 0 */
1579 .chn_num = 1, /* one channels for tsadc */
1580
1581 .tshut_mode = TSHUT_MODE_CRU, /* default TSHUT via GPIO give PMIC */
1582 .tshut_polarity = TSHUT_LOW_ACTIVE, /* default TSHUT LOW ACTIVE */
1583 .tshut_temp = 95000,
1584
1585 .tsadc_init = tsadc_init_v11,
1586 .tsadc_control = tsadc_control_v4,
1587 .tsadc_get_temp = tsadc_get_temp_v4,
1588 .irq_ack = tsadc_irq_ack_v4,
1589 .set_alarm_temp = tsadc_alarm_temp_v3,
1590 .set_tshut_temp = tsadc_tshut_temp_v3,
1591 .set_tshut_mode = tsadc_tshut_mode_v4,
1592
1593 .table = {
1594 .id = rk3528_code_table,
1595 .length = ARRAY_SIZE(rk3528_code_table),
1596 .data_mask = TSADCV2_DATA_MASK,
1597 .mode = ADC_INCREMENT,
1598 },
1599 };
1600
1601 static const struct rockchip_tsadc_chip rk3562_tsadc_data = {
1602 .chn_id[SENSOR_CPU] = 0, /* cpu sensor is channel 0 */
1603 .chn_num = 1, /* one channels for tsadc */
1604
1605 .tshut_mode = TSHUT_MODE_GPIO, /* default TSHUT via GPIO give PMIC */
1606 .tshut_polarity = TSHUT_LOW_ACTIVE, /* default TSHUT LOW ACTIVE */
1607 .tshut_temp = 95000,
1608
1609 .tsadc_init = tsadc_init_v12,
1610 .tsadc_control = tsadc_control_v4,
1611 .tsadc_get_temp = tsadc_get_temp_v4,
1612 .irq_ack = tsadc_irq_ack_v4,
1613 .set_alarm_temp = tsadc_alarm_temp_v3,
1614 .set_tshut_temp = tsadc_tshut_temp_v3,
1615 .set_tshut_mode = tsadc_tshut_mode_v4,
1616
1617 .table = {
1618 .id = rk3562_code_table,
1619 .length = ARRAY_SIZE(rk3562_code_table),
1620 .data_mask = TSADCV2_DATA_MASK,
1621 .mode = ADC_INCREMENT,
1622 },
1623 };
1624
1625 static const struct rockchip_tsadc_chip rk3568_tsadc_data = {
1626 .chn_id[SENSOR_CPU] = 0, /* cpu sensor is channel 0 */
1627 .chn_id[SENSOR_GPU] = 1, /* gpu sensor is channel 1 */
1628 .chn_num = 2, /* two channels for tsadc */
1629
1630 .tshut_mode = TSHUT_MODE_GPIO, /* default TSHUT via GPIO give PMIC */
1631 .tshut_polarity = TSHUT_LOW_ACTIVE, /* default TSHUT LOW ACTIVE */
1632 .tshut_temp = 95000,
1633
1634 .tsadc_init = tsadc_init_v7,
1635 .tsadc_control = tsadc_control_v3,
1636 .tsadc_get_temp = tsadc_get_temp_v2,
1637 .irq_ack = tsadc_irq_ack_v3,
1638 .set_alarm_temp = tsadc_alarm_temp_v2,
1639 .set_tshut_temp = tsadc_tshut_temp_v2,
1640 .set_tshut_mode = tsadc_tshut_mode_v2,
1641
1642 .table = {
1643 .id = rk3568_code_table,
1644 .length = ARRAY_SIZE(rk3568_code_table),
1645 .data_mask = TSADCV2_DATA_MASK,
1646 .mode = ADC_INCREMENT,
1647 },
1648 };
1649
1650 static const struct rockchip_tsadc_chip rk3588_tsadc_data = {
1651 /* top, big_core0, big_core1, little_core, center, gpu, npu */
1652 .chn_id = {0, 1, 2, 3, 4, 5, 6},
1653 .chn_num = 7, /* seven channels for tsadc */
1654
1655 .tshut_mode = TSHUT_MODE_GPIO, /* default TSHUT via GPIO give PMIC */
1656 .tshut_polarity = TSHUT_LOW_ACTIVE, /* default TSHUT LOW ACTIVE */
1657 .tshut_temp = 95000,
1658
1659 .tsadc_init = tsadc_init_v8,
1660 .tsadc_control = tsadc_control_v4,
1661 .tsadc_get_temp = tsadc_get_temp_v4,
1662 .irq_ack = tsadc_irq_ack_v4,
1663 .set_alarm_temp = tsadc_alarm_temp_v3,
1664 .set_tshut_temp = tsadc_tshut_temp_v3,
1665 .set_tshut_mode = tsadc_tshut_mode_v4,
1666
1667 .table = {
1668 .id = rk3588_code_table,
1669 .length = ARRAY_SIZE(rk3588_code_table),
1670 .data_mask = TSADCV4_DATA_MASK,
1671 .mode = ADC_INCREMENT,
1672 },
1673 };
1674
1675 static const struct udevice_id rockchip_thermal_match[] = {
1676 {
1677 .compatible = "rockchip,px30-tsadc",
1678 .data = (ulong)&px30_tsadc_data,
1679 },
1680 {
1681 .compatible = "rockchip,px30s-tsadc",
1682 .data = (ulong)&px30s_tsadc_data,
1683 },
1684 {
1685 .compatible = "rockchip,rk1808-tsadc",
1686 .data = (ulong)&rk1808_tsadc_data,
1687 },
1688 {
1689 .compatible = "rockchip,rk3228-tsadc",
1690 .data = (ulong)&rk3228_tsadc_data,
1691 },
1692 {
1693 .compatible = "rockchip,rk3288-tsadc",
1694 .data = (ulong)&rk3288_tsadc_data,
1695 },
1696 {
1697 .compatible = "rockchip,rk3308-tsadc",
1698 .data = (ulong)&rk3308_tsadc_data,
1699 },
1700 {
1701 .compatible = "rockchip,rk3308bs-tsadc",
1702 .data = (ulong)&rk3308bs_tsadc_data,
1703 },
1704 {
1705 .compatible = "rockchip,rk3328-tsadc",
1706 .data = (ulong)&rk3328_tsadc_data,
1707 },
1708 {
1709 .compatible = "rockchip,rk3366-tsadc",
1710 .data = (ulong)&rk3366_tsadc_data,
1711 },
1712 {
1713 .compatible = "rockchip,rk3368-tsadc",
1714 .data = (ulong)&rk3368_tsadc_data,
1715 },
1716 {
1717 .compatible = "rockchip,rk3399-tsadc",
1718 .data = (ulong)&rk3399_tsadc_data,
1719 },
1720 {
1721 .compatible = "rockchip,rk3528-tsadc",
1722 .data = (ulong)&rk3528_tsadc_data,
1723 },
1724 {
1725 .compatible = "rockchip,rk3562-tsadc",
1726 .data = (ulong)&rk3562_tsadc_data,
1727 },
1728 {
1729 .compatible = "rockchip,rk3568-tsadc",
1730 .data = (ulong)&rk3568_tsadc_data,
1731 },
1732 {
1733 .compatible = "rockchip,rk3588-tsadc",
1734 .data = (ulong)&rk3588_tsadc_data,
1735 },
1736 { /* end */ },
1737 };
1738
1739 U_BOOT_DRIVER(rockchip_thermal) = {
1740 .name = "rockchip_thermal",
1741 .id = UCLASS_THERMAL,
1742 .of_match = rockchip_thermal_match,
1743 .priv_auto_alloc_size = sizeof(struct rockchip_thermal_priv),
1744 .ofdata_to_platdata = rockchip_thermal_ofdata_to_platdata,
1745 .ops = &rockchip_thermal_ops,
1746 .probe = rockchip_thermal_probe,
1747 };
1748