1 /*
2 * (C) Copyright 2016
3 *
4 * Michael Kurz, <michi.kurz@gmail.com>
5 *
6 * STM32 QSPI driver
7 *
8 * SPDX-License-Identifier: GPL-2.0+
9 */
10
11 #include <common.h>
12 #include <malloc.h>
13 #include <spi.h>
14 #include <spi_flash.h>
15 #include <asm/io.h>
16 #include <dm.h>
17 #include <errno.h>
18 #include <asm/arch/stm32.h>
19 #include <asm/arch/stm32_defs.h>
20 #include <clk.h>
21
22 DECLARE_GLOBAL_DATA_PTR;
23
24 struct stm32_qspi_regs {
25 u32 cr; /* 0x00 */
26 u32 dcr; /* 0x04 */
27 u32 sr; /* 0x08 */
28 u32 fcr; /* 0x0C */
29 u32 dlr; /* 0x10 */
30 u32 ccr; /* 0x14 */
31 u32 ar; /* 0x18 */
32 u32 abr; /* 0x1C */
33 u32 dr; /* 0x20 */
34 u32 psmkr; /* 0x24 */
35 u32 psmar; /* 0x28 */
36 u32 pir; /* 0x2C */
37 u32 lptr; /* 0x30 */
38 };
39
40 /*
41 * QUADSPI control register
42 */
43 #define STM32_QSPI_CR_EN BIT(0)
44 #define STM32_QSPI_CR_ABORT BIT(1)
45 #define STM32_QSPI_CR_DMAEN BIT(2)
46 #define STM32_QSPI_CR_TCEN BIT(3)
47 #define STM32_QSPI_CR_SSHIFT BIT(4)
48 #define STM32_QSPI_CR_DFM BIT(6)
49 #define STM32_QSPI_CR_FSEL BIT(7)
50 #define STM32_QSPI_CR_FTHRES_MASK GENMASK(4, 0)
51 #define STM32_QSPI_CR_FTHRES_SHIFT (8)
52 #define STM32_QSPI_CR_TEIE BIT(16)
53 #define STM32_QSPI_CR_TCIE BIT(17)
54 #define STM32_QSPI_CR_FTIE BIT(18)
55 #define STM32_QSPI_CR_SMIE BIT(19)
56 #define STM32_QSPI_CR_TOIE BIT(20)
57 #define STM32_QSPI_CR_APMS BIT(22)
58 #define STM32_QSPI_CR_PMM BIT(23)
59 #define STM32_QSPI_CR_PRESCALER_MASK GENMASK(7, 0)
60 #define STM32_QSPI_CR_PRESCALER_SHIFT (24)
61
62 /*
63 * QUADSPI device configuration register
64 */
65 #define STM32_QSPI_DCR_CKMODE BIT(0)
66 #define STM32_QSPI_DCR_CSHT_MASK GENMASK(2, 0)
67 #define STM32_QSPI_DCR_CSHT_SHIFT (8)
68 #define STM32_QSPI_DCR_FSIZE_MASK GENMASK(4, 0)
69 #define STM32_QSPI_DCR_FSIZE_SHIFT (16)
70
71 /*
72 * QUADSPI status register
73 */
74 #define STM32_QSPI_SR_TEF BIT(0)
75 #define STM32_QSPI_SR_TCF BIT(1)
76 #define STM32_QSPI_SR_FTF BIT(2)
77 #define STM32_QSPI_SR_SMF BIT(3)
78 #define STM32_QSPI_SR_TOF BIT(4)
79 #define STM32_QSPI_SR_BUSY BIT(5)
80 #define STM32_QSPI_SR_FLEVEL_MASK GENMASK(5, 0)
81 #define STM32_QSPI_SR_FLEVEL_SHIFT (8)
82
83 /*
84 * QUADSPI flag clear register
85 */
86 #define STM32_QSPI_FCR_CTEF BIT(0)
87 #define STM32_QSPI_FCR_CTCF BIT(1)
88 #define STM32_QSPI_FCR_CSMF BIT(3)
89 #define STM32_QSPI_FCR_CTOF BIT(4)
90
91 /*
92 * QUADSPI communication configuration register
93 */
94 #define STM32_QSPI_CCR_DDRM BIT(31)
95 #define STM32_QSPI_CCR_DHHC BIT(30)
96 #define STM32_QSPI_CCR_SIOO BIT(28)
97 #define STM32_QSPI_CCR_FMODE_SHIFT (26)
98 #define STM32_QSPI_CCR_DMODE_SHIFT (24)
99 #define STM32_QSPI_CCR_DCYC_SHIFT (18)
100 #define STM32_QSPI_CCR_DCYC_MASK GENMASK(4, 0)
101 #define STM32_QSPI_CCR_ABSIZE_SHIFT (16)
102 #define STM32_QSPI_CCR_ABMODE_SHIFT (14)
103 #define STM32_QSPI_CCR_ADSIZE_SHIFT (12)
104 #define STM32_QSPI_CCR_ADMODE_SHIFT (10)
105 #define STM32_QSPI_CCR_IMODE_SHIFT (8)
106 #define STM32_QSPI_CCR_INSTRUCTION_MASK GENMASK(7, 0)
107
108 enum STM32_QSPI_CCR_IMODE {
109 STM32_QSPI_CCR_IMODE_NONE = 0,
110 STM32_QSPI_CCR_IMODE_ONE_LINE = 1,
111 STM32_QSPI_CCR_IMODE_TWO_LINE = 2,
112 STM32_QSPI_CCR_IMODE_FOUR_LINE = 3,
113 };
114
115 enum STM32_QSPI_CCR_ADMODE {
116 STM32_QSPI_CCR_ADMODE_NONE = 0,
117 STM32_QSPI_CCR_ADMODE_ONE_LINE = 1,
118 STM32_QSPI_CCR_ADMODE_TWO_LINE = 2,
119 STM32_QSPI_CCR_ADMODE_FOUR_LINE = 3,
120 };
121
122 enum STM32_QSPI_CCR_ADSIZE {
123 STM32_QSPI_CCR_ADSIZE_8BIT = 0,
124 STM32_QSPI_CCR_ADSIZE_16BIT = 1,
125 STM32_QSPI_CCR_ADSIZE_24BIT = 2,
126 STM32_QSPI_CCR_ADSIZE_32BIT = 3,
127 };
128
129 enum STM32_QSPI_CCR_ABMODE {
130 STM32_QSPI_CCR_ABMODE_NONE = 0,
131 STM32_QSPI_CCR_ABMODE_ONE_LINE = 1,
132 STM32_QSPI_CCR_ABMODE_TWO_LINE = 2,
133 STM32_QSPI_CCR_ABMODE_FOUR_LINE = 3,
134 };
135
136 enum STM32_QSPI_CCR_ABSIZE {
137 STM32_QSPI_CCR_ABSIZE_8BIT = 0,
138 STM32_QSPI_CCR_ABSIZE_16BIT = 1,
139 STM32_QSPI_CCR_ABSIZE_24BIT = 2,
140 STM32_QSPI_CCR_ABSIZE_32BIT = 3,
141 };
142
143 enum STM32_QSPI_CCR_DMODE {
144 STM32_QSPI_CCR_DMODE_NONE = 0,
145 STM32_QSPI_CCR_DMODE_ONE_LINE = 1,
146 STM32_QSPI_CCR_DMODE_TWO_LINE = 2,
147 STM32_QSPI_CCR_DMODE_FOUR_LINE = 3,
148 };
149
150 enum STM32_QSPI_CCR_FMODE {
151 STM32_QSPI_CCR_IND_WRITE = 0,
152 STM32_QSPI_CCR_IND_READ = 1,
153 STM32_QSPI_CCR_AUTO_POLL = 2,
154 STM32_QSPI_CCR_MEM_MAP = 3,
155 };
156
157 /* default SCK frequency, unit: HZ */
158 #define STM32_QSPI_DEFAULT_SCK_FREQ 108000000
159
160 struct stm32_qspi_platdata {
161 u32 base;
162 u32 memory_map;
163 u32 max_hz;
164 };
165
166 struct stm32_qspi_priv {
167 struct stm32_qspi_regs *regs;
168 ulong clock_rate;
169 u32 max_hz;
170 u32 mode;
171
172 u32 command;
173 u32 address;
174 u32 dummycycles;
175 #define CMD_HAS_ADR BIT(24)
176 #define CMD_HAS_DUMMY BIT(25)
177 #define CMD_HAS_DATA BIT(26)
178 };
179
_stm32_qspi_disable(struct stm32_qspi_priv * priv)180 static void _stm32_qspi_disable(struct stm32_qspi_priv *priv)
181 {
182 clrbits_le32(&priv->regs->cr, STM32_QSPI_CR_EN);
183 }
184
_stm32_qspi_enable(struct stm32_qspi_priv * priv)185 static void _stm32_qspi_enable(struct stm32_qspi_priv *priv)
186 {
187 setbits_le32(&priv->regs->cr, STM32_QSPI_CR_EN);
188 }
189
_stm32_qspi_wait_for_not_busy(struct stm32_qspi_priv * priv)190 static void _stm32_qspi_wait_for_not_busy(struct stm32_qspi_priv *priv)
191 {
192 while (readl(&priv->regs->sr) & STM32_QSPI_SR_BUSY)
193 ;
194 }
195
_stm32_qspi_wait_for_complete(struct stm32_qspi_priv * priv)196 static void _stm32_qspi_wait_for_complete(struct stm32_qspi_priv *priv)
197 {
198 while (!(readl(&priv->regs->sr) & STM32_QSPI_SR_TCF))
199 ;
200 }
201
_stm32_qspi_wait_for_ftf(struct stm32_qspi_priv * priv)202 static void _stm32_qspi_wait_for_ftf(struct stm32_qspi_priv *priv)
203 {
204 while (!(readl(&priv->regs->sr) & STM32_QSPI_SR_FTF))
205 ;
206 }
207
_stm32_qspi_set_flash_size(struct stm32_qspi_priv * priv,u32 size)208 static void _stm32_qspi_set_flash_size(struct stm32_qspi_priv *priv, u32 size)
209 {
210 u32 fsize = fls(size) - 1;
211 clrsetbits_le32(&priv->regs->dcr,
212 STM32_QSPI_DCR_FSIZE_MASK << STM32_QSPI_DCR_FSIZE_SHIFT,
213 fsize << STM32_QSPI_DCR_FSIZE_SHIFT);
214 }
215
_stm32_qspi_gen_ccr(struct stm32_qspi_priv * priv)216 static unsigned int _stm32_qspi_gen_ccr(struct stm32_qspi_priv *priv)
217 {
218 unsigned int ccr_reg = 0;
219 u8 imode, admode, dmode;
220 u32 mode = priv->mode;
221 u32 cmd = (priv->command & STM32_QSPI_CCR_INSTRUCTION_MASK);
222
223 imode = STM32_QSPI_CCR_IMODE_ONE_LINE;
224 admode = STM32_QSPI_CCR_ADMODE_ONE_LINE;
225
226 if (mode & SPI_RX_QUAD) {
227 dmode = STM32_QSPI_CCR_DMODE_FOUR_LINE;
228 if (mode & SPI_TX_QUAD) {
229 imode = STM32_QSPI_CCR_IMODE_FOUR_LINE;
230 admode = STM32_QSPI_CCR_ADMODE_FOUR_LINE;
231 }
232 } else if (mode & SPI_RX_DUAL) {
233 dmode = STM32_QSPI_CCR_DMODE_TWO_LINE;
234 if (mode & SPI_TX_DUAL) {
235 imode = STM32_QSPI_CCR_IMODE_TWO_LINE;
236 admode = STM32_QSPI_CCR_ADMODE_TWO_LINE;
237 }
238 } else {
239 dmode = STM32_QSPI_CCR_DMODE_ONE_LINE;
240 }
241
242 if (priv->command & CMD_HAS_DATA)
243 ccr_reg |= (dmode << STM32_QSPI_CCR_DMODE_SHIFT);
244
245 if (priv->command & CMD_HAS_DUMMY)
246 ccr_reg |= ((priv->dummycycles & STM32_QSPI_CCR_DCYC_MASK)
247 << STM32_QSPI_CCR_DCYC_SHIFT);
248
249 if (priv->command & CMD_HAS_ADR) {
250 ccr_reg |= (STM32_QSPI_CCR_ADSIZE_24BIT
251 << STM32_QSPI_CCR_ADSIZE_SHIFT);
252 ccr_reg |= (admode << STM32_QSPI_CCR_ADMODE_SHIFT);
253 }
254 ccr_reg |= (imode << STM32_QSPI_CCR_IMODE_SHIFT);
255 ccr_reg |= cmd;
256 return ccr_reg;
257 }
258
_stm32_qspi_enable_mmap(struct stm32_qspi_priv * priv,struct spi_flash * flash)259 static void _stm32_qspi_enable_mmap(struct stm32_qspi_priv *priv,
260 struct spi_flash *flash)
261 {
262 unsigned int ccr_reg;
263
264 priv->command = flash->read_opcode | CMD_HAS_ADR | CMD_HAS_DATA
265 | CMD_HAS_DUMMY;
266 priv->dummycycles = flash->read_dummy;
267
268 unsigned int ccr_reg = _stm32_qspi_gen_ccr(priv);
269 ccr_reg |= (STM32_QSPI_CCR_MEM_MAP << STM32_QSPI_CCR_FMODE_SHIFT);
270
271 _stm32_qspi_wait_for_not_busy(priv);
272
273 writel(ccr_reg, &priv->regs->ccr);
274
275 priv->dummycycles = 0;
276 }
277
_stm32_qspi_disable_mmap(struct stm32_qspi_priv * priv)278 static void _stm32_qspi_disable_mmap(struct stm32_qspi_priv *priv)
279 {
280 setbits_le32(&priv->regs->cr, STM32_QSPI_CR_ABORT);
281 }
282
_stm32_qspi_set_xfer_length(struct stm32_qspi_priv * priv,u32 length)283 static void _stm32_qspi_set_xfer_length(struct stm32_qspi_priv *priv,
284 u32 length)
285 {
286 writel(length - 1, &priv->regs->dlr);
287 }
288
_stm32_qspi_start_xfer(struct stm32_qspi_priv * priv,u32 cr_reg)289 static void _stm32_qspi_start_xfer(struct stm32_qspi_priv *priv, u32 cr_reg)
290 {
291 writel(cr_reg, &priv->regs->ccr);
292
293 if (priv->command & CMD_HAS_ADR)
294 writel(priv->address, &priv->regs->ar);
295 }
296
_stm32_qspi_xfer(struct stm32_qspi_priv * priv,struct spi_flash * flash,unsigned int bitlen,const u8 * dout,u8 * din,unsigned long flags)297 static int _stm32_qspi_xfer(struct stm32_qspi_priv *priv,
298 struct spi_flash *flash, unsigned int bitlen,
299 const u8 *dout, u8 *din, unsigned long flags)
300 {
301 unsigned int words = bitlen / 8;
302
303 if (flags & SPI_XFER_MMAP) {
304 _stm32_qspi_enable_mmap(priv, flash);
305 return 0;
306 } else if (flags & SPI_XFER_MMAP_END) {
307 _stm32_qspi_disable_mmap(priv);
308 return 0;
309 }
310
311 if (bitlen == 0)
312 return -1;
313
314 if (bitlen % 8) {
315 debug("spi_xfer: Non byte aligned SPI transfer\n");
316 return -1;
317 }
318
319 if (dout && din) {
320 debug("spi_xfer: QSPI cannot have data in and data out set\n");
321 return -1;
322 }
323
324 if (!dout && (flags & SPI_XFER_BEGIN)) {
325 debug("spi_xfer: QSPI transfer must begin with command\n");
326 return -1;
327 }
328
329 if (dout) {
330 if (flags & SPI_XFER_BEGIN) {
331 /* data is command */
332 priv->command = dout[0] | CMD_HAS_DATA;
333 if (words >= 4) {
334 /* address is here too */
335 priv->address = (dout[1] << 16) |
336 (dout[2] << 8) | dout[3];
337 priv->command |= CMD_HAS_ADR;
338 }
339
340 if (words > 4) {
341 /* rest is dummy bytes */
342 priv->dummycycles = (words - 4) * 8;
343 priv->command |= CMD_HAS_DUMMY;
344 }
345
346 if (flags & SPI_XFER_END) {
347 /* command without data */
348 priv->command &= ~(CMD_HAS_DATA);
349 }
350 }
351
352 if (flags & SPI_XFER_END) {
353 u32 ccr_reg = _stm32_qspi_gen_ccr(priv);
354 ccr_reg |= STM32_QSPI_CCR_IND_WRITE
355 << STM32_QSPI_CCR_FMODE_SHIFT;
356
357 _stm32_qspi_wait_for_not_busy(priv);
358
359 if (priv->command & CMD_HAS_DATA)
360 _stm32_qspi_set_xfer_length(priv, words);
361
362 _stm32_qspi_start_xfer(priv, ccr_reg);
363
364 debug("%s: write: ccr:0x%08x adr:0x%08x\n",
365 __func__, priv->regs->ccr, priv->regs->ar);
366
367 if (priv->command & CMD_HAS_DATA) {
368 _stm32_qspi_wait_for_ftf(priv);
369
370 debug("%s: words:%d data:", __func__, words);
371
372 int i = 0;
373 while (words > i) {
374 writeb(dout[i], &priv->regs->dr);
375 debug("%02x ", dout[i]);
376 i++;
377 }
378 debug("\n");
379
380 _stm32_qspi_wait_for_complete(priv);
381 } else {
382 _stm32_qspi_wait_for_not_busy(priv);
383 }
384 }
385 } else if (din) {
386 u32 ccr_reg = _stm32_qspi_gen_ccr(priv);
387 ccr_reg |= STM32_QSPI_CCR_IND_READ
388 << STM32_QSPI_CCR_FMODE_SHIFT;
389
390 _stm32_qspi_wait_for_not_busy(priv);
391
392 _stm32_qspi_set_xfer_length(priv, words);
393
394 _stm32_qspi_start_xfer(priv, ccr_reg);
395
396 debug("%s: read: ccr:0x%08x adr:0x%08x len:%d\n", __func__,
397 priv->regs->ccr, priv->regs->ar, priv->regs->dlr);
398
399 debug("%s: data:", __func__);
400
401 int i = 0;
402 while (words > i) {
403 din[i] = readb(&priv->regs->dr);
404 debug("%02x ", din[i]);
405 i++;
406 }
407 debug("\n");
408 }
409
410 return 0;
411 }
412
stm32_qspi_ofdata_to_platdata(struct udevice * bus)413 static int stm32_qspi_ofdata_to_platdata(struct udevice *bus)
414 {
415 struct fdt_resource res_regs, res_mem;
416 struct stm32_qspi_platdata *plat = bus->platdata;
417 const void *blob = gd->fdt_blob;
418 int node = dev_of_offset(bus);
419 int ret;
420
421 ret = fdt_get_named_resource(blob, node, "reg", "reg-names",
422 "QuadSPI", &res_regs);
423 if (ret) {
424 debug("Error: can't get regs base addresses(ret = %d)!\n", ret);
425 return -ENOMEM;
426 }
427 ret = fdt_get_named_resource(blob, node, "reg", "reg-names",
428 "QuadSPI-memory", &res_mem);
429 if (ret) {
430 debug("Error: can't get mmap base address(ret = %d)!\n", ret);
431 return -ENOMEM;
432 }
433
434 plat->max_hz = fdtdec_get_int(blob, node, "spi-max-frequency",
435 STM32_QSPI_DEFAULT_SCK_FREQ);
436
437 plat->base = res_regs.start;
438 plat->memory_map = res_mem.start;
439
440 debug("%s: regs=<0x%x> mapped=<0x%x>, max-frequency=%d\n",
441 __func__,
442 plat->base,
443 plat->memory_map,
444 plat->max_hz
445 );
446
447 return 0;
448 }
449
stm32_qspi_probe(struct udevice * bus)450 static int stm32_qspi_probe(struct udevice *bus)
451 {
452 struct stm32_qspi_platdata *plat = dev_get_platdata(bus);
453 struct stm32_qspi_priv *priv = dev_get_priv(bus);
454 struct dm_spi_bus *dm_spi_bus;
455
456 dm_spi_bus = bus->uclass_priv;
457
458 dm_spi_bus->max_hz = plat->max_hz;
459
460 priv->regs = (struct stm32_qspi_regs *)(uintptr_t)plat->base;
461
462 priv->max_hz = plat->max_hz;
463
464 #ifdef CONFIG_CLK
465 int ret;
466 struct clk clk;
467 ret = clk_get_by_index(bus, 0, &clk);
468 if (ret < 0)
469 return ret;
470
471 ret = clk_enable(&clk);
472
473 if (ret) {
474 dev_err(bus, "failed to enable clock\n");
475 return ret;
476 }
477
478 priv->clock_rate = clk_get_rate(&clk);
479 if (priv->clock_rate < 0) {
480 clk_disable(&clk);
481 return priv->clock_rate;
482 }
483
484 #endif
485
486 setbits_le32(&priv->regs->cr, STM32_QSPI_CR_SSHIFT);
487
488 return 0;
489 }
490
stm32_qspi_remove(struct udevice * bus)491 static int stm32_qspi_remove(struct udevice *bus)
492 {
493 return 0;
494 }
495
stm32_qspi_claim_bus(struct udevice * dev)496 static int stm32_qspi_claim_bus(struct udevice *dev)
497 {
498 struct stm32_qspi_priv *priv;
499 struct udevice *bus;
500 struct spi_flash *flash;
501
502 bus = dev->parent;
503 priv = dev_get_priv(bus);
504 flash = dev_get_uclass_priv(dev);
505
506 _stm32_qspi_set_flash_size(priv, flash->size);
507
508 _stm32_qspi_enable(priv);
509
510 return 0;
511 }
512
stm32_qspi_release_bus(struct udevice * dev)513 static int stm32_qspi_release_bus(struct udevice *dev)
514 {
515 struct stm32_qspi_priv *priv;
516 struct udevice *bus;
517
518 bus = dev->parent;
519 priv = dev_get_priv(bus);
520
521 _stm32_qspi_disable(priv);
522
523 return 0;
524 }
525
stm32_qspi_xfer(struct udevice * dev,unsigned int bitlen,const void * dout,void * din,unsigned long flags)526 static int stm32_qspi_xfer(struct udevice *dev, unsigned int bitlen,
527 const void *dout, void *din, unsigned long flags)
528 {
529 struct stm32_qspi_priv *priv;
530 struct udevice *bus;
531 struct spi_flash *flash;
532
533 bus = dev->parent;
534 priv = dev_get_priv(bus);
535 flash = dev_get_uclass_priv(dev);
536
537 return _stm32_qspi_xfer(priv, flash, bitlen, (const u8 *)dout,
538 (u8 *)din, flags);
539 }
540
stm32_qspi_set_speed(struct udevice * bus,uint speed)541 static int stm32_qspi_set_speed(struct udevice *bus, uint speed)
542 {
543 struct stm32_qspi_platdata *plat = bus->platdata;
544 struct stm32_qspi_priv *priv = dev_get_priv(bus);
545
546 if (speed > plat->max_hz)
547 speed = plat->max_hz;
548
549 u32 qspi_clk = priv->clock_rate;
550 u32 prescaler = 255;
551 if (speed > 0) {
552 prescaler = DIV_ROUND_UP(qspi_clk, speed) - 1;
553 if (prescaler > 255)
554 prescaler = 255;
555 else if (prescaler < 0)
556 prescaler = 0;
557 }
558
559 u32 csht = DIV_ROUND_UP((5 * qspi_clk) / (prescaler + 1), 100000000);
560 csht = (csht - 1) & STM32_QSPI_DCR_CSHT_MASK;
561
562 _stm32_qspi_wait_for_not_busy(priv);
563
564 clrsetbits_le32(&priv->regs->cr,
565 STM32_QSPI_CR_PRESCALER_MASK <<
566 STM32_QSPI_CR_PRESCALER_SHIFT,
567 prescaler << STM32_QSPI_CR_PRESCALER_SHIFT);
568
569
570 clrsetbits_le32(&priv->regs->dcr,
571 STM32_QSPI_DCR_CSHT_MASK << STM32_QSPI_DCR_CSHT_SHIFT,
572 csht << STM32_QSPI_DCR_CSHT_SHIFT);
573
574 debug("%s: regs=%p, speed=%d\n", __func__, priv->regs,
575 (qspi_clk / (prescaler + 1)));
576
577 return 0;
578 }
579
stm32_qspi_set_mode(struct udevice * bus,uint mode)580 static int stm32_qspi_set_mode(struct udevice *bus, uint mode)
581 {
582 struct stm32_qspi_priv *priv = dev_get_priv(bus);
583
584 _stm32_qspi_wait_for_not_busy(priv);
585
586 if ((mode & SPI_CPHA) && (mode & SPI_CPOL))
587 setbits_le32(&priv->regs->dcr, STM32_QSPI_DCR_CKMODE);
588 else if (!(mode & SPI_CPHA) && !(mode & SPI_CPOL))
589 clrbits_le32(&priv->regs->dcr, STM32_QSPI_DCR_CKMODE);
590 else
591 return -ENODEV;
592
593 if (mode & SPI_CS_HIGH)
594 return -ENODEV;
595
596 if (mode & SPI_RX_QUAD)
597 priv->mode |= SPI_RX_QUAD;
598 else if (mode & SPI_RX_DUAL)
599 priv->mode |= SPI_RX_DUAL;
600 else
601 priv->mode &= ~(SPI_RX_QUAD | SPI_RX_DUAL);
602
603 if (mode & SPI_TX_QUAD)
604 priv->mode |= SPI_TX_QUAD;
605 else if (mode & SPI_TX_DUAL)
606 priv->mode |= SPI_TX_DUAL;
607 else
608 priv->mode &= ~(SPI_TX_QUAD | SPI_TX_DUAL);
609
610 debug("%s: regs=%p, mode=%d rx: ", __func__, priv->regs, mode);
611
612 if (mode & SPI_RX_QUAD)
613 debug("quad, tx: ");
614 else if (mode & SPI_RX_DUAL)
615 debug("dual, tx: ");
616 else
617 debug("single, tx: ");
618
619 if (mode & SPI_TX_QUAD)
620 debug("quad\n");
621 else if (mode & SPI_TX_DUAL)
622 debug("dual\n");
623 else
624 debug("single\n");
625
626 return 0;
627 }
628
629 static const struct dm_spi_ops stm32_qspi_ops = {
630 .claim_bus = stm32_qspi_claim_bus,
631 .release_bus = stm32_qspi_release_bus,
632 .xfer = stm32_qspi_xfer,
633 .set_speed = stm32_qspi_set_speed,
634 .set_mode = stm32_qspi_set_mode,
635 };
636
637 static const struct udevice_id stm32_qspi_ids[] = {
638 { .compatible = "st,stm32-qspi" },
639 { }
640 };
641
642 U_BOOT_DRIVER(stm32_qspi) = {
643 .name = "stm32_qspi",
644 .id = UCLASS_SPI,
645 .of_match = stm32_qspi_ids,
646 .ops = &stm32_qspi_ops,
647 .ofdata_to_platdata = stm32_qspi_ofdata_to_platdata,
648 .platdata_auto_alloc_size = sizeof(struct stm32_qspi_platdata),
649 .priv_auto_alloc_size = sizeof(struct stm32_qspi_priv),
650 .probe = stm32_qspi_probe,
651 .remove = stm32_qspi_remove,
652 };
653