1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * (C) Copyright 2018 Rockchip Electronics Co., Ltd 4 */ 5 6 #ifndef __ROCKCHIP_I2S_H__ 7 #define __ROCKCHIP_I2S_H__ 8 9 /* I2S REGS */ 10 #define I2S_TXCR (0x0000) 11 #define I2S_RXCR (0x0004) 12 #define I2S_CKR (0x0008) 13 #define I2S_FIFOLR (0x000c) 14 #define I2S_DMACR (0x0010) 15 #define I2S_INTCR (0x0014) 16 #define I2S_INTSR (0x0018) 17 #define I2S_XFER (0x001c) 18 #define I2S_CLR (0x0020) 19 #define I2S_TXDR (0x0024) 20 #define I2S_RXDR (0x0028) 21 22 /* 23 * TXCR 24 * transmit operation control register 25 */ 26 #define I2S_TXCR_RCNT_SHIFT 17 27 #define I2S_TXCR_RCNT_MASK (0x3f << I2S_TXCR_RCNT_SHIFT) 28 #define I2S_TXCR_CSR_SHIFT 15 29 #define I2S_TXCR_CSR(x) (x << I2S_TXCR_CSR_SHIFT) 30 #define I2S_TXCR_CHN_2 (0 << I2S_TXCR_CSR_SHIFT) 31 #define I2S_TXCR_CHN_4 (1 << I2S_TXCR_CSR_SHIFT) 32 #define I2S_TXCR_CHN_6 (2 << I2S_TXCR_CSR_SHIFT) 33 #define I2S_TXCR_CHN_8 (3 << I2S_TXCR_CSR_SHIFT) 34 #define I2S_TXCR_CSR_MASK (3 << I2S_TXCR_CSR_SHIFT) 35 #define I2S_TXCR_HWT BIT(14) 36 #define I2S_TXCR_SJM_SHIFT 12 37 #define I2S_TXCR_SJM_R (0 << I2S_TXCR_SJM_SHIFT) 38 #define I2S_TXCR_SJM_L (1 << I2S_TXCR_SJM_SHIFT) 39 #define I2S_TXCR_FBM_SHIFT 11 40 #define I2S_TXCR_FBM_MSB (0 << I2S_TXCR_FBM_SHIFT) 41 #define I2S_TXCR_FBM_LSB (1 << I2S_TXCR_FBM_SHIFT) 42 #define I2S_TXCR_IBM_SHIFT 9 43 #define I2S_TXCR_IBM_NORMAL (0 << I2S_TXCR_IBM_SHIFT) 44 #define I2S_TXCR_IBM_LSJM (1 << I2S_TXCR_IBM_SHIFT) 45 #define I2S_TXCR_IBM_RSJM (2 << I2S_TXCR_IBM_SHIFT) 46 #define I2S_TXCR_IBM_MASK (3 << I2S_TXCR_IBM_SHIFT) 47 #define I2S_TXCR_PBM_SHIFT 7 48 #define I2S_TXCR_PBM_MODE(x) (x << I2S_TXCR_PBM_SHIFT) 49 #define I2S_TXCR_PBM_MASK (3 << I2S_TXCR_PBM_SHIFT) 50 #define I2S_TXCR_TFS_SHIFT 5 51 #define I2S_TXCR_TFS_I2S (0 << I2S_TXCR_TFS_SHIFT) 52 #define I2S_TXCR_TFS_PCM (1 << I2S_TXCR_TFS_SHIFT) 53 #define I2S_TXCR_TFS_MASK (1 << I2S_TXCR_TFS_SHIFT) 54 #define I2S_TXCR_VDW_SHIFT 0 55 #define I2S_TXCR_VDW(x) ((x - 1) << I2S_TXCR_VDW_SHIFT) 56 #define I2S_TXCR_VDW_MASK (0x1f << I2S_TXCR_VDW_SHIFT) 57 58 /* 59 * RXCR 60 * receive operation control register 61 */ 62 #define I2S_RXCR_CSR_SHIFT 15 63 #define I2S_RXCR_CSR(x) (x << I2S_RXCR_CSR_SHIFT) 64 #define I2S_RXCR_CSR_MASK (3 << I2S_RXCR_CSR_SHIFT) 65 #define I2S_RXCR_HWT BIT(14) 66 #define I2S_RXCR_SJM_SHIFT 12 67 #define I2S_RXCR_SJM_R (0 << I2S_RXCR_SJM_SHIFT) 68 #define I2S_RXCR_SJM_L (1 << I2S_RXCR_SJM_SHIFT) 69 #define I2S_RXCR_FBM_SHIFT 11 70 #define I2S_RXCR_FBM_MSB (0 << I2S_RXCR_FBM_SHIFT) 71 #define I2S_RXCR_FBM_LSB (1 << I2S_RXCR_FBM_SHIFT) 72 #define I2S_RXCR_IBM_SHIFT 9 73 #define I2S_RXCR_IBM_NORMAL (0 << I2S_RXCR_IBM_SHIFT) 74 #define I2S_RXCR_IBM_LSJM (1 << I2S_RXCR_IBM_SHIFT) 75 #define I2S_RXCR_IBM_RSJM (2 << I2S_RXCR_IBM_SHIFT) 76 #define I2S_RXCR_IBM_MASK (3 << I2S_RXCR_IBM_SHIFT) 77 #define I2S_RXCR_PBM_SHIFT 7 78 #define I2S_RXCR_PBM_MODE(x) (x << I2S_RXCR_PBM_SHIFT) 79 #define I2S_RXCR_PBM_MASK (3 << I2S_RXCR_PBM_SHIFT) 80 #define I2S_RXCR_TFS_SHIFT 5 81 #define I2S_RXCR_TFS_I2S (0 << I2S_RXCR_TFS_SHIFT) 82 #define I2S_RXCR_TFS_PCM (1 << I2S_RXCR_TFS_SHIFT) 83 #define I2S_RXCR_TFS_MASK (1 << I2S_RXCR_TFS_SHIFT) 84 #define I2S_RXCR_VDW_SHIFT 0 85 #define I2S_RXCR_VDW(x) ((x - 1) << I2S_RXCR_VDW_SHIFT) 86 #define I2S_RXCR_VDW_MASK (0x1f << I2S_RXCR_VDW_SHIFT) 87 88 /* 89 * CKR 90 * clock generation register 91 */ 92 #define I2S_CKR_MSS_SHIFT 27 93 #define I2S_CKR_MSS_MASTER (0 << I2S_CKR_MSS_SHIFT) 94 #define I2S_CKR_MSS_SLAVE (1 << I2S_CKR_MSS_SHIFT) 95 #define I2S_CKR_MSS_MASK (1 << I2S_CKR_MSS_SHIFT) 96 #define I2S_CKR_CKP_SHIFT 26 97 #define I2S_CKR_CKP_NEG (0 << I2S_CKR_CKP_SHIFT) 98 #define I2S_CKR_CKP_POS (1 << I2S_CKR_CKP_SHIFT) 99 #define I2S_CKR_RLP_SHIFT 25 100 #define I2S_CKR_RLP_NORMAL (0 << I2S_CKR_RLP_SHIFT) 101 #define I2S_CKR_RLP_OPPSITE (1 << I2S_CKR_RLP_SHIFT) 102 #define I2S_CKR_TLP_SHIFT 24 103 #define I2S_CKR_TLP_NORMAL (0 << I2S_CKR_TLP_SHIFT) 104 #define I2S_CKR_TLP_OPPSITE (1 << I2S_CKR_TLP_SHIFT) 105 #define I2S_CKR_MDIV_SHIFT 16 106 #define I2S_CKR_MDIV(x) (((x) - 1) << I2S_CKR_MDIV_SHIFT) 107 #define I2S_CKR_MDIV_MASK (0xff << I2S_CKR_MDIV_SHIFT) 108 #define I2S_CKR_RSD_SHIFT 8 109 #define I2S_CKR_RSD(x) (((x) - 1) << I2S_CKR_RSD_SHIFT) 110 #define I2S_CKR_RSD_MASK (0xff << I2S_CKR_RSD_SHIFT) 111 #define I2S_CKR_TSD_SHIFT 0 112 #define I2S_CKR_TSD(x) (((x) - 1) << I2S_CKR_TSD_SHIFT) 113 #define I2S_CKR_TSD_MASK (0xff << I2S_CKR_TSD_SHIFT) 114 115 /* 116 * FIFOLR 117 * FIFO level register 118 */ 119 #define I2S_FIFOLR_RFL_SHIFT 24 120 #define I2S_FIFOLR_RFL_MASK (0x3f << I2S_FIFOLR_RFL_SHIFT) 121 #define I2S_FIFOLR_TFL3_SHIFT 18 122 #define I2S_FIFOLR_TFL3_MASK (0x3f << I2S_FIFOLR_TFL3_SHIFT) 123 #define I2S_FIFOLR_TFL2_SHIFT 12 124 #define I2S_FIFOLR_TFL2_MASK (0x3f << I2S_FIFOLR_TFL2_SHIFT) 125 #define I2S_FIFOLR_TFL1_SHIFT 6 126 #define I2S_FIFOLR_TFL1_MASK (0x3f << I2S_FIFOLR_TFL1_SHIFT) 127 #define I2S_FIFOLR_TFL0_SHIFT 0 128 #define I2S_FIFOLR_TFL0_MASK (0x3f << I2S_FIFOLR_TFL0_SHIFT) 129 130 /* 131 * DMACR 132 * DMA control register 133 */ 134 #define I2S_DMACR_RDE_SHIFT 24 135 #define I2S_DMACR_RDE_DISABLE (0 << I2S_DMACR_RDE_SHIFT) 136 #define I2S_DMACR_RDE_ENABLE (1 << I2S_DMACR_RDE_SHIFT) 137 #define I2S_DMACR_RDE_MASK (1 << I2S_DMACR_RDE_SHIFT) 138 #define I2S_DMACR_RDL_SHIFT 16 139 #define I2S_DMACR_RDL(x) ((x - 1) << I2S_DMACR_RDL_SHIFT) 140 #define I2S_DMACR_RDL_MASK (0x1f << I2S_DMACR_RDL_SHIFT) 141 #define I2S_DMACR_TDE_SHIFT 8 142 #define I2S_DMACR_TDE_DISABLE (0 << I2S_DMACR_TDE_SHIFT) 143 #define I2S_DMACR_TDE_ENABLE (1 << I2S_DMACR_TDE_SHIFT) 144 #define I2S_DMACR_TDE_MASK (1 << I2S_DMACR_TDE_SHIFT) 145 #define I2S_DMACR_TDL_SHIFT 0 146 #define I2S_DMACR_TDL(x) ((x) << I2S_DMACR_TDL_SHIFT) 147 #define I2S_DMACR_TDL_MASK (0x1f << I2S_DMACR_TDL_SHIFT) 148 149 /* 150 * INTCR 151 * interrupt control register 152 */ 153 #define I2S_INTCR_RFT_SHIFT 20 154 #define I2S_INTCR_RFT(x) ((x - 1) << I2S_INTCR_RFT_SHIFT) 155 #define I2S_INTCR_RXOIC BIT(18) 156 #define I2S_INTCR_RXOIE_SHIFT 17 157 #define I2S_INTCR_RXOIE_DISABLE (0 << I2S_INTCR_RXOIE_SHIFT) 158 #define I2S_INTCR_RXOIE_ENABLE (1 << I2S_INTCR_RXOIE_SHIFT) 159 #define I2S_INTCR_RXFIE_SHIFT 16 160 #define I2S_INTCR_RXFIE_DISABLE (0 << I2S_INTCR_RXFIE_SHIFT) 161 #define I2S_INTCR_RXFIE_ENABLE (1 << I2S_INTCR_RXFIE_SHIFT) 162 #define I2S_INTCR_TFT_SHIFT 4 163 #define I2S_INTCR_TFT(x) ((x - 1) << I2S_INTCR_TFT_SHIFT) 164 #define I2S_INTCR_TFT_MASK (0x1f << I2S_INTCR_TFT_SHIFT) 165 #define I2S_INTCR_TXUIC BIT(2) 166 #define I2S_INTCR_TXUIE_SHIFT 1 167 #define I2S_INTCR_TXUIE_DISABLE (0 << I2S_INTCR_TXUIE_SHIFT) 168 #define I2S_INTCR_TXUIE_ENABLE (1 << I2S_INTCR_TXUIE_SHIFT) 169 170 /* 171 * INTSR 172 * interrupt status register 173 */ 174 #define I2S_INTSR_RXOI_SHIFT 17 175 #define I2S_INTSR_RXOI_INA (0 << I2S_INTSR_RXOI_SHIFT) 176 #define I2S_INTSR_RXOI_ACT (1 << I2S_INTSR_RXOI_SHIFT) 177 #define I2S_INTSR_RXFI_SHIFT 16 178 #define I2S_INTSR_RXFI_INA (0 << I2S_INTSR_RXFI_SHIFT) 179 #define I2S_INTSR_RXFI_ACT (1 << I2S_INTSR_RXFI_SHIFT) 180 #define I2S_INTSR_TXUI_SHIFT 1 181 #define I2S_INTSR_TXUI_INA (0 << I2S_INTSR_TXUI_SHIFT) 182 #define I2S_INTSR_TXUI_ACT (1 << I2S_INTSR_TXUI_SHIFT) 183 #define I2S_INTSR_TXEI_SHIFT 0 184 #define I2S_INTSR_TXEI_INA (0 << I2S_INTSR_TXEI_SHIFT) 185 #define I2S_INTSR_TXEI_ACT (1 << I2S_INTSR_TXEI_SHIFT) 186 187 /* 188 * XFER 189 * Transfer start register 190 */ 191 #define I2S_XFER_RXS_SHIFT 1 192 #define I2S_XFER_RXS_STOP (0 << I2S_XFER_RXS_SHIFT) 193 #define I2S_XFER_RXS_START (1 << I2S_XFER_RXS_SHIFT) 194 #define I2S_XFER_RXS_MASK (1 << I2S_XFER_RXS_SHIFT) 195 #define I2S_XFER_TXS_SHIFT 0 196 #define I2S_XFER_TXS_STOP (0 << I2S_XFER_TXS_SHIFT) 197 #define I2S_XFER_TXS_START (1 << I2S_XFER_TXS_SHIFT) 198 #define I2S_XFER_TXS_MASK (1 << I2S_XFER_TXS_SHIFT) 199 200 /* 201 * CLR 202 * clear SCLK domain logic register 203 */ 204 #define I2S_CLR_RXC BIT(1) 205 #define I2S_CLR_RXC_MASK BIT(1) 206 #define I2S_CLR_TXC BIT(0) 207 #define I2S_CLR_TXC_MASK BIT(0) 208 209 #endif 210