1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * (C) Copyright 2018 Rockchip Electronics Co., Ltd 4 */ 5 6 #ifndef __RK817_CODEC_H__ 7 #define __RK817_CODEC_H__ 8 9 /* codec register */ 10 #define RK817_CODEC_BASE 0x0000 11 12 #define RK817_CODEC_DTOP_VUCTL (RK817_CODEC_BASE + 0x12) 13 #define RK817_CODEC_DTOP_VUCTIME (RK817_CODEC_BASE + 0x13) 14 #define RK817_CODEC_DTOP_LPT_SRST (RK817_CODEC_BASE + 0x14) 15 #define RK817_CODEC_DTOP_DIGEN_CLKE (RK817_CODEC_BASE + 0x15) 16 #define RK817_CODEC_AREF_RTCFG0 (RK817_CODEC_BASE + 0x16) 17 #define RK817_CODEC_AREF_RTCFG1 (RK817_CODEC_BASE + 0x17) 18 #define RK817_CODEC_AADC_CFG0 (RK817_CODEC_BASE + 0x18) 19 #define RK817_CODEC_AADC_CFG1 (RK817_CODEC_BASE + 0x19) 20 #define RK817_CODEC_DADC_VOLL (RK817_CODEC_BASE + 0x1a) 21 #define RK817_CODEC_DADC_VOLR (RK817_CODEC_BASE + 0x1b) 22 #define RK817_CODEC_DADC_SR_ACL0 (RK817_CODEC_BASE + 0x1e) 23 #define RK817_CODEC_DADC_ALC1 (RK817_CODEC_BASE + 0x1f) 24 #define RK817_CODEC_DADC_ALC2 (RK817_CODEC_BASE + 0x20) 25 #define RK817_CODEC_DADC_NG (RK817_CODEC_BASE + 0x21) 26 #define RK817_CODEC_DADC_HPF (RK817_CODEC_BASE + 0x22) 27 #define RK817_CODEC_DADC_RVOLL (RK817_CODEC_BASE + 0x23) 28 #define RK817_CODEC_DADC_RVOLR (RK817_CODEC_BASE + 0x24) 29 #define RK817_CODEC_AMIC_CFG0 (RK817_CODEC_BASE + 0x27) 30 #define RK817_CODEC_AMIC_CFG1 (RK817_CODEC_BASE + 0x28) 31 #define RK817_CODEC_DMIC_PGA_GAIN (RK817_CODEC_BASE + 0x29) 32 #define RK817_CODEC_DMIC_LMT1 (RK817_CODEC_BASE + 0x2a) 33 #define RK817_CODEC_DMIC_LMT2 (RK817_CODEC_BASE + 0x2b) 34 #define RK817_CODEC_DMIC_NG1 (RK817_CODEC_BASE + 0x2c) 35 #define RK817_CODEC_DMIC_NG2 (RK817_CODEC_BASE + 0x2d) 36 #define RK817_CODEC_ADAC_CFG0 (RK817_CODEC_BASE + 0x2e) 37 #define RK817_CODEC_ADAC_CFG1 (RK817_CODEC_BASE + 0x2f) 38 #define RK817_CODEC_DDAC_POPD_DACST (RK817_CODEC_BASE + 0x30) 39 #define RK817_CODEC_DDAC_VOLL (RK817_CODEC_BASE + 0x31) 40 #define RK817_CODEC_DDAC_VOLR (RK817_CODEC_BASE + 0x32) 41 #define RK817_CODEC_DDAC_SR_LMT0 (RK817_CODEC_BASE + 0x35) 42 #define RK817_CODEC_DDAC_LMT1 (RK817_CODEC_BASE + 0x36) 43 #define RK817_CODEC_DDAC_LMT2 (RK817_CODEC_BASE + 0x37) 44 #define RK817_CODEC_DDAC_MUTE_MIXCTL (RK817_CODEC_BASE + 0x38) 45 #define RK817_CODEC_DDAC_RVOLL (RK817_CODEC_BASE + 0x39) 46 #define RK817_CODEC_DDAC_RVOLR (RK817_CODEC_BASE + 0x3a) 47 #define RK817_CODEC_AHP_ANTI0 (RK817_CODEC_BASE + 0x3b) 48 #define RK817_CODEC_AHP_ANTI1 (RK817_CODEC_BASE + 0x3c) 49 #define RK817_CODEC_AHP_CFG0 (RK817_CODEC_BASE + 0x3d) 50 #define RK817_CODEC_AHP_CFG1 (RK817_CODEC_BASE + 0x3e) 51 #define RK817_CODEC_AHP_CP (RK817_CODEC_BASE + 0x3f) 52 #define RK817_CODEC_ACLASSD_CFG1 (RK817_CODEC_BASE + 0x40) 53 #define RK817_CODEC_ACLASSD_CFG2 (RK817_CODEC_BASE + 0x41) 54 #define RK817_CODEC_APLL_CFG0 (RK817_CODEC_BASE + 0x42) 55 #define RK817_CODEC_APLL_CFG1 (RK817_CODEC_BASE + 0x43) 56 #define RK817_CODEC_APLL_CFG2 (RK817_CODEC_BASE + 0x44) 57 #define RK817_CODEC_APLL_CFG3 (RK817_CODEC_BASE + 0x45) 58 #define RK817_CODEC_APLL_CFG4 (RK817_CODEC_BASE + 0x46) 59 #define RK817_CODEC_APLL_CFG5 (RK817_CODEC_BASE + 0x47) 60 #define RK817_CODEC_DI2S_CKM (RK817_CODEC_BASE + 0x48) 61 #define RK817_CODEC_DI2S_RSD (RK817_CODEC_BASE + 0x49) 62 #define RK817_CODEC_DI2S_RXCR1 (RK817_CODEC_BASE + 0x4a) 63 #define RK817_CODEC_DI2S_RXCR2 (RK817_CODEC_BASE + 0x4b) 64 #define RK817_CODEC_DI2S_RXCMD_TSD (RK817_CODEC_BASE + 0x4c) 65 #define RK817_CODEC_DI2S_TXCR1 (RK817_CODEC_BASE + 0x4d) 66 #define RK817_CODEC_DI2S_TXCR2 (RK817_CODEC_BASE + 0x4e) 67 #define RK817_CODEC_DI2S_TXCR3_TXCMD (RK817_CODEC_BASE + 0x4f) 68 69 /* RK817_CODEC_DTOP_DIGEN_CLKE */ 70 #define ADC_DIG_CLK_MASK (0xf << 4) 71 #define ADC_DIG_CLK_SFT 4 72 #define ADC_DIG_CLK_DIS (0x0 << 4) 73 #define ADC_DIG_CLK_EN (0xf << 4) 74 75 #define DAC_DIG_CLK_MASK (0xf << 0) 76 #define DAC_DIG_CLK_SFT 0 77 #define DAC_DIG_CLK_DIS (0x0 << 0) 78 #define DAC_DIG_CLK_EN (0xf << 0) 79 80 /* RK817_CODEC_APLL_CFG5 */ 81 #define PLL_PW_DOWN (0x01 << 0) 82 #define PLL_PW_UP (0x00 << 0) 83 84 /* RK817_CODEC_DI2S_CKM */ 85 #define PDM_EN_MASK (0x1 << 3) 86 #define PDM_EN_SFT 3 87 #define PDM_EN_DISABLE (0x0 << 3) 88 #define PDM_EN_ENABLE (0x1 << 3) 89 90 #define SCK_EN_ENABLE (0x1 << 2) 91 #define SCK_EN_DISABLE (0x0 << 2) 92 93 #define RK817_I2S_MODE_MASK (0x1 << 0) 94 #define RK817_I2S_MODE_SFT 0 95 #define RK817_I2S_MODE_MST (0x1 << 0) 96 #define RK817_I2S_MODE_SLV (0x0 << 0) 97 98 /* RK817_CODEC_DDAC_MUTE_MIXCTL */ 99 #define DACMT_ENABLE (0x1 << 0) 100 #define DACMT_DISABLE (0x0 << 0) 101 102 /* RK817_CODEC_DI2S_RXCR2 */ 103 #define VDW_RX_24BITS (0x17) 104 #define VDW_RX_16BITS (0x0f) 105 /* RK817_CODEC_DI2S_TXCR2 */ 106 #define VDW_TX_24BITS (0x17) 107 #define VDW_TX_16BITS (0x0f) 108 109 /* RK817_CODEC_AHP_CFG1 */ 110 #define HP_ANTIPOP_ENABLE (0x1 << 4) 111 #define HP_ANTIPOP_DISABLE (0x0 << 4) 112 113 /* RK817_CODEC_ADAC_CFG1 */ 114 #define PWD_DACBIAS_MASK (0x1 << 3) 115 #define PWD_DACBIAS_SFT 3 116 #define PWD_DACBIAS_DOWN (0x1 << 3) 117 #define PWD_DACBIAS_ON (0x0 << 3) 118 119 #define PWD_DACD_MASK (0x1 << 2) 120 #define PWD_DACD_SFT 2 121 #define PWD_DACD_DOWN (0x1 << 2) 122 #define PWD_DACD_ON (0x0 << 2) 123 124 #define PWD_DACL_MASK (0x1 << 1) 125 #define PWD_DACL_SFT 1 126 #define PWD_DACL_DOWN (0x1 << 1) 127 #define PWD_DACL_ON (0x0 << 1) 128 129 #define PWD_DACR_MASK (0x1 << 0) 130 #define PWD_DACR_SFT 0 131 #define PWD_DACR_DOWN (0x1 << 0) 132 #define PWD_DACR_ON (0x0 << 0) 133 134 /* RK817_CODEC_AADC_CFG0 */ 135 #define ADC_L_PWD_MASK (0x1 << 7) 136 #define ADC_L_PWD_SFT 7 137 #define ADC_L_PWD_DIS (0x0 << 7) 138 #define ADC_L_PWD_EN (0x1 << 7) 139 140 #define ADC_R_PWD_MASK (0x1 << 6) 141 #define ADC_R_PWD_SFT 6 142 #define ADC_R_PWD_DIS (0x0 << 6) 143 #define ADC_R_PWD_EN (0x1 << 6) 144 145 /* RK817_CODEC_AMIC_CFG0 */ 146 #define MIC_DIFF_MASK (0x1 << 7) 147 #define MIC_DIFF_SFT 7 148 #define MIC_DIFF_DIS (0x0 << 7) 149 #define MIC_DIFF_EN (0x1 << 7) 150 151 #define PWD_PGA_L_MASK (0x1 << 5) 152 #define PWD_PGA_L_SFT 5 153 #define PWD_PGA_L_DIS (0x0 << 5) 154 #define PWD_PGA_L_EN (0x1 << 5) 155 156 #define PWD_PGA_R_MASK (0x1 << 4) 157 #define PWD_PGA_R_SFT 4 158 #define PWD_PGA_R_DIS (0x0 << 4) 159 #define PWD_PGA_R_EN (0x1 << 4) 160 161 enum { 162 RK817_HIFI, 163 RK817_VOICE, 164 }; 165 166 enum { 167 RK817_MONO = 1, 168 RK817_STEREO, 169 }; 170 171 enum { 172 OFF, 173 RCV, 174 SPK_PATH, 175 HP_PATH, 176 HP_NO_MIC, 177 BT, 178 SPK_HP, 179 RING_SPK, 180 RING_HP, 181 RING_HP_NO_MIC, 182 RING_SPK_HP, 183 }; 184 185 enum { 186 MIC_OFF, 187 MAIN_MIC, 188 HANDS_FREE_MIC, 189 BT_SCO_MIC, 190 }; 191 192 struct rk817_reg_val_typ { 193 unsigned int reg; 194 unsigned int value; 195 }; 196 197 struct rk817_init_bit_typ { 198 unsigned int reg; 199 unsigned int power_bit; 200 unsigned int init_bit; 201 }; 202 203 #endif /* __RK817_CODEC_H__ */ 204