1 /*
2 * Copyright (c) 2018 Fuzhou Rockchip Electronics Co., Ltd
3 *
4 * SPDX-License-Identifier: GPL-2.0
5 */
6 #include <linux/compat.h>
7 #include <linux/delay.h>
8 #include <linux/kernel.h>
9 #include <linux/string.h>
10
11 #include "rkflash_debug.h"
12 #include "sfc_nor.h"
13
14 static struct flash_info spi_flash_tbl[] = {
15 /* GD25Q40B */
16 { 0xc84013, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x05, 10, 9, 0 },
17 /* GD25Q32B */
18 { 0xc84016, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0D, 13, 9, 0 },
19 /* GD25Q64B/C/E */
20 { 0xc84017, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 14, 9, 0 },
21 /* GD25Q127C and GD25Q128C/E */
22 { 0xc84018, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 15, 9, 0 },
23 /* GD25Q256B/C/D/E */
24 { 0xc84019, 128, 8, 0x13, 0x12, 0x6C, 0x3E, 0x21, 0xDC, 0x1C, 16, 6, 0 },
25 /* GD25Q512MC */
26 { 0xc84020, 128, 8, 0x13, 0x12, 0x6C, 0x3E, 0x21, 0xDC, 0x1C, 17, 6, 0 },
27 /* GD25LQ64C */
28 { 0xc86017, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0D, 14, 9, 0 },
29 /* GD25LQ128 */
30 { 0xc86018, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0D, 15, 9, 0 },
31 /* GD25LQ32E */
32 { 0xc86016, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0D, 13, 9, 0 },
33 /* GD25B512MEYIG */
34 { 0xc8471A, 128, 8, 0x13, 0x12, 0x6C, 0x34, 0x21, 0xDC, 0x1C, 17, 0, 0 },
35 /* GD55B01GE */
36 { 0xc8471B, 128, 8, 0x13, 0x12, 0x6C, 0x34, 0x21, 0xDC, 0x1C, 18, 0, 0 },
37 /* GD25LQ255E and GD25LQ256C */
38 { 0xc86019, 128, 8, 0x13, 0x12, 0x6C, 0x34, 0x21, 0xDC, 0x1D, 16, 9, 0 },
39 /* GD25LB512MEYIG */
40 { 0xc8671A, 128, 8, 0x13, 0x12, 0x6C, 0x34, 0x21, 0xDC, 0x1C, 17, 0, 0 },
41 /* GD55LB01GEFIRR */
42 { 0xc8671B, 128, 8, 0x13, 0x12, 0x6C, 0x34, 0x21, 0xDC, 0x1C, 18, 0, 0 },
43
44 /* W25Q32JV */
45 { 0xef4016, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 13, 9, 0 },
46 /* W25Q64JVSSIQ */
47 { 0xef4017, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 14, 9, 0 },
48 /* W25Q128FV and W25Q128JV*/
49 { 0xef4018, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 15, 9, 0 },
50 /* W25Q256F/J */
51 { 0xef4019, 128, 8, 0x13, 0x02, 0x6C, 0x32, 0x20, 0xD8, 0x3C, 16, 9, 0 },
52 /* W25Q32JW */
53 { 0xef6016, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 13, 9, 0 },
54 /* W25Q64FWSSIG */
55 { 0xef6017, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 14, 9, 0 },
56 /* W25Q128JWSQ */
57 { 0xef6018, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 15, 9, 0 },
58 /* W25Q256JWEQ*/
59 { 0xef6019, 128, 8, 0x13, 0x02, 0x6C, 0x32, 0x20, 0xD8, 0x3C, 16, 9, 0 },
60 /* W25Q128JVSIM */
61 { 0xef7018, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 15, 9, 0 },
62 /* W25Q256JVEM */
63 { 0xef7019, 128, 8, 0x13, 0x12, 0x6C, 0x34, 0x21, 0xDC, 0x3C, 16, 9, 0 },
64
65 /* MX25L3233FM2I-08G */
66 { 0xc22016, 128, 8, 0x03, 0x02, 0x6B, 0x38, 0x20, 0xD8, 0x0E, 13, 6, 0 },
67 /* MX25L6433F */
68 { 0xc22017, 128, 8, 0x03, 0x02, 0x6B, 0x38, 0x20, 0xD8, 0x0E, 14, 6, 0 },
69 /* MX25L12835E/F MX25L12833FMI-10G */
70 { 0xc22018, 128, 8, 0x03, 0x02, 0x6B, 0x38, 0x20, 0xD8, 0x0E, 15, 6, 0 },
71 /* MX25L25635E/F MX25L25645G MX25L25645GMI-08G */
72 { 0xc22019, 128, 8, 0x13, 0x12, 0x6C, 0x3E, 0x21, 0xDC, 0x1E, 16, 6, 0 },
73 /* MX25L51245GMI */
74 { 0xc2201a, 128, 8, 0x13, 0x12, 0x6C, 0x3E, 0x21, 0xDC, 0x1E, 17, 6, 0 },
75 /* MX25U51245G */
76 { 0xc2253a, 128, 8, 0x0C, 0x12, 0x6C, 0x3E, 0x21, 0xDC, 0x1E, 17, 6, 0 },
77 /* MX25U3232F */
78 { 0xc22536, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0E, 13, 6, 0 },
79 /* MX25U6432F */
80 { 0xc22537, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0E, 14, 6, 0 },
81 /* MX25U12832F */
82 { 0xc22538, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0E, 15, 6, 0 },
83 /* MX25U25645GZ4I-00 */
84 { 0xc22539, 128, 8, 0x13, 0x12, 0x6C, 0x3E, 0x21, 0xDC, 0x1E, 16, 6, 0 },
85
86 /* XM25QH32C */
87 { 0x204016, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 13, 9, 0 },
88 /* XM25QH64C */
89 { 0x204017, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 14, 9, 0 },
90 /* XM25QH128C */
91 { 0x204018, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x05, 15, 9, 0 },
92 /* XM25QH256C */
93 { 0x204019, 128, 8, 0x13, 0x12, 0x6C, 0x34, 0x21, 0xDC, 0x1C, 16, 9, 0 },
94 /* XM25QH64B */
95 { 0x206017, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0D, 14, 6, 0 },
96 /* XM25QH128B */
97 { 0x206018, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0D, 15, 6, 0 },
98 /* XM25QH(QU)256B */
99 { 0x206019, 128, 8, 0x13, 0x12, 0x6C, 0x3E, 0x21, 0xDC, 0x1D, 16, 6, 0 },
100 /* XM25QH64A */
101 { 0x207017, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 14, 0, 0 },
102 /* XM25QU128C */
103 { 0x204118, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 15, 9, 0 },
104 /* XM25QU64C */
105 { 0x204117, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 14, 9, 0 },
106
107 /* XT25F128A XM25QH128A */
108 { 0x207018, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 15, 0, 0 },
109 /* XT25F64BSSIGU-5 XT25F64F */
110 { 0x0b4017, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0D, 14, 9, 0 },
111 /* XT25F128BSSIGU */
112 { 0x0b4018, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0D, 15, 9, 0 },
113 /* XT25F256BSFIGU */
114 { 0x0b4019, 128, 8, 0x13, 0x12, 0x6C, 0x34, 0x21, 0xDC, 0x1C, 16, 9, 0 },
115 /* XT25F32BS XT25F32F */
116 { 0x0b4016, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0D, 13, 9, 0 },
117 /* XT25F16BS */
118 { 0x0b4015, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0D, 12, 9, 0 },
119 /* XT25Q64D */
120 { 0x0b6017, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 14, 9, 0 },
121 /* XT25Q128D */
122 { 0x0b6018, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 15, 9, 0 },
123
124 /* EN25QH64A */
125 { 0x1c7017, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 14, 0, 0 },
126 /* EN25QH128A */
127 { 0x1c7018, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 15, 0, 0 },
128 /* EN25QH32B */
129 { 0x1c7016, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 13, 0, 0 },
130 /* EN25S32A */
131 { 0x1c3816, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 13, 0, 0 },
132 /* EN25S64A */
133 { 0x1c3817, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 14, 0, 0 },
134 /* EN25QH256A */
135 { 0x1c7019, 128, 8, 0x13, 0x12, 0x6C, 0x34, 0x21, 0xDC, 0x1C, 16, 0, 0 },
136 /* EN25QX256A */
137 { 0x1c7119, 128, 8, 0x13, 0x12, 0x6C, 0x34, 0x21, 0xDC, 0x1C, 16, 9, 0 },
138 /* EN25QX128A */
139 { 0x1c7118, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 15, 9, 0 },
140
141 /* P25Q64H */
142 { 0x856017, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 14, 9, 0 },
143 /* P25Q128H */
144 { 0x856018, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 15, 9, 0 },
145 /* P25Q16H-SUH-IT */
146 { 0x856015, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0D, 12, 9, 0 },
147 /* P25Q32SL P25Q32SH-SSH-IT */
148 { 0x856016, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 13, 9, 0 },
149 /* PY25Q64HA */
150 { 0x852017, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 14, 9, 0 },
151 /* PY25Q128H */
152 { 0x852018, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 15, 9, 0 },
153 /* PY25Q256H */
154 { 0x852019, 128, 8, 0x13, 0x12, 0x6C, 0x34, 0x21, 0xDC, 0x1C, 16, 9, 0 },
155
156 /* ZB25VQ64 */
157 { 0x5e4017, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 14, 9, 0 },
158 /* ZB25VQ128 */
159 { 0x5e4018, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 15, 9, 0 },
160 /* ZB25LQ128 */
161 { 0x5e5018, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 15, 9, 0 },
162
163 /* BH25Q128AS */
164 { 0x684018, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 15, 9, 0 },
165 /* BH25Q64BS */
166 { 0x684017, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 14, 9, 0 },
167
168 /* FM25Q128A */
169 { 0xA14018, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 15, 9, 0 },
170 /* FM25Q64-SOB-T-G */
171 { 0xA14017, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 14, 9, 0 },
172 /* FM25Q256I3 */
173 { 0xA14019, 128, 8, 0x13, 0x12, 0x6C, 0x34, 0x21, 0xDC, 0x1C, 16, 9, 0 },
174
175 /* FM25Q64A */
176 { 0xf83217, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0D, 14, 9, 0 },
177 /* FM25M4AA */
178 { 0xf84218, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0D, 15, 9, 0 },
179 /* FM25M64C */
180 { 0xf84317, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0D, 14, 9, 0 },
181
182 /* DS25M4AB-1AIB4 */
183 { 0xe54218, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 15, 9, 0 },
184
185 /* GM25Q128A */
186 { 0x1c4018, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 15, 9, 0 },
187
188 /* IS25LP512M */
189 { 0x9D601A, 128, 8, 0x13, 0x12, 0x6C, 0x34, 0x21, 0xDC, 0x3C, 17, 6, 0 },
190 /* IS25WP512M */
191 { 0x9D701A, 128, 8, 0x13, 0x12, 0x6C, 0x34, 0x21, 0xDC, 0x3C, 17, 6, 0 },
192
193 /* BY25Q256FSEIG */
194 { 0x684919, 128, 8, 0x13, 0x12, 0x6C, 0x34, 0x21, 0xDC, 0x1C, 16, 9, 0 },
195
196 /* NM25Q128EVB */
197 { 0x522118, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 15, 10, 0 },
198 };
199
snor_write_en(void)200 static int snor_write_en(void)
201 {
202 int ret;
203 struct rk_sfc_op op;
204
205 op.sfcmd.d32 = 0;
206 op.sfcmd.b.cmd = CMD_WRITE_EN;
207
208 op.sfctrl.d32 = 0;
209
210 ret = sfc_request(&op, 0, NULL, 0);
211
212 return ret;
213 }
214
snor_reset_device(void)215 int snor_reset_device(void)
216 {
217 struct rk_sfc_op op;
218
219 op.sfcmd.d32 = 0;
220 op.sfcmd.b.cmd = CMD_ENABLE_RESER;
221
222 op.sfctrl.d32 = 0;
223 sfc_request(&op, 0, NULL, 0);
224
225 op.sfcmd.d32 = 0;
226 op.sfcmd.b.cmd = CMD_RESET_DEVICE;
227
228 op.sfctrl.d32 = 0;
229 sfc_request(&op, 0, NULL, 0);
230 /* tRST=30us , delay 1ms here */
231 sfc_delay(1000);
232
233 return SFC_OK;
234 }
235
snor_enter_4byte_mode(void)236 static int snor_enter_4byte_mode(void)
237 {
238 int ret;
239 struct rk_sfc_op op;
240
241 op.sfcmd.d32 = 0;
242 op.sfcmd.b.cmd = CMD_ENTER_4BYTE_MODE;
243
244 op.sfctrl.d32 = 0;
245
246 ret = sfc_request(&op, 0, NULL, 0);
247 return ret;
248 }
249
snor_read_status(u32 reg_index,u8 * status)250 static int snor_read_status(u32 reg_index, u8 *status)
251 {
252 int ret;
253 struct rk_sfc_op op;
254 u8 read_stat_cmd[] = {CMD_READ_STATUS,
255 CMD_READ_STATUS2, CMD_READ_STATUS3};
256 op.sfcmd.d32 = 0;
257 op.sfcmd.b.cmd = read_stat_cmd[reg_index];
258
259 op.sfctrl.d32 = 0;
260 ret = sfc_request(&op, 0, status, 1);
261
262 return ret;
263 }
264
snor_wait_busy(int timeout)265 static int snor_wait_busy(int timeout)
266 {
267 int ret;
268 struct rk_sfc_op op;
269 int i;
270 u32 status;
271
272 op.sfcmd.d32 = 0;
273 op.sfcmd.b.cmd = CMD_READ_STATUS;
274
275 op.sfctrl.d32 = 0;
276
277 for (i = 0; i < timeout; i++) {
278 ret = sfc_request(&op, 0, &status, 1);
279 if (ret != SFC_OK)
280 return ret;
281
282 if ((status & 0x01) == 0)
283 return SFC_OK;
284
285 sfc_delay(1);
286 }
287 rkflash_print_error("%s error %x\n", __func__, timeout);
288
289 return SFC_BUSY_TIMEOUT;
290 }
291
snor_write_status2(u32 reg_index,u8 status)292 static int snor_write_status2(u32 reg_index, u8 status)
293 {
294 int ret;
295 struct rk_sfc_op op;
296 u8 status2[2];
297
298 status2[reg_index] = status;
299 if (reg_index == 0)
300 ret = snor_read_status(2, &status2[1]);
301 else
302 ret = snor_read_status(0, &status2[0]);
303 if (ret != SFC_OK)
304 return ret;
305
306 snor_write_en();
307
308 op.sfcmd.d32 = 0;
309 op.sfcmd.b.cmd = CMD_WRITE_STATUS;
310 op.sfcmd.b.rw = SFC_WRITE;
311
312 op.sfctrl.d32 = 0;
313
314 ret = sfc_request(&op, 0, &status2[0], 2);
315 if (ret != SFC_OK)
316 return ret;
317
318 ret = snor_wait_busy(10000); /* 10ms */
319
320 return ret;
321 }
322
snor_write_status1(u32 reg_index,u8 status)323 static int snor_write_status1(u32 reg_index, u8 status)
324 {
325 int ret;
326 struct rk_sfc_op op;
327 u8 status2[2];
328 u8 read_index;
329
330 status2[reg_index] = status;
331 read_index = (reg_index == 0) ? 1 : 0;
332 ret = snor_read_status(read_index, &status2[read_index]);
333 if (ret != SFC_OK)
334 return ret;
335
336 snor_write_en();
337
338 op.sfcmd.d32 = 0;
339 op.sfcmd.b.cmd = CMD_WRITE_STATUS;
340 op.sfcmd.b.rw = SFC_WRITE;
341
342 op.sfctrl.d32 = 0;
343
344 ret = sfc_request(&op, 0, &status2[0], 2);
345 if (ret != SFC_OK)
346 return ret;
347
348 ret = snor_wait_busy(10000); /* 10ms */
349
350 return ret;
351 }
352
snor_write_status(u32 reg_index,u8 status)353 static int snor_write_status(u32 reg_index, u8 status)
354 {
355 int ret;
356 struct rk_sfc_op op;
357 u8 write_stat_cmd[] = {CMD_WRITE_STATUS,
358 CMD_WRITE_STATUS2, CMD_WRITE_STATUS3};
359 snor_write_en();
360 op.sfcmd.d32 = 0;
361 op.sfcmd.b.cmd = write_stat_cmd[reg_index];
362 op.sfcmd.b.rw = SFC_WRITE;
363
364 op.sfctrl.d32 = 0;
365
366 ret = sfc_request(&op, 0, &status, 1);
367 if (ret != SFC_OK)
368 return ret;
369
370 ret = snor_wait_busy(10000); /* 10ms */
371
372 return ret;
373 }
374
snor_erase(struct SFNOR_DEV * p_dev,u32 addr,enum NOR_ERASE_TYPE erase_type)375 int snor_erase(struct SFNOR_DEV *p_dev,
376 u32 addr,
377 enum NOR_ERASE_TYPE erase_type)
378 {
379 int ret;
380 struct rk_sfc_op op;
381 int timeout[] = {400, 2000, 40000}; /* ms */
382
383 rkflash_print_dio("%s %x %x\n", __func__, addr, erase_type);
384
385 if (erase_type > ERASE_CHIP)
386 return SFC_PARAM_ERR;
387
388 op.sfcmd.d32 = 0;
389 if (erase_type == ERASE_BLOCK64K)
390 op.sfcmd.b.cmd = p_dev->blk_erase_cmd;
391 else if (erase_type == ERASE_SECTOR)
392 op.sfcmd.b.cmd = p_dev->sec_erase_cmd;
393 else
394 op.sfcmd.b.cmd = CMD_CHIP_ERASE;
395
396 op.sfcmd.b.addrbits = (erase_type != ERASE_CHIP) ?
397 SFC_ADDR_24BITS : SFC_ADDR_0BITS;
398 if (p_dev->addr_mode == ADDR_MODE_4BYTE && erase_type != ERASE_CHIP)
399 op.sfcmd.b.addrbits = SFC_ADDR_32BITS;
400 op.sfcmd.b.rw = SFC_WRITE;
401
402 op.sfctrl.d32 = 0;
403
404 snor_write_en();
405
406 ret = sfc_request(&op, addr, NULL, 0);
407 if (ret != SFC_OK)
408 return ret;
409
410 ret = snor_wait_busy(timeout[erase_type] * 1000);
411 return ret;
412 }
413
snor_prog_page(struct SFNOR_DEV * p_dev,u32 addr,void * p_data,u32 size)414 int snor_prog_page(struct SFNOR_DEV *p_dev,
415 u32 addr,
416 void *p_data,
417 u32 size)
418 {
419 int ret;
420 struct rk_sfc_op op;
421
422 rkflash_print_dio("%s %x %x\n", __func__, addr, *(u32 *)(p_data));
423
424 op.sfcmd.d32 = 0;
425 op.sfcmd.b.cmd = p_dev->prog_cmd;
426 op.sfcmd.b.addrbits = SFC_ADDR_24BITS;
427 op.sfcmd.b.rw = SFC_WRITE;
428
429 op.sfctrl.d32 = 0;
430 op.sfctrl.b.datalines = p_dev->prog_lines;
431 op.sfctrl.b.enbledma = 1;
432 op.sfctrl.b.addrlines = p_dev->prog_addr_lines;
433
434 if (p_dev->addr_mode == ADDR_MODE_4BYTE)
435 op.sfcmd.b.addrbits = SFC_ADDR_32BITS;
436
437 snor_write_en();
438
439 ret = sfc_request(&op, addr, p_data, size);
440 if (ret != SFC_OK)
441 return ret;
442
443 ret = snor_wait_busy(10000);
444
445 return ret;
446 }
447
snor_prog(struct SFNOR_DEV * p_dev,u32 addr,void * p_data,u32 size)448 static int snor_prog(struct SFNOR_DEV *p_dev, u32 addr, void *p_data, u32 size)
449 {
450 int ret = SFC_OK;
451 u32 page_size, len;
452 u8 *p_buf = (u8 *)p_data;
453
454 page_size = NOR_PAGE_SIZE;
455 while (size) {
456 len = page_size < size ? page_size : size;
457 ret = snor_prog_page(p_dev, addr, p_buf, len);
458 if (ret != SFC_OK)
459 return ret;
460
461 size -= len;
462 addr += len;
463 p_buf += len;
464 }
465
466 return ret;
467 }
468
snor_enable_QE(struct SFNOR_DEV * p_dev)469 static int snor_enable_QE(struct SFNOR_DEV *p_dev)
470 {
471 int ret = SFC_OK;
472 int reg_index;
473 int bit_offset;
474 u8 status;
475
476 reg_index = p_dev->QE_bits >> 3;
477 bit_offset = p_dev->QE_bits & 0x7;
478 ret = snor_read_status(reg_index, &status);
479 if (ret != SFC_OK)
480 return ret;
481
482 if (status & (1 << bit_offset)) /* is QE bit set */
483 return SFC_OK;
484
485 status |= (1 << bit_offset);
486
487 return p_dev->write_status(reg_index, status);
488 }
489
snor_disable_QE(struct SFNOR_DEV * p_dev)490 int snor_disable_QE(struct SFNOR_DEV *p_dev)
491 {
492 int ret = SFC_OK;
493 int reg_index;
494 int bit_offset;
495 u8 status;
496
497 reg_index = p_dev->QE_bits >> 3;
498 bit_offset = p_dev->QE_bits & 0x7;
499 ret = snor_read_status(reg_index, &status);
500 if (ret != SFC_OK)
501 return ret;
502
503 if (!(status & (1 << bit_offset)))
504 return SFC_OK;
505
506 status &= ~(1 << bit_offset);
507
508 return p_dev->write_status(reg_index, status);
509 }
510
snor_read_data(struct SFNOR_DEV * p_dev,u32 addr,void * p_data,u32 size)511 int snor_read_data(struct SFNOR_DEV *p_dev,
512 u32 addr,
513 void *p_data,
514 u32 size)
515 {
516 int ret;
517 struct rk_sfc_op op;
518
519 op.sfcmd.d32 = 0;
520 op.sfcmd.b.cmd = p_dev->read_cmd;
521 op.sfcmd.b.addrbits = SFC_ADDR_24BITS;
522
523 op.sfctrl.d32 = 0;
524 op.sfctrl.b.datalines = p_dev->read_lines;
525 if (!(size & 0x3) && size >= 4)
526 op.sfctrl.b.enbledma = 1;
527
528 if (p_dev->read_cmd == CMD_FAST_READ_X1 ||
529 p_dev->read_cmd == CMD_PAGE_FASTREAD4B ||
530 p_dev->read_cmd == CMD_FAST_READ_X4 ||
531 p_dev->read_cmd == CMD_FAST_READ_X2 ||
532 p_dev->read_cmd == CMD_FAST_4READ_X4) {
533 op.sfcmd.b.dummybits = 8;
534 } else if (p_dev->read_cmd == CMD_FAST_READ_A4) {
535 op.sfcmd.b.addrbits = SFC_ADDR_32BITS;
536 addr = (addr << 8) | 0xFF; /* Set M[7:0] = 0xFF */
537 op.sfcmd.b.dummybits = 4;
538 op.sfctrl.b.addrlines = SFC_4BITS_LINE;
539 }
540
541 if (p_dev->addr_mode == ADDR_MODE_4BYTE)
542 op.sfcmd.b.addrbits = SFC_ADDR_32BITS;
543
544 ret = sfc_request(&op, addr, p_data, size);
545 rkflash_print_dio("%s %x %x\n", __func__, addr, *(u32 *)(p_data));
546
547 return ret;
548 }
549
snor_read(struct SFNOR_DEV * p_dev,u32 sec,u32 n_sec,void * p_data)550 int snor_read(struct SFNOR_DEV *p_dev, u32 sec, u32 n_sec, void *p_data)
551 {
552 int ret = SFC_OK;
553 u32 addr, size, len;
554 u8 *p_buf = (u8 *)p_data;
555
556 rkflash_print_dio("%s %x %x\n", __func__, sec, n_sec);
557
558 if ((sec + n_sec) > p_dev->capacity)
559 return SFC_PARAM_ERR;
560
561 addr = sec << 9;
562 size = n_sec << 9;
563 while (size) {
564 len = size < p_dev->max_iosize ? size : p_dev->max_iosize;
565 ret = snor_read_data(p_dev, addr, p_buf, len);
566 if (ret != SFC_OK) {
567 rkflash_print_error("snor_read_data %x ret= %x\n",
568 addr >> 9, ret);
569 goto out;
570 }
571
572 size -= len;
573 addr += len;
574 p_buf += len;
575 }
576 out:
577 if (!ret)
578 ret = n_sec;
579
580 return ret;
581 }
582
snor_write(struct SFNOR_DEV * p_dev,u32 sec,u32 n_sec,void * p_data)583 int snor_write(struct SFNOR_DEV *p_dev, u32 sec, u32 n_sec, void *p_data)
584 {
585 int ret = SFC_OK;
586 u32 len, blk_size, offset;
587 u8 *p_buf = (u8 *)p_data;
588 u32 total_sec = n_sec;
589
590 rkflash_print_dio("%s %x %x\n", __func__, sec, n_sec);
591
592 if ((sec + n_sec) > p_dev->capacity)
593 return SFC_PARAM_ERR;
594
595 while (n_sec) {
596 if (sec < 512 || sec >= p_dev->capacity - 512)
597 blk_size = 8;
598 else
599 blk_size = p_dev->blk_size;
600
601 offset = (sec & (blk_size - 1));
602 if (!offset) {
603 ret = snor_erase(p_dev, sec << 9, (blk_size == 8) ?
604 ERASE_SECTOR : ERASE_BLOCK64K);
605 if (ret != SFC_OK) {
606 rkflash_print_error("snor_erase %x ret= %x\n",
607 sec, ret);
608 goto out;
609 }
610 }
611 len = (blk_size - offset) < n_sec ?
612 (blk_size - offset) : n_sec;
613 ret = snor_prog(p_dev, sec << 9, p_buf, len << 9);
614 if (ret != SFC_OK) {
615 rkflash_print_error("snor_prog %x ret= %x\n", sec, ret);
616 goto out;
617 }
618 n_sec -= len;
619 sec += len;
620 p_buf += len << 9;
621 }
622 out:
623 if (!ret)
624 ret = total_sec;
625
626 return ret;
627 }
628
snor_read_id(u8 * data)629 int snor_read_id(u8 *data)
630 {
631 int ret;
632 struct rk_sfc_op op;
633
634 op.sfcmd.d32 = 0;
635 op.sfcmd.b.cmd = CMD_READ_JEDECID;
636
637 op.sfctrl.d32 = 0;
638
639 ret = sfc_request(&op, 0, data, 3);
640
641 return ret;
642 }
643
snor_read_parameter(u32 addr,u8 * data)644 static int snor_read_parameter(u32 addr, u8 *data)
645 {
646 int ret;
647 struct rk_sfc_op op;
648
649 op.sfcmd.d32 = 0;
650 op.sfcmd.b.cmd = CMD_READ_PARAMETER;
651 op.sfcmd.b.addrbits = SFC_ADDR_24BITS;
652 op.sfcmd.b.dummybits = 8;
653
654 op.sfctrl.d32 = 0;
655
656 ret = sfc_request(&op, addr, data, 1);
657
658 return ret;
659 }
660
snor_get_capacity(struct SFNOR_DEV * p_dev)661 u32 snor_get_capacity(struct SFNOR_DEV *p_dev)
662 {
663 return p_dev->capacity;
664 }
665
snor_get_flash_info(u8 * flash_id)666 static struct flash_info *snor_get_flash_info(u8 *flash_id)
667 {
668 u32 i;
669 u32 id = (flash_id[0] << 16) | (flash_id[1] << 8) | (flash_id[2] << 0);
670
671 for (i = 0; i < ARRAY_SIZE(spi_flash_tbl); i++) {
672 if (spi_flash_tbl[i].id == id)
673 return &spi_flash_tbl[i];
674 }
675 return NULL;
676 }
677
678 /* Adjust flash info in ram base on parameter */
snor_flash_info_adjust(struct flash_info * spi_flash_info)679 static void *snor_flash_info_adjust(struct flash_info *spi_flash_info)
680 {
681 u32 addr;
682 u8 para_version;
683
684 if (spi_flash_info->id == 0xc84019) {
685 addr = 0x09;
686 snor_read_parameter(addr, ¶_version);
687 if (para_version == 0x06) {
688 spi_flash_info->QE_bits = 9;
689 spi_flash_info->prog_cmd_4 = 0x34;
690 }
691 }
692 return 0;
693 }
694
snor_parse_flash_table(struct SFNOR_DEV * p_dev,struct flash_info * g_spi_flash_info)695 static int snor_parse_flash_table(struct SFNOR_DEV *p_dev,
696 struct flash_info *g_spi_flash_info)
697 {
698 int i, ret;
699
700 if (g_spi_flash_info) {
701 snor_flash_info_adjust(g_spi_flash_info);
702 p_dev->manufacturer = (g_spi_flash_info->id >> 16) & 0xFF;
703 p_dev->mem_type = (g_spi_flash_info->id >> 8) & 0xFF;
704 p_dev->capacity = 1 << g_spi_flash_info->density;
705 p_dev->blk_size = g_spi_flash_info->block_size;
706 p_dev->page_size = NOR_SECS_PAGE;
707 p_dev->read_cmd = g_spi_flash_info->read_cmd;
708 p_dev->prog_cmd = g_spi_flash_info->prog_cmd;
709 p_dev->sec_erase_cmd = g_spi_flash_info->sector_erase_cmd;
710 p_dev->blk_erase_cmd = g_spi_flash_info->block_erase_cmd;
711 p_dev->prog_lines = DATA_LINES_X1;
712 p_dev->read_lines = DATA_LINES_X1;
713 p_dev->QE_bits = g_spi_flash_info->QE_bits;
714 p_dev->addr_mode = ADDR_MODE_3BYTE;
715
716 i = g_spi_flash_info->feature & FEA_READ_STATUE_MASK;
717 if (i == 0)
718 p_dev->write_status = snor_write_status;
719 else if (i == 1)
720 p_dev->write_status = snor_write_status1;
721 else if (i == 2)
722 p_dev->write_status = snor_write_status2;
723
724 if (g_spi_flash_info->feature & FEA_4BIT_READ) {
725 ret = SFC_OK;
726 if (g_spi_flash_info->QE_bits)
727 ret = snor_enable_QE(p_dev);
728 if (ret == SFC_OK) {
729 p_dev->read_lines = DATA_LINES_X4;
730 p_dev->read_cmd = g_spi_flash_info->read_cmd_4;
731 }
732 }
733 if (g_spi_flash_info->feature & FEA_4BIT_PROG &&
734 p_dev->read_lines == DATA_LINES_X4) {
735 p_dev->prog_lines = DATA_LINES_X4;
736 p_dev->prog_cmd = g_spi_flash_info->prog_cmd_4;
737 if ((p_dev->manufacturer == MID_MACRONIX) &&
738 (p_dev->prog_cmd == CMD_PAGE_PROG_A4 ||
739 p_dev->prog_cmd == CMD_PAGE_PROG_4PP))
740 p_dev->prog_addr_lines = DATA_LINES_X4;
741 }
742
743 if (g_spi_flash_info->feature & FEA_4BYTE_ADDR)
744 p_dev->addr_mode = ADDR_MODE_4BYTE;
745
746 if ((g_spi_flash_info->feature & FEA_4BYTE_ADDR_MODE))
747 snor_enter_4byte_mode();
748 }
749
750 return SFC_OK;
751 }
752
snor_init(struct SFNOR_DEV * p_dev)753 int snor_init(struct SFNOR_DEV *p_dev)
754 {
755 struct flash_info *g_spi_flash_info;
756 u8 id_byte[5];
757
758 if (!p_dev)
759 return SFC_PARAM_ERR;
760
761 memset((void *)p_dev, 0, sizeof(struct SFNOR_DEV));
762 p_dev->max_iosize = sfc_get_max_iosize();
763
764 snor_read_id(id_byte);
765 rkflash_print_error("sfc nor id: %x %x %x\n",
766 id_byte[0], id_byte[1], id_byte[2]);
767 if (0xFF == id_byte[0] || 0x00 == id_byte[0] || 0xFF == id_byte[1] || 0x00 == id_byte[1])
768 return SFC_ERROR;
769
770 g_spi_flash_info = snor_get_flash_info(id_byte);
771 if (g_spi_flash_info) {
772 snor_parse_flash_table(p_dev, g_spi_flash_info);
773 } else {
774 pr_err("The device not support yet!\n");
775
776 p_dev->manufacturer = id_byte[0];
777 p_dev->mem_type = id_byte[1];
778 p_dev->capacity = 1 << (id_byte[2] - 9);
779 p_dev->QE_bits = 0;
780 p_dev->blk_size = NOR_SECS_BLK;
781 p_dev->page_size = NOR_SECS_PAGE;
782 p_dev->read_cmd = CMD_READ_DATA;
783 p_dev->prog_cmd = CMD_PAGE_PROG;
784 p_dev->sec_erase_cmd = CMD_SECTOR_ERASE;
785 p_dev->blk_erase_cmd = CMD_BLOCK_ERASE;
786 p_dev->prog_lines = DATA_LINES_X1;
787 p_dev->prog_addr_lines = DATA_LINES_X1;
788 p_dev->read_lines = DATA_LINES_X1;
789 p_dev->write_status = snor_write_status;
790 snor_reset_device();
791 }
792
793 rkflash_print_info("addr_mode: %x\n", p_dev->addr_mode);
794 rkflash_print_info("read_lines: %x\n", p_dev->read_lines);
795 rkflash_print_info("prog_lines: %x\n", p_dev->prog_lines);
796 rkflash_print_info("read_cmd: %x\n", p_dev->read_cmd);
797 rkflash_print_info("prog_cmd: %x\n", p_dev->prog_cmd);
798 rkflash_print_info("blk_erase_cmd: %x\n", p_dev->blk_erase_cmd);
799 rkflash_print_info("sec_erase_cmd: %x\n", p_dev->sec_erase_cmd);
800 rkflash_print_info("capacity: %x\n", p_dev->capacity);
801
802 return SFC_OK;
803 }
804
snor_reinit_from_table_packet(struct SFNOR_DEV * p_dev,struct snor_info_packet * packet)805 int snor_reinit_from_table_packet(struct SFNOR_DEV *p_dev,
806 struct snor_info_packet *packet)
807 {
808 struct flash_info g_spi_flash_info;
809 u8 id_byte[5];
810 int ret;
811
812 if (!p_dev || packet->id != SNOR_INFO_PACKET_ID)
813 return SFC_PARAM_ERR;
814
815 snor_read_id(id_byte);
816 if (0xFF == id_byte[0] || 0x00 == id_byte[0])
817 return SFC_ERROR;
818
819 g_spi_flash_info.id = id_byte[0] << 16 | id_byte[1] << 8 | id_byte[2];
820 g_spi_flash_info.block_size = NOR_SECS_BLK;
821 g_spi_flash_info.sector_size = NOR_SECS_PAGE;
822 g_spi_flash_info.read_cmd = packet->read_cmd;
823 g_spi_flash_info.prog_cmd = packet->prog_cmd;
824 g_spi_flash_info.read_cmd_4 = packet->read_cmd_4;
825 g_spi_flash_info.prog_cmd_4 = packet->prog_cmd_4;
826 if (id_byte[2] >= 0x19)
827 g_spi_flash_info.read_cmd_4 = CMD_FAST_4READ_X4;
828 g_spi_flash_info.sector_erase_cmd = packet->sector_erase_cmd;
829 g_spi_flash_info.block_erase_cmd = packet->block_erase_cmd;
830 g_spi_flash_info.feature = packet->feature;
831 g_spi_flash_info.density = id_byte[2] - 9;
832 g_spi_flash_info.QE_bits = packet->QE_bits;
833
834 ret = snor_parse_flash_table(p_dev, &g_spi_flash_info);
835
836 return ret;
837 }
838
839