1 /* 2 * Copyright (c) 2018 Fuzhou Rockchip Electronics Co., Ltd 3 * 4 * SPDX-License-Identifier: GPL-2.0 5 */ 6 7 #ifndef _SFC_H 8 #define _SFC_H 9 10 #define SFC_VER_3 0x3 11 #define SFC_VER_4 0x4 12 #define SFC_VER_5 0x5 13 14 #define SFC_EN_INT (0) /* enable interrupt */ 15 #define SFC_EN_DMA (1) /* enable dma */ 16 #define SFC_FIFO_DEPTH (0x10) /* 16 words */ 17 18 /* FIFO watermark */ 19 #define SFC_RX_WMARK (SFC_FIFO_DEPTH) /* RX watermark level */ 20 #define SFC_TX_WMARK (SFC_FIFO_DEPTH) /* TX watermark level */ 21 #define SFC_RX_WMARK_SHIFT (8) 22 #define SFC_TX_WMARK_SHIFT (0) 23 24 /* return value */ 25 #define SFC_OK (0) 26 #define SFC_ERROR (-1) 27 #define SFC_PARAM_ERR (-2) 28 #define SFC_TX_TIMEOUT (-3) 29 #define SFC_RX_TIMEOUT (-4) 30 #define SFC_WAIT_TIMEOUT (-5) 31 #define SFC_BUSY_TIMEOUT (-6) 32 #define SFC_ECC_FAIL (-7) 33 #define SFC_PROG_FAIL (-8) 34 #define SFC_ERASE_FAIL (-9) 35 36 /* SFC_CMD Register */ 37 #define SFC_ADDR_0BITS (0) 38 #define SFC_ADDR_24BITS (1) 39 #define SFC_ADDR_32BITS (2) 40 #define SFC_ADDR_XBITS (3) 41 42 #define SFC_WRITE (1) 43 #define SFC_READ (0) 44 45 /* SFC_CTRL Register */ 46 #define SFC_1BITS_LINE (0) 47 #define SFC_2BITS_LINE (1) 48 #define SFC_4BITS_LINE (2) 49 50 #define SFC_ENABLE_DMA BIT(14) 51 #define sfc_delay(us) udelay(us) 52 53 #define DMA_INT BIT(7) /* dma interrupt */ 54 #define NSPIERR_INT BIT(6) /* Nspi error interrupt */ 55 #define AHBERR_INT BIT(5) /* Ahb bus error interrupt */ 56 #define FINISH_INT BIT(4) /* Transfer finish interrupt */ 57 #define TXEMPTY_INT BIT(3) /* Tx fifo empty interrupt */ 58 #define TXOF_INT BIT(2) /* Tx fifo overflow interrupt */ 59 #define RXUF_INT BIT(1) /* Rx fifo underflow interrupt */ 60 #define RXFULL_INT BIT(0) /* Rx fifo full interrupt */ 61 62 /* SFC_FSR Register*/ 63 #define SFC_RXFULL BIT(3) /* rx fifo full */ 64 #define SFC_RXEMPTY BIT(2) /* rx fifo empty */ 65 #define SFC_TXEMPTY BIT(1) /* tx fifo empty */ 66 #define SFC_TXFULL BIT(0) /* tx fifo full */ 67 68 /* SFC_RCVR Register */ 69 #define SFC_RESET BIT(0) /* controller reset */ 70 71 /* SFC_DLL_CTRL Register */ 72 #define SCLK_SMP_SEL_EN BIT(15) /* SCLK Sampling Selection */ 73 #define SCLK_SMP_SEL_MAX_V4 0xFF /* SCLK Sampling Selection */ 74 #define SCLK_SMP_SEL_MAX_V5 0x1FF /* SCLK Sampling Selection */ 75 76 /* SFC_SR Register */ 77 /* sfc busy flag. When busy, don't try to set the control register */ 78 #define SFC_BUSY BIT(0) 79 80 /* SFC_DMA_TRIGGER Register */ 81 /* Dma start trigger signal. Auto cleared after write */ 82 #define SFC_DMA_START BIT(0) 83 84 #define SFC_CTRL 0x00 85 #define SFC_IMR 0x04 86 #define SFC_ICLR 0x08 87 #define SFC_FTLR 0x0C 88 #define SFC_RCVR 0x10 89 #define SFC_AX 0x14 90 #define SFC_ABIT 0x18 91 #define SFC_MASKISR 0x1C 92 #define SFC_FSR 0x20 93 #define SFC_SR 0x24 94 #define SFC_RAWISR 0x28 95 #define SFC_VER 0x2C 96 #define SFC_QOP 0x30 97 #define SFC_DLL_CTRL0 0x3C 98 #define SFC_DMA_TRIGGER 0x80 99 #define SFC_DMA_ADDR 0x84 100 #define SFC_LEN_CTRL 0x88 101 #define SFC_LEN_EXT 0x8C 102 #define SFC_CMD 0x100 103 #define SFC_ADDR 0x104 104 #define SFC_DATA 0x108 105 106 union SFCFSR_DATA { 107 u32 d32; 108 struct { 109 unsigned txempty : 1; 110 unsigned txfull : 1; 111 unsigned rxempty : 1; 112 unsigned rxfull : 1; 113 unsigned reserved7_4 : 4; 114 unsigned txlevel : 5; 115 unsigned reserved15_13 : 3; 116 unsigned rxlevel : 5; 117 unsigned reserved31_21 : 11; 118 } b; 119 }; 120 121 /* Manufactory ID */ 122 #define MID_WINBOND 0xEF 123 #define MID_GIGADEV 0xC8 124 #define MID_MICRON 0x2C 125 #define MID_MACRONIX 0xC2 126 #define MID_SPANSION 0x01 127 #define MID_EON 0x1C 128 #define MID_ST 0x20 129 #define MID_XTX 0x0B 130 #define MID_PUYA 0x85 131 #define MID_XMC 0x20 132 #define MID_DOSILICON 0xF8 133 #define MID_ZBIT 0x5E 134 135 /*------------------------------ Global Typedefs -----------------------------*/ 136 enum SFC_DATA_LINES { 137 DATA_LINES_X1 = 0, 138 DATA_LINES_X2, 139 DATA_LINES_X4 140 }; 141 142 union SFCCTRL_DATA { 143 /* raw register data */ 144 u32 d32; 145 /* register bits */ 146 struct { 147 /* spi mode select */ 148 unsigned mode : 1; 149 /* 150 * Shift in phase selection 151 * 0: shift in the flash data at posedge sclk_out 152 * 1: shift in the flash data at negedge sclk_out 153 */ 154 unsigned sps : 1; 155 unsigned reserved3_2 : 2; 156 /* sclk_idle_level_cycles */ 157 unsigned scic : 4; 158 /* Cmd bits number */ 159 unsigned cmdlines : 2; 160 /* Address bits number */ 161 unsigned addrlines : 2; 162 /* Data bits number */ 163 unsigned datalines : 2; 164 /* this bit is not exit in regiseter, just use for code param */ 165 unsigned enbledma : 1; 166 unsigned reserved15 : 1; 167 unsigned addrbits : 5; 168 unsigned reserved31_21 : 11; 169 } b; 170 }; 171 172 union SFCCMD_DATA { 173 /* raw register data */ 174 u32 d32; 175 /* register bits */ 176 struct { 177 /* Command that will send to Serial Flash */ 178 unsigned cmd : 8; 179 /* Dummy bits number */ 180 unsigned dummybits : 4; 181 /* 0: read, 1: write */ 182 unsigned rw : 1; 183 /* Continuous read mode */ 184 unsigned readmode : 1; 185 /* Address bits number */ 186 unsigned addrbits : 2; 187 /* Transferred bytes number */ 188 unsigned datasize : 14; 189 /* Chip select */ 190 unsigned cs : 2; 191 } b; 192 }; 193 194 struct rk_sfc_op { 195 union SFCCMD_DATA sfcmd; 196 union SFCCTRL_DATA sfctrl; 197 }; 198 199 #define IDB_BLOCK_TAG_ID 0xFCDC8C3B 200 201 struct id_block_tag { 202 u32 id; 203 u32 version; 204 u32 flags; 205 u16 boot_img_offset; 206 u8 reserved1[10]; 207 u32 dev_param[8]; 208 u8 reserved2[506 - 56]; 209 u16 data_img_len; 210 u16 boot_img_len; 211 u8 reserved3[512 - 510]; 212 } __packed; 213 214 int sfc_init(void __iomem *reg_addr); 215 int sfc_request(struct rk_sfc_op *op, u32 addr, void *data, u32 size); 216 u16 sfc_get_version(void); 217 void sfc_clean_irq(void); 218 u32 sfc_get_max_iosize(void); 219 void sfc_set_delay_lines(u16 cells); 220 void sfc_disable_delay_lines(void); 221 int rksfc_get_reg_addr(unsigned long *p_sfc_addr); 222 223 #endif 224