1 /*
2 * Copyright (C) 2021 Rockchip Electronics Co., Ltd
3 *
4 * SPDX-License-Identifier: GPL-2.0+
5 */
6
7 #include <common.h>
8 #include <dm.h>
9 #include <errno.h>
10 #include <power/rk8xx_pmic.h>
11 #include <power/pmic.h>
12 #include <power/regulator.h>
13
14 #ifndef CONFIG_SPL_BUILD
15 #define ENABLE_DRIVER
16 #endif
17
18 /* Not used or exisit register and configure */
19 #define NA -1
20
21 /* rk806 buck*/
22 #define RK806_BUCK_ON_VSEL(n) (0x1a + n - 1)
23 #define RK806_BUCK_SLP_VSEL(n) (0x24 + n - 1)
24 #define RK806_BUCK_CONFIG(n) (0x10 + n - 1)
25 #define RK806_BUCK_VSEL_MASK 0xff
26
27 /* RK806 LDO */
28 #define RK806_NLDO_ON_VSEL(n) (0x43 + n - 1)
29 #define RK806_NLDO_SLP_VSEL(n) (0x48 + n - 1)
30 #define RK806_NLDO_VSEL_MASK 0xff
31 #define RK806_PLDO_ON_VSEL(n) (0x4e + n - 1)
32 #define RK806_PLDO_SLP_VSEL(n) (0x54 + n - 1)
33 #define RK806_PLDO_VSEL_MASK 0xff
34
35 /* RK806 ENABLE */
36 #define RK806_POWER_EN(n) (0x00 + n)
37 #define RK806_NLDO_EN(n) (0x03 + n)
38 #define RK806_PLDO_EN(n) (0x04 + n)
39
40 #define RK806_BUCK_SUSPEND_EN 0x06
41 #define RK806_NLDO_SUSPEND_EN 0x07
42 #define RK806_PLDO_SUSPEND_EN 0x08
43
44 #define RK806_RAMP_RATE_MASK1 0xc0
45 #define RK806_RAMP_RATE_REG1(n) (0x10 + n)
46 #define RK806_RAMP_RATE_REG1_8 0xeb
47 #define RK806_RAMP_RATE_REG9_10 0xea
48
49 #define RK806_RAMP_RATE_4LSB_PER_1CLK 0x00/* LDO 100mV/uS buck 50mV/us */
50 #define RK806_RAMP_RATE_2LSB_PER_1CLK 0x01/* LDO 50mV/uS buck 25mV/us */
51 #define RK806_RAMP_RATE_1LSB_PER_1CLK 0x02/* LDO 25mV/uS buck 12.5mV/us */
52 #define RK806_RAMP_RATE_1LSB_PER_2CLK 0x03/* LDO 12.5mV/uS buck 6.25mV/us */
53
54 #define RK806_RAMP_RATE_1LSB_PER_4CLK 0x04/* LDO 6.28/2mV/uS buck 3.125mV/us */
55 #define RK806_RAMP_RATE_1LSB_PER_8CLK 0x05/* LDO 3.12mV/uS buck 1.56mV/us */
56 #define RK806_RAMP_RATE_1LSB_PER_13CLK 0x06/* LDO 1.9mV/uS buck 961mV/us */
57 #define RK806_RAMP_RATE_1LSB_PER_32CLK 0x07/* LDO 0.78mV/uS buck 0.39mV/us */
58
59 #define RK806_PLDO0_2_MSK(pldo) (BIT(pldo + 5))
60 #define RK806_PLDO0_2_SET(pldo) (BIT(pldo + 1) | RK806_PLDO0_2_MSK(pldo))
61 #define RK806_PLDO0_2_CLR(pldo) RK806_PLDO0_2_MSK(pldo)
62
63 struct rk8xx_reg_info {
64 uint min_uv;
65 uint step_uv;
66 u8 vsel_reg;
67 u8 vsel_sleep_reg;
68 u8 config_reg;
69 u8 vsel_mask;
70 u8 min_sel;
71 /* only for buck now */
72 u8 max_sel;
73 u8 range_num;
74 };
75
76 static const struct rk8xx_reg_info rk806_buck[] = {
77 /* buck 1 */
78 { 500000, 6250, RK806_BUCK_ON_VSEL(1), RK806_BUCK_SLP_VSEL(1), RK806_BUCK_CONFIG(1), RK806_BUCK_VSEL_MASK, 0x00, 0x9f, 3},
79 { 1500000, 25000, RK806_BUCK_ON_VSEL(1), RK806_BUCK_SLP_VSEL(1), RK806_BUCK_CONFIG(1), RK806_BUCK_VSEL_MASK, 0xa0, 0xec, 3},
80 { 3400000, 0, RK806_BUCK_ON_VSEL(1), RK806_BUCK_SLP_VSEL(1), RK806_BUCK_CONFIG(1), RK806_BUCK_VSEL_MASK, 0xed, 0xff, 3},
81 /* buck 2 */
82 { 500000, 6250, RK806_BUCK_ON_VSEL(2), RK806_BUCK_SLP_VSEL(2), RK806_BUCK_CONFIG(2), RK806_BUCK_VSEL_MASK, 0x00, 0x9f, 3},
83 { 1500000, 25000, RK806_BUCK_ON_VSEL(2), RK806_BUCK_SLP_VSEL(2), RK806_BUCK_CONFIG(2), RK806_BUCK_VSEL_MASK, 0xa0, 0xed, 3},
84 { 3400000, 0, RK806_BUCK_ON_VSEL(2), RK806_BUCK_SLP_VSEL(2), RK806_BUCK_CONFIG(2), RK806_BUCK_VSEL_MASK, 0xed, 0xff, 3},
85 /* buck 3 */
86 { 500000, 6250, RK806_BUCK_ON_VSEL(3), RK806_BUCK_SLP_VSEL(3), RK806_BUCK_CONFIG(3), RK806_BUCK_VSEL_MASK, 0x00, 0x9f, 3},
87 { 1500000, 25000, RK806_BUCK_ON_VSEL(3), RK806_BUCK_SLP_VSEL(3), RK806_BUCK_CONFIG(3), RK806_BUCK_VSEL_MASK, 0xa0, 0xed, 3},
88 { 3400000, 0, RK806_BUCK_ON_VSEL(3), RK806_BUCK_SLP_VSEL(3), RK806_BUCK_CONFIG(3), RK806_BUCK_VSEL_MASK, 0xed, 0xff, 3},
89 /* buck 4 */
90 { 500000, 6250, RK806_BUCK_ON_VSEL(4), RK806_BUCK_SLP_VSEL(4), RK806_BUCK_CONFIG(4), RK806_BUCK_VSEL_MASK, 0x00, 0x9f, 3},
91 { 1500000, 25000, RK806_BUCK_ON_VSEL(4), RK806_BUCK_SLP_VSEL(4), RK806_BUCK_CONFIG(4), RK806_BUCK_VSEL_MASK, 0xa0, 0xed, 3},
92 { 3400000, 0, RK806_BUCK_ON_VSEL(4), RK806_BUCK_SLP_VSEL(4), RK806_BUCK_CONFIG(4), RK806_BUCK_VSEL_MASK, 0xed, 0xff, 3},
93 /* buck 5 */
94 { 500000, 6250, RK806_BUCK_ON_VSEL(5), RK806_BUCK_SLP_VSEL(5), RK806_BUCK_CONFIG(5), RK806_BUCK_VSEL_MASK, 0x00, 0x9f, 3},
95 { 1500000, 25000, RK806_BUCK_ON_VSEL(5), RK806_BUCK_SLP_VSEL(5), RK806_BUCK_CONFIG(5), RK806_BUCK_VSEL_MASK, 0xa0, 0xed, 3},
96 { 3400000, 0, RK806_BUCK_ON_VSEL(5), RK806_BUCK_SLP_VSEL(5), RK806_BUCK_CONFIG(5), RK806_BUCK_VSEL_MASK, 0xed, 0xff, 3},
97 /* buck 6 */
98 { 500000, 6250, RK806_BUCK_ON_VSEL(6), RK806_BUCK_SLP_VSEL(6), RK806_BUCK_CONFIG(6), RK806_BUCK_VSEL_MASK, 0x00, 0x9f, 3},
99 { 1500000, 25000, RK806_BUCK_ON_VSEL(6), RK806_BUCK_SLP_VSEL(6), RK806_BUCK_CONFIG(6), RK806_BUCK_VSEL_MASK, 0xa0, 0xed, 3},
100 { 3400000, 0, RK806_BUCK_ON_VSEL(6), RK806_BUCK_SLP_VSEL(6), RK806_BUCK_CONFIG(6), RK806_BUCK_VSEL_MASK, 0xed, 0xff, 3},
101 /* buck 7 */
102 { 500000, 6250, RK806_BUCK_ON_VSEL(7), RK806_BUCK_SLP_VSEL(7), RK806_BUCK_CONFIG(7), RK806_BUCK_VSEL_MASK, 0x00, 0x9f, 3},
103 { 1500000, 25000, RK806_BUCK_ON_VSEL(7), RK806_BUCK_SLP_VSEL(7), RK806_BUCK_CONFIG(7), RK806_BUCK_VSEL_MASK, 0xa0, 0xed, 3},
104 { 3400000, 0, RK806_BUCK_ON_VSEL(7), RK806_BUCK_SLP_VSEL(7), RK806_BUCK_CONFIG(7), RK806_BUCK_VSEL_MASK, 0xed, 0xff, 3},
105 /* buck 8 */
106 { 500000, 6250, RK806_BUCK_ON_VSEL(8), RK806_BUCK_SLP_VSEL(8), RK806_BUCK_CONFIG(8), RK806_BUCK_VSEL_MASK, 0x00, 0x9f, 3},
107 { 1500000, 25000, RK806_BUCK_ON_VSEL(8), RK806_BUCK_SLP_VSEL(8), RK806_BUCK_CONFIG(8), RK806_BUCK_VSEL_MASK, 0xa0, 0xed, 3},
108 { 3400000, 0, RK806_BUCK_ON_VSEL(8), RK806_BUCK_SLP_VSEL(8), RK806_BUCK_CONFIG(8), RK806_BUCK_VSEL_MASK, 0xed, 0xff, 3},
109 /* buck 9 */
110 { 500000, 6250, RK806_BUCK_ON_VSEL(9), RK806_BUCK_SLP_VSEL(9), RK806_BUCK_CONFIG(9), RK806_BUCK_VSEL_MASK, 0x00, 0x9f, 3},
111 { 1500000, 25000, RK806_BUCK_ON_VSEL(9), RK806_BUCK_SLP_VSEL(9), RK806_BUCK_CONFIG(9), RK806_BUCK_VSEL_MASK, 0xa0, 0xed, 3},
112 { 3400000, 0, RK806_BUCK_ON_VSEL(9), RK806_BUCK_SLP_VSEL(9), RK806_BUCK_CONFIG(9), RK806_BUCK_VSEL_MASK, 0xed, 0xff, 3},
113 /* buck 10 */
114 { 500000, 6250, RK806_BUCK_ON_VSEL(10), RK806_BUCK_SLP_VSEL(10), RK806_BUCK_CONFIG(10), RK806_BUCK_VSEL_MASK, 0x00, 0x9f, 3},
115 { 1500000, 25000, RK806_BUCK_ON_VSEL(10), RK806_BUCK_SLP_VSEL(10), RK806_BUCK_CONFIG(10), RK806_BUCK_VSEL_MASK, 0xa0, 0xed, 3},
116 { 3400000, 0, RK806_BUCK_ON_VSEL(10), RK806_BUCK_SLP_VSEL(10), RK806_BUCK_CONFIG(10), RK806_BUCK_VSEL_MASK, 0xed, 0xff, 3},
117 };
118
119 static const struct rk8xx_reg_info rk806_nldo[] = {
120 /* nldo1 */
121 { 500000, 12500, RK806_NLDO_ON_VSEL(1), RK806_NLDO_SLP_VSEL(1), NA, RK806_NLDO_VSEL_MASK, 0x00, },
122 { 3400000, 0, RK806_NLDO_ON_VSEL(1), RK806_NLDO_SLP_VSEL(1), NA, RK806_NLDO_VSEL_MASK, 0xE8, },
123 /* nldo2 */
124 { 500000, 12500, RK806_NLDO_ON_VSEL(2), RK806_NLDO_SLP_VSEL(2), NA, RK806_NLDO_VSEL_MASK, 0x00, },
125 { 3400000, 0, RK806_NLDO_ON_VSEL(2), RK806_NLDO_SLP_VSEL(2), NA, RK806_NLDO_VSEL_MASK, 0xE8, },
126 /* nldo3 */
127 { 500000, 12500, RK806_NLDO_ON_VSEL(3), RK806_NLDO_SLP_VSEL(3), NA, RK806_NLDO_VSEL_MASK, 0x00, },
128 { 3400000, 0, RK806_NLDO_ON_VSEL(3), RK806_NLDO_SLP_VSEL(3), NA, RK806_NLDO_VSEL_MASK, 0xE8, },
129 /* nldo4 */
130 { 500000, 12500, RK806_NLDO_ON_VSEL(4), RK806_NLDO_SLP_VSEL(4), NA, RK806_NLDO_VSEL_MASK, 0x00, },
131 { 3400000, 0, RK806_NLDO_ON_VSEL(4), RK806_NLDO_SLP_VSEL(4), NA, RK806_NLDO_VSEL_MASK, 0xE8, },
132 /* nldo5 */
133 { 500000, 12500, RK806_NLDO_ON_VSEL(5), RK806_NLDO_SLP_VSEL(5), NA, RK806_NLDO_VSEL_MASK, 0x00, },
134 { 3400000, 0, RK806_NLDO_ON_VSEL(5), RK806_NLDO_SLP_VSEL(5), NA, RK806_NLDO_VSEL_MASK, 0xE8, },
135 };
136
137 static const struct rk8xx_reg_info rk806_pldo[] = {
138 /* pldo1 */
139 { 500000, 12500, RK806_PLDO_ON_VSEL(1), RK806_PLDO_SLP_VSEL(1), NA, RK806_PLDO_VSEL_MASK, 0x00, },
140 { 3400000, 0, RK806_PLDO_ON_VSEL(1), RK806_PLDO_SLP_VSEL(1), NA, RK806_PLDO_VSEL_MASK, 0xE8, },
141 /* pldo2 */
142 { 500000, 12500, RK806_PLDO_ON_VSEL(2), RK806_PLDO_SLP_VSEL(2), NA, RK806_PLDO_VSEL_MASK, 0x00, },
143 { 3400000, 0, RK806_PLDO_ON_VSEL(2), RK806_PLDO_SLP_VSEL(2), NA, RK806_PLDO_VSEL_MASK, 0xE8, },
144 /* pldo3 */
145 { 500000, 12500, RK806_PLDO_ON_VSEL(3), RK806_PLDO_SLP_VSEL(3), NA, RK806_PLDO_VSEL_MASK, 0x00, },
146 { 3400000, 0, RK806_PLDO_ON_VSEL(3), RK806_PLDO_SLP_VSEL(3), NA, RK806_PLDO_VSEL_MASK, 0xE8, },
147 /* pldo4 */
148 { 500000, 12500, RK806_PLDO_ON_VSEL(4), RK806_PLDO_SLP_VSEL(4), NA, RK806_PLDO_VSEL_MASK, 0x00, },
149 { 3400000, 0, RK806_PLDO_ON_VSEL(4), RK806_PLDO_SLP_VSEL(4), NA, RK806_PLDO_VSEL_MASK, 0xE8, },
150 /* pldo5 */
151 { 500000, 12500, RK806_PLDO_ON_VSEL(5), RK806_PLDO_SLP_VSEL(5), NA, RK806_PLDO_VSEL_MASK, 0x00, },
152 { 3400000, 0, RK806_PLDO_ON_VSEL(5), RK806_PLDO_SLP_VSEL(5), NA, RK806_PLDO_VSEL_MASK, 0xE8, },
153 /* pldo6 */
154 { 500000, 12500, RK806_PLDO_ON_VSEL(6), RK806_PLDO_SLP_VSEL(6), NA, RK806_PLDO_VSEL_MASK, 0x00, },
155 { 3400000, 0, RK806_PLDO_ON_VSEL(6), RK806_PLDO_SLP_VSEL(6), NA, RK806_PLDO_VSEL_MASK, 0xE8, },
156 };
157
get_buck_reg(struct udevice * pmic,int num,int uvolt)158 static const struct rk8xx_reg_info *get_buck_reg(struct udevice *pmic,
159 int num, int uvolt)
160 {
161 struct rk8xx_priv *priv = dev_get_priv(pmic);
162
163 switch (priv->variant) {
164 case RK806_ID:
165 switch (num) {
166 case 0 ... 9:
167 if (uvolt < 1500000)
168 return &rk806_buck[num * 3 + 0];
169 else if (uvolt < 3400000)
170 return &rk806_buck[num * 3 + 1];
171 else
172 return &rk806_buck[num * 3 + 2];
173 break;
174 }
175 default:
176 return &rk806_buck[num * 3 + 0];
177 }
178 }
179
_buck_set_value(struct udevice * pmic,int buck,int uvolt)180 static int _buck_set_value(struct udevice *pmic, int buck, int uvolt)
181 {
182 const struct rk8xx_reg_info *info = get_buck_reg(pmic, buck, uvolt);
183 int mask = info->vsel_mask;
184 int val;
185
186 if (info->vsel_reg == NA)
187 return -EINVAL;
188
189 if (info->step_uv == 0) /* Fixed voltage */
190 val = info->min_sel;
191 else
192 val = ((uvolt - info->min_uv) / info->step_uv) + info->min_sel;
193
194 debug("%s: volt=%d, buck=%d, reg=0x%x, mask=0x%x, val=0x%x\n",
195 __func__, uvolt, buck + 1, info->vsel_reg, mask, val);
196
197 return pmic_clrsetbits(pmic, info->vsel_reg, mask, val);
198 }
199
_buck_set_enable(struct udevice * pmic,int buck,bool enable)200 static int _buck_set_enable(struct udevice *pmic, int buck, bool enable)
201 {
202 struct rk8xx_priv *priv = dev_get_priv(pmic);
203 uint value, en_reg;
204 int ret;
205
206 switch (priv->variant) {
207 case RK806_ID:
208 en_reg = RK806_POWER_EN(buck / 4);
209 if (enable)
210 value = ((1 << buck % 4) | (1 << (buck % 4 + 4)));
211 else
212 value = ((0 << buck % 4) | (1 << (buck % 4 + 4)));
213
214 ret = pmic_reg_write(pmic, en_reg, value);
215 break;
216 default:
217 ret = -EINVAL;
218 }
219
220 return ret;
221 }
222
223 #ifdef ENABLE_DRIVER
_buck_set_suspend_value(struct udevice * pmic,int buck,int uvolt)224 static int _buck_set_suspend_value(struct udevice *pmic, int buck, int uvolt)
225 {
226 const struct rk8xx_reg_info *info = get_buck_reg(pmic, buck, uvolt);
227 int mask = info->vsel_mask;
228 int val;
229
230 if (info->vsel_sleep_reg == NA)
231 return -EINVAL;
232
233 if (info->step_uv == 0)
234 val = info->min_sel;
235 else
236 val = ((uvolt - info->min_uv) / info->step_uv) + info->min_sel;
237
238 debug("%s: volt=%d, buck=%d, reg=0x%x, mask=0x%x, val=0x%x\n",
239 __func__, uvolt, buck + 1, info->vsel_sleep_reg, mask, val);
240
241 return pmic_clrsetbits(pmic, info->vsel_sleep_reg, mask, val);
242 }
243
_buck_get_enable(struct udevice * pmic,int buck)244 static int _buck_get_enable(struct udevice *pmic, int buck)
245 {
246 struct rk8xx_priv *priv = dev_get_priv(pmic);
247 uint mask = 0;
248 int ret = 0;
249
250 switch (priv->variant) {
251 case RK806_ID:
252 mask = 1 << buck % 4;
253 ret = pmic_reg_read(pmic, RK806_POWER_EN(buck / 4));
254 break;
255 default:
256 ret = 0;
257 }
258
259 if (ret < 0)
260 return ret;
261
262 return ret & mask ? true : false;
263 }
264
_buck_set_ramp_delay(struct udevice * pmic,int buck,u32 ramp_delay)265 static int _buck_set_ramp_delay(struct udevice *pmic, int buck, u32 ramp_delay)
266 {
267 const struct rk8xx_reg_info *info = get_buck_reg(pmic, buck, 0);
268 struct rk8xx_priv *priv = dev_get_priv(pmic);
269 int ramp_value = 0, reg_value;
270 int ramp_reg1, ramp_reg2;
271
272 if (info->config_reg == NA)
273 return -EINVAL;
274
275 switch (priv->variant) {
276 case RK806_ID:
277 switch (ramp_delay) {
278 case 1 ... 390:
279 ramp_value = RK806_RAMP_RATE_1LSB_PER_32CLK;
280 break;
281 case 391 ... 961:
282 ramp_value = RK806_RAMP_RATE_1LSB_PER_13CLK;
283 break;
284 case 962 ... 1560:
285 ramp_value = RK806_RAMP_RATE_1LSB_PER_8CLK;
286 break;
287 case 1561 ... 3125:
288 ramp_value = RK806_RAMP_RATE_1LSB_PER_4CLK;
289 break;
290 case 3126 ... 6250:
291 ramp_value = RK806_RAMP_RATE_1LSB_PER_2CLK;
292 break;
293 case 6251 ... 12500:
294 ramp_value = RK806_RAMP_RATE_1LSB_PER_1CLK;
295 break;
296 case 12501 ... 25000:
297 ramp_value = RK806_RAMP_RATE_2LSB_PER_1CLK;
298 break;
299 case 25001 ... 50000: /* 50mV/us */
300 ramp_value = RK806_RAMP_RATE_4LSB_PER_1CLK;
301 break;
302 default:
303 ramp_value = RK806_RAMP_RATE_1LSB_PER_32CLK;
304 printf("buck%d ramp_delay: %d not supported\n",
305 buck, ramp_delay);
306 break;
307 }
308 break;
309 default:
310 ramp_value = RK806_RAMP_RATE_1LSB_PER_32CLK;
311 return -EINVAL;
312 }
313
314 ramp_reg1 = RK806_RAMP_RATE_REG1(buck);
315 if (buck < 8)
316 ramp_reg2 = RK806_RAMP_RATE_REG1_8;
317 else
318 ramp_reg2 = RK806_RAMP_RATE_REG9_10;
319
320 reg_value = pmic_reg_read(pmic, ramp_reg1);
321 if (reg_value < 0) {
322 printf("buck%d read ramp reg(0x%x) error: %d", buck, ramp_reg1, reg_value);
323 return reg_value;
324 }
325 reg_value &= 0x3f;
326
327 pmic_reg_write(pmic,
328 ramp_reg1,
329 reg_value | (ramp_value & 0x03) << 0x06);
330
331 reg_value = pmic_reg_read(pmic, ramp_reg2);
332 if (reg_value < 0) {
333 printf("buck%d read ramp reg(0x%x) error: %d", buck, ramp_reg2, reg_value);
334 return reg_value;
335 }
336
337 return pmic_reg_write(pmic,
338 ramp_reg2,
339 reg_value | (ramp_value & 0x04) << (buck % 8));
340 }
341
_buck_set_suspend_enable(struct udevice * pmic,int buck,bool enable)342 static int _buck_set_suspend_enable(struct udevice *pmic, int buck, bool enable)
343 {
344 uint mask;
345 int ret;
346
347 if (buck <= 7) {
348 mask = 1 << buck;
349 ret = pmic_clrsetbits(pmic, RK806_BUCK_SUSPEND_EN, mask,
350 enable ? mask : 0);
351 } else {
352 if (buck == 8)
353 mask = 0x40;
354 else
355 mask = 0x80;
356 ret = pmic_clrsetbits(pmic, RK806_NLDO_SUSPEND_EN, mask,
357 enable ? mask : 0);
358 }
359
360 return ret;
361 }
362
_buck_get_suspend_enable(struct udevice * pmic,int buck)363 static int _buck_get_suspend_enable(struct udevice *pmic, int buck)
364 {
365 uint mask, val;
366 int ret;
367
368 if (buck <= 7) {
369 mask = 1 << buck % 7;
370 val = pmic_reg_read(pmic, RK806_BUCK_SUSPEND_EN);
371 } else {
372 mask = 1 << ((buck - 7) + 6);
373 val = pmic_reg_read(pmic, RK806_NLDO_SUSPEND_EN);
374 }
375
376 if (val < 0)
377 return val;
378 ret = val & mask ? 1 : 0;
379
380 return ret;
381 }
382
get_ldo_reg(struct udevice * pmic,int num,int uvolt)383 static const struct rk8xx_reg_info *get_ldo_reg(struct udevice *pmic,
384 int num, int uvolt)
385 {
386 struct rk8xx_priv *priv = dev_get_priv(pmic);
387
388 switch (priv->variant) {
389 case RK806_ID:
390 if (uvolt < 3400000)
391 return &rk806_nldo[num * 2];
392 else
393 return &rk806_nldo[num * 2 + 1];
394 default:
395 return &rk806_nldo[num * 2];
396 }
397 }
398
get_pldo_reg(struct udevice * pmic,int num,int uvolt)399 static const struct rk8xx_reg_info *get_pldo_reg(struct udevice *pmic,
400 int num, int uvolt)
401 {
402 struct rk8xx_priv *priv = dev_get_priv(pmic);
403
404 switch (priv->variant) {
405 case RK806_ID:
406 if (uvolt < 3400000)
407 return &rk806_pldo[num * 2];
408 else
409 return &rk806_pldo[num * 2 + 1];
410 default:
411 return &rk806_pldo[num * 2];
412 }
413 }
414
_ldo_get_enable(struct udevice * pmic,int ldo)415 static int _ldo_get_enable(struct udevice *pmic, int ldo)
416 {
417 struct rk8xx_priv *priv = dev_get_priv(pmic);
418 uint mask = 0;
419 int ret = 0;
420
421 switch (priv->variant) {
422 case RK806_ID:
423 if (ldo < 4) {
424 mask = 1 << ldo % 4;
425 ret = pmic_reg_read(pmic, RK806_NLDO_EN(ldo / 4));
426 } else {
427 mask = 1 << 2;
428 ret = pmic_reg_read(pmic, RK806_NLDO_EN(2));
429 }
430 break;
431 default:
432 return false;
433 }
434
435 if (ret < 0)
436 return ret;
437
438 return ret & mask ? true : false;
439 }
440
_ldo_set_enable(struct udevice * pmic,int ldo,bool enable)441 static int _ldo_set_enable(struct udevice *pmic, int ldo, bool enable)
442 {
443 struct rk8xx_priv *priv = dev_get_priv(pmic);
444 uint value, en_reg;
445 int ret = 0;
446
447 switch (priv->variant) {
448 case RK806_ID:
449 if (ldo < 4) {
450 en_reg = RK806_NLDO_EN(0);
451 if (enable)
452 value = ((1 << ldo % 4) | (1 << (ldo % 4 + 4)));
453 else
454 value = ((0 << ldo % 4) | (1 << (ldo % 4 + 4)));
455 ret = pmic_reg_write(pmic, en_reg, value);
456 } else {
457 en_reg = RK806_NLDO_EN(2);
458 if (enable)
459 value = 0x44;
460 else
461 value = 0x40;
462 ret = pmic_reg_write(pmic, en_reg, value);
463 }
464 break;
465 default:
466 return -EINVAL;
467 }
468
469 return ret;
470 }
471
_pldo_get_enable(struct udevice * pmic,int pldo)472 static int _pldo_get_enable(struct udevice *pmic, int pldo)
473 {
474 struct rk8xx_priv *priv = dev_get_priv(pmic);
475 uint mask = 0, en_reg;
476 int ret = 0;
477
478 switch (priv->variant) {
479 case RK806_ID:
480 if ((pldo < 3) || (pldo == 5)) {
481 en_reg = RK806_PLDO_EN(0);
482 mask = RK806_PLDO0_2_SET(pldo);
483 if (pldo == 5)
484 mask = (1 << 0);
485 ret = pmic_reg_read(pmic, en_reg);
486 } else if ((pldo == 3) || (pldo == 4)) {
487 en_reg = RK806_PLDO_EN(1);
488 if (pldo == 3)
489 mask = (1 << 0);
490 else
491 mask = (1 << 1);
492 ret = pmic_reg_read(pmic, en_reg);
493 }
494 break;
495
496 default:
497 return -EINVAL;
498 }
499
500 if (ret < 0)
501 return ret;
502
503 return ret & mask ? true : false;
504 }
505
_pldo_set_enable(struct udevice * pmic,int pldo,bool enable)506 static int _pldo_set_enable(struct udevice *pmic, int pldo, bool enable)
507 {
508 struct rk8xx_priv *priv = dev_get_priv(pmic);
509 uint value, en_reg;
510 int ret = 0;
511
512 switch (priv->variant) {
513 case RK806_ID:
514 if (pldo < 3) {
515 en_reg = RK806_PLDO_EN(0);
516 if (enable)
517 value = RK806_PLDO0_2_SET(pldo);
518 else
519 value = RK806_PLDO0_2_CLR(pldo);
520 ret = pmic_reg_write(pmic, en_reg, value);
521 } else if (pldo == 3) {
522 en_reg = RK806_PLDO_EN(1);
523 if (enable)
524 value = ((1 << 0) | (1 << 4));
525 else
526 value = (1 << 4);
527 ret = pmic_reg_write(pmic, en_reg, value);
528 } else if (pldo == 4) {
529 en_reg = RK806_PLDO_EN(1);
530 if (enable)
531 value = ((1 << 1) | (1 << 5));
532 else
533 value = ((0 << 1) | (1 << 5));
534 ret = pmic_reg_write(pmic, en_reg, value);
535 } else if (pldo == 5) {
536 en_reg = RK806_PLDO_EN(0);
537 if (enable)
538 value = ((1 << 0) | (1 << 4));
539 else
540 value = ((0 << 0) | (1 << 4));
541 ret = pmic_reg_write(pmic, en_reg, value);
542 }
543
544 break;
545 default:
546 return -EINVAL;
547 }
548
549 return ret;
550 }
551
_ldo_set_suspend_enable(struct udevice * pmic,int ldo,bool enable)552 static int _ldo_set_suspend_enable(struct udevice *pmic, int ldo, bool enable)
553 {
554 uint mask;
555 int ret;
556
557 mask = 1 << ldo;
558 ret = pmic_clrsetbits(pmic, RK806_NLDO_SUSPEND_EN, mask,
559 enable ? mask : 0);
560
561 return ret;
562 }
563
_ldo_get_suspend_enable(struct udevice * pmic,int ldo)564 static int _ldo_get_suspend_enable(struct udevice *pmic, int ldo)
565 {
566 uint mask, val;
567 int ret;
568
569 mask = 1 << ldo;
570 val = pmic_reg_read(pmic, RK806_NLDO_SUSPEND_EN);
571
572 if (val < 0)
573 return val;
574 ret = val & mask ? 1 : 0;
575
576 return ret;
577 }
578
buck_get_value(struct udevice * dev)579 static int buck_get_value(struct udevice *dev)
580 {
581 int buck = dev->driver_data - 1;
582 const struct rk8xx_reg_info *info = get_buck_reg(dev->parent, buck, 0);
583 int mask = info->vsel_mask;
584 int i, ret, val;
585
586 if (info->vsel_reg == NA)
587 return -EINVAL;
588
589 ret = pmic_reg_read(dev->parent, info->vsel_reg);
590 if (ret < 0)
591 return ret;
592
593 val = ret & mask;
594 if (val >= info->min_sel && val <= info->max_sel)
595 goto finish;
596
597 /* unlucky to try */
598 for (i = 1; i < info->range_num; i++) {
599 info++;
600 if (val <= info->max_sel && val >= info->min_sel)
601 break;
602 }
603
604 finish:
605 return info->min_uv + (val - info->min_sel) * info->step_uv;
606 }
607
buck_set_value(struct udevice * dev,int uvolt)608 static int buck_set_value(struct udevice *dev, int uvolt)
609 {
610 int buck = dev->driver_data - 1;
611
612 return _buck_set_value(dev->parent, buck, uvolt);
613 }
614
buck_get_suspend_value(struct udevice * dev)615 static int buck_get_suspend_value(struct udevice *dev)
616 {
617 int buck = dev->driver_data - 1;
618 const struct rk8xx_reg_info *info = get_buck_reg(dev->parent, buck, 0);
619 int mask = info->vsel_mask;
620 int i, ret, val;
621
622 if (info->vsel_sleep_reg == NA)
623 return -EINVAL;
624
625 ret = pmic_reg_read(dev->parent, info->vsel_sleep_reg);
626 if (ret < 0)
627 return ret;
628
629 val = ret & mask;
630 if (val <= info->max_sel && val >= info->min_sel)
631 goto finish;
632
633 /* unlucky to try */
634 for (i = 1; i < info->range_num; i++) {
635 info++;
636 if (val <= info->max_sel && val >= info->min_sel)
637 break;
638 }
639
640 finish:
641 return info->min_uv + (val - info->min_sel) * info->step_uv;
642 }
643
buck_set_suspend_value(struct udevice * dev,int uvolt)644 static int buck_set_suspend_value(struct udevice *dev, int uvolt)
645 {
646 int buck = dev->driver_data - 1;
647
648 return _buck_set_suspend_value(dev->parent, buck, uvolt);
649 }
650
buck_set_enable(struct udevice * dev,bool enable)651 static int buck_set_enable(struct udevice *dev, bool enable)
652 {
653 int buck = dev->driver_data - 1;
654
655 return _buck_set_enable(dev->parent, buck, enable);
656 }
657
buck_set_suspend_enable(struct udevice * dev,bool enable)658 static int buck_set_suspend_enable(struct udevice *dev, bool enable)
659 {
660 int buck = dev->driver_data - 1;
661
662 return _buck_set_suspend_enable(dev->parent, buck, enable);
663 }
664
buck_get_suspend_enable(struct udevice * dev)665 static int buck_get_suspend_enable(struct udevice *dev)
666 {
667 int buck = dev->driver_data - 1;
668
669 return _buck_get_suspend_enable(dev->parent, buck);
670 }
671
buck_set_ramp_delay(struct udevice * dev,u32 ramp_delay)672 static int buck_set_ramp_delay(struct udevice *dev, u32 ramp_delay)
673 {
674 int buck = dev->driver_data - 1;
675
676 return _buck_set_ramp_delay(dev->parent, buck, ramp_delay);
677 }
678
buck_get_enable(struct udevice * dev)679 static int buck_get_enable(struct udevice *dev)
680 {
681 int buck = dev->driver_data - 1;
682
683 return _buck_get_enable(dev->parent, buck);
684 }
685
ldo_get_value(struct udevice * dev)686 static int ldo_get_value(struct udevice *dev)
687 {
688 int ldo = dev->driver_data - 1;
689 const struct rk8xx_reg_info *info = get_ldo_reg(dev->parent, ldo, 0);
690 int mask = info->vsel_mask;
691 int ret, val;
692
693 if (info->vsel_reg == NA)
694 return -EINVAL;
695
696 ret = pmic_reg_read(dev->parent, info->vsel_reg);
697 if (ret < 0)
698 return ret;
699 val = ret & mask;
700
701 return info->min_uv + val * info->step_uv;
702 }
703
ldo_set_value(struct udevice * dev,int uvolt)704 static int ldo_set_value(struct udevice *dev, int uvolt)
705 {
706 int ldo = dev->driver_data - 1;
707 const struct rk8xx_reg_info *info = get_ldo_reg(dev->parent, ldo, uvolt);
708 int mask = info->vsel_mask;
709 int val;
710
711 if (info->vsel_reg == NA)
712 return -EINVAL;
713
714 if (info->step_uv == 0)
715 val = info->min_sel;
716 else
717 val = ((uvolt - info->min_uv) / info->step_uv) + info->min_sel;
718
719 debug("%s: volt=%d, ldo=%d, reg=0x%x, mask=0x%x, val=0x%x\n",
720 __func__, uvolt, ldo + 1, info->vsel_reg, mask, val);
721
722 return pmic_clrsetbits(dev->parent, info->vsel_reg, mask, val);
723 }
724
pldo_get_value(struct udevice * dev)725 static int pldo_get_value(struct udevice *dev)
726 {
727 int ldo = dev->driver_data - 1;
728 const struct rk8xx_reg_info *info = get_pldo_reg(dev->parent, ldo, 0);
729 int mask = info->vsel_mask;
730 int ret, val;
731
732 if (info->vsel_reg == NA)
733 return -EINVAL;
734
735 ret = pmic_reg_read(dev->parent, info->vsel_reg);
736 if (ret < 0)
737 return ret;
738 val = ret & mask;
739
740 return info->min_uv + val * info->step_uv;
741 }
742
pldo_set_value(struct udevice * dev,int uvolt)743 static int pldo_set_value(struct udevice *dev, int uvolt)
744 {
745 int ldo = dev->driver_data - 1;
746 const struct rk8xx_reg_info *info = get_pldo_reg(dev->parent, ldo, uvolt);
747 int mask = info->vsel_mask;
748 int val;
749
750 if (info->vsel_reg == NA)
751 return -EINVAL;
752
753 if (info->step_uv == 0)
754 val = info->min_sel;
755 else
756 val = ((uvolt - info->min_uv) / info->step_uv) + info->min_sel;
757
758 debug("%s: volt=%d, ldo=%d, reg=0x%x, mask=0x%x, val=0x%x\n",
759 __func__, uvolt, ldo + 1, info->vsel_reg, mask, val);
760
761 return pmic_clrsetbits(dev->parent, info->vsel_reg, mask, val);
762 }
763
ldo_set_suspend_value(struct udevice * dev,int uvolt)764 static int ldo_set_suspend_value(struct udevice *dev, int uvolt)
765 {
766 int ldo = dev->driver_data - 1;
767 const struct rk8xx_reg_info *info = get_ldo_reg(dev->parent, ldo, uvolt);
768 int mask = info->vsel_mask;
769 int val;
770
771 if (info->vsel_sleep_reg == NA)
772 return -EINVAL;
773
774 if (info->step_uv == 0)
775 val = info->min_sel;
776 else
777 val = ((uvolt - info->min_uv) / info->step_uv) + info->min_sel;
778
779 debug("%s: volt=%d, ldo=%d, reg=0x%x, mask=0x%x, val=0x%x\n",
780 __func__, uvolt, ldo + 1, info->vsel_sleep_reg, mask, val);
781
782 return pmic_clrsetbits(dev->parent, info->vsel_sleep_reg, mask, val);
783 }
784
ldo_get_suspend_value(struct udevice * dev)785 static int ldo_get_suspend_value(struct udevice *dev)
786 {
787 int ldo = dev->driver_data - 1;
788 const struct rk8xx_reg_info *info = get_ldo_reg(dev->parent, ldo, 0);
789 int mask = info->vsel_mask;
790 int val, ret;
791
792 if (info->vsel_sleep_reg == NA)
793 return -EINVAL;
794
795 ret = pmic_reg_read(dev->parent, info->vsel_sleep_reg);
796 if (ret < 0)
797 return ret;
798
799 val = ret & mask;
800
801 return info->min_uv + val * info->step_uv;
802 }
803
ldo_set_enable(struct udevice * dev,bool enable)804 static int ldo_set_enable(struct udevice *dev, bool enable)
805 {
806 int ldo = dev->driver_data - 1;
807
808 return _ldo_set_enable(dev->parent, ldo, enable);
809 }
810
ldo_set_suspend_enable(struct udevice * dev,bool enable)811 static int ldo_set_suspend_enable(struct udevice *dev, bool enable)
812 {
813 int ldo = dev->driver_data - 1;
814
815 return _ldo_set_suspend_enable(dev->parent, ldo, enable);
816 }
817
ldo_get_suspend_enable(struct udevice * dev)818 static int ldo_get_suspend_enable(struct udevice *dev)
819 {
820 int ldo = dev->driver_data - 1;
821
822 return _ldo_get_suspend_enable(dev->parent, ldo);
823 }
824
ldo_get_enable(struct udevice * dev)825 static int ldo_get_enable(struct udevice *dev)
826 {
827 int ldo = dev->driver_data - 1;
828
829 return _ldo_get_enable(dev->parent, ldo);
830 }
831
pldo_set_enable(struct udevice * dev,bool enable)832 static int pldo_set_enable(struct udevice *dev, bool enable)
833 {
834 int ldo = dev->driver_data - 1;
835
836 return _pldo_set_enable(dev->parent, ldo, enable);
837 }
838
pldo_get_enable(struct udevice * dev)839 static int pldo_get_enable(struct udevice *dev)
840 {
841 int ldo = dev->driver_data - 1;
842
843 return _pldo_get_enable(dev->parent, ldo);
844 }
845
pldo_set_suspend_value(struct udevice * dev,int uvolt)846 static int pldo_set_suspend_value(struct udevice *dev, int uvolt)
847 {
848 int ldo = dev->driver_data - 1;
849 const struct rk8xx_reg_info *info = get_pldo_reg(dev->parent, ldo, uvolt);;
850 int mask = info->vsel_mask;
851 int val;
852
853 if (info->vsel_sleep_reg == NA)
854 return -EINVAL;
855
856 if (info->step_uv == 0)
857 val = info->min_sel;
858 else
859 val = ((uvolt - info->min_uv) / info->step_uv) + info->min_sel;
860
861 return pmic_clrsetbits(dev->parent, info->vsel_sleep_reg, mask, val);
862 }
863
pldo_get_suspend_value(struct udevice * dev)864 static int pldo_get_suspend_value(struct udevice *dev)
865 {
866 int ldo = dev->driver_data - 1;
867 const struct rk8xx_reg_info *info = get_pldo_reg(dev->parent, ldo, 0);
868 int mask = info->vsel_mask;
869 int val, ret;
870
871 if (info->vsel_sleep_reg == NA)
872 return -EINVAL;
873
874 ret = pmic_reg_read(dev->parent, info->vsel_sleep_reg);
875 if (ret < 0)
876 return ret;
877
878 val = ret & mask;
879
880 return info->min_uv + val * info->step_uv;
881 }
882
_pldo_set_suspend_enable(struct udevice * pmic,int ldo,bool enable)883 static int _pldo_set_suspend_enable(struct udevice *pmic, int ldo, bool enable)
884 {
885 uint mask;
886 int ret;
887
888 if (ldo < 5)
889 mask = 1 << (ldo + 1);
890 else
891 mask = 1;
892 ret = pmic_clrsetbits(pmic, RK806_PLDO_SUSPEND_EN, mask,
893 enable ? mask : 0);
894
895 return ret;
896 }
897
_pldo_get_suspend_enable(struct udevice * pmic,int ldo)898 static int _pldo_get_suspend_enable(struct udevice *pmic, int ldo)
899 {
900 uint mask, val;
901 int ret;
902
903 if (ldo < 5)
904 mask = 1 << (ldo + 1);
905 else
906 mask = 1;
907 val = pmic_reg_read(pmic, RK806_PLDO_SUSPEND_EN);
908
909 if (val < 0)
910 return val;
911 ret = val & mask ? 1 : 0;
912
913 return ret;
914 }
915
pldo_set_suspend_enable(struct udevice * dev,bool enable)916 static int pldo_set_suspend_enable(struct udevice *dev, bool enable)
917 {
918 int ldo = dev->driver_data - 1;
919
920 return _pldo_set_suspend_enable(dev->parent, ldo, enable);
921 }
922
pldo_get_suspend_enable(struct udevice * dev)923 static int pldo_get_suspend_enable(struct udevice *dev)
924 {
925 int ldo = dev->driver_data - 1;
926
927 return _pldo_get_suspend_enable(dev->parent, ldo);
928 }
929
rk8xx_buck_probe(struct udevice * dev)930 static int rk8xx_buck_probe(struct udevice *dev)
931 {
932 struct dm_regulator_uclass_platdata *uc_pdata;
933
934 uc_pdata = dev_get_uclass_platdata(dev);
935 uc_pdata->type = REGULATOR_TYPE_BUCK;
936 uc_pdata->mode_count = 0;
937
938 return 0;
939 }
940
rk8xx_ldo_probe(struct udevice * dev)941 static int rk8xx_ldo_probe(struct udevice *dev)
942 {
943 struct dm_regulator_uclass_platdata *uc_pdata;
944
945 uc_pdata = dev_get_uclass_platdata(dev);
946 uc_pdata->type = REGULATOR_TYPE_LDO;
947 uc_pdata->mode_count = 0;
948
949 return 0;
950 }
951
rk8xx_pldo_probe(struct udevice * dev)952 static int rk8xx_pldo_probe(struct udevice *dev)
953 {
954 struct dm_regulator_uclass_platdata *uc_pdata;
955
956 uc_pdata = dev_get_uclass_platdata(dev);
957 uc_pdata->type = REGULATOR_TYPE_LDO;
958 uc_pdata->mode_count = 0;
959
960 return 0;
961 }
962
963 static const struct dm_regulator_ops rk8xx_buck_ops = {
964 .get_value = buck_get_value,
965 .set_value = buck_set_value,
966 .set_suspend_value = buck_set_suspend_value,
967 .get_suspend_value = buck_get_suspend_value,
968 .get_enable = buck_get_enable,
969 .set_enable = buck_set_enable,
970 .set_suspend_enable = buck_set_suspend_enable,
971 .get_suspend_enable = buck_get_suspend_enable,
972 .set_ramp_delay = buck_set_ramp_delay,
973 };
974
975 static const struct dm_regulator_ops rk8xx_ldo_ops = {
976 .get_value = ldo_get_value,
977 .set_value = ldo_set_value,
978 .set_suspend_value = ldo_set_suspend_value,
979 .get_suspend_value = ldo_get_suspend_value,
980 .get_enable = ldo_get_enable,
981 .set_enable = ldo_set_enable,
982 .set_suspend_enable = ldo_set_suspend_enable,
983 .get_suspend_enable = ldo_get_suspend_enable,
984 };
985
986 static const struct dm_regulator_ops rk8xx_pldo_ops = {
987 .get_value = pldo_get_value,
988 .set_value = pldo_set_value,
989 .set_suspend_value = pldo_set_suspend_value,
990 .get_suspend_value = pldo_get_suspend_value,
991 .get_enable = pldo_get_enable,
992 .set_enable = pldo_set_enable,
993 .set_suspend_enable = pldo_set_suspend_enable,
994 .get_suspend_enable = pldo_get_suspend_enable,
995 };
996
997 U_BOOT_DRIVER(rk8xx_spi_buck) = {
998 .name = "rk8xx_spi_buck",
999 .id = UCLASS_REGULATOR,
1000 .ops = &rk8xx_buck_ops,
1001 .probe = rk8xx_buck_probe,
1002 };
1003
1004 U_BOOT_DRIVER(rk8xx_spi_ldo) = {
1005 .name = "rk8xx_spi_ldo",
1006 .id = UCLASS_REGULATOR,
1007 .ops = &rk8xx_ldo_ops,
1008 .probe = rk8xx_ldo_probe,
1009 };
1010
1011 U_BOOT_DRIVER(rk8xx_spi_pldo) = {
1012 .name = "rk8xx_spi_pldo",
1013 .id = UCLASS_REGULATOR,
1014 .ops = &rk8xx_pldo_ops,
1015 .probe = rk8xx_pldo_probe,
1016 };
1017 #endif
1018