1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * (C) Copyright 2022 Rockchip Electronics Co., Ltd
4 */
5
6 #include <common.h>
7 #include <dm.h>
8 #include <dm/pinctrl.h>
9 #include <regmap.h>
10 #include <syscon.h>
11
12 #include "pinctrl-rockchip.h"
13
rk3562_set_mux(struct rockchip_pin_bank * bank,int pin,int mux)14 static int rk3562_set_mux(struct rockchip_pin_bank *bank, int pin, int mux)
15 {
16 struct rockchip_pinctrl_priv *priv = bank->priv;
17 int iomux_num = (pin / 8);
18 struct regmap *regmap;
19 int reg, ret, mask;
20 u8 bit;
21 u32 data;
22
23 debug("setting mux of GPIO%d-%d to %d\n", bank->bank_num, pin, mux);
24
25 regmap = priv->regmap_base;
26 reg = bank->iomux[iomux_num].offset;
27 if ((pin % 8) >= 4)
28 reg += 0x4;
29 bit = (pin % 4) * 4;
30 mask = 0xf;
31
32 data = (mask << (bit + 16));
33 data |= (mux & mask) << bit;
34
35 /* force jtag m1 */
36 if (bank->bank_num == 1) {
37 if ((pin == 13) || (pin == 14)) {
38 if (mux == 1) {
39 regmap_write(regmap, 0x504, 0x10001);
40 } else {
41 regmap_write(regmap, 0x504, 0x10000);
42 }
43 }
44 }
45
46 debug("iomux write reg = %x data = %x\n", reg, data);
47
48 ret = regmap_write(regmap, reg, data);
49
50 return ret;
51 }
52
53 #define RK3562_DRV_BITS_PER_PIN 8
54 #define RK3562_DRV_PINS_PER_REG 2
55 #define RK3562_DRV_GPIO0_OFFSET 0x20070
56 #define RK3562_DRV_GPIO1_OFFSET 0x200
57 #define RK3562_DRV_GPIO2_OFFSET 0x240
58 #define RK3562_DRV_GPIO3_OFFSET 0x10280
59 #define RK3562_DRV_GPIO4_OFFSET 0x102C0
60
rk3562_calc_drv_reg_and_bit(struct rockchip_pin_bank * bank,int pin_num,struct regmap ** regmap,int * reg,u8 * bit)61 static void rk3562_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
62 int pin_num, struct regmap **regmap,
63 int *reg, u8 *bit)
64 {
65 struct rockchip_pinctrl_priv *priv = bank->priv;
66
67 *regmap = priv->regmap_base;
68 switch (bank->bank_num) {
69 case 0:
70 *reg = RK3562_DRV_GPIO0_OFFSET;
71 break;
72
73 case 1:
74 *reg = RK3562_DRV_GPIO1_OFFSET;
75 break;
76
77 case 2:
78 *reg = RK3562_DRV_GPIO2_OFFSET;
79 break;
80
81 case 3:
82 *reg = RK3562_DRV_GPIO3_OFFSET;
83 break;
84
85 case 4:
86 *reg = RK3562_DRV_GPIO4_OFFSET;
87 break;
88
89 default:
90 *reg = 0;
91 dev_err(priv->dev, "unsupported bank_num %d\n", bank->bank_num);
92 break;
93 }
94
95 *reg += ((pin_num / RK3562_DRV_PINS_PER_REG) * 4);
96 *bit = pin_num % RK3562_DRV_PINS_PER_REG;
97 *bit *= RK3562_DRV_BITS_PER_PIN;
98 }
99
rk3562_set_drive(struct rockchip_pin_bank * bank,int pin_num,int strength)100 static int rk3562_set_drive(struct rockchip_pin_bank *bank,
101 int pin_num, int strength)
102 {
103 struct regmap *regmap;
104 int reg, ret;
105 u32 data;
106 u8 bit;
107 int drv = (1 << (strength + 1)) - 1;
108
109 rk3562_calc_drv_reg_and_bit(bank, pin_num, ®map, ®, &bit);
110
111 /* enable the write to the equivalent lower bits */
112 data = ((1 << RK3562_DRV_BITS_PER_PIN) - 1) << (bit + 16);
113 data |= (drv << bit);
114 ret = regmap_write(regmap, reg, data);
115
116 return ret;
117 }
118
119 #define RK3562_PULL_BITS_PER_PIN 2
120 #define RK3562_PULL_PINS_PER_REG 8
121 #define RK3562_PULL_GPIO0_OFFSET 0x20020
122 #define RK3562_PULL_GPIO1_OFFSET 0x80
123 #define RK3562_PULL_GPIO2_OFFSET 0x90
124 #define RK3562_PULL_GPIO3_OFFSET 0x100A0
125 #define RK3562_PULL_GPIO4_OFFSET 0x100B0
126
rk3562_calc_pull_reg_and_bit(struct rockchip_pin_bank * bank,int pin_num,struct regmap ** regmap,int * reg,u8 * bit)127 static void rk3562_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
128 int pin_num, struct regmap **regmap,
129 int *reg, u8 *bit)
130 {
131 struct rockchip_pinctrl_priv *priv = bank->priv;
132
133 *regmap = priv->regmap_base;
134 switch (bank->bank_num) {
135 case 0:
136 *reg = RK3562_PULL_GPIO0_OFFSET;
137 break;
138
139 case 1:
140 *reg = RK3562_PULL_GPIO1_OFFSET;
141 break;
142
143 case 2:
144 *reg = RK3562_PULL_GPIO2_OFFSET;
145 break;
146
147 case 3:
148 *reg = RK3562_PULL_GPIO3_OFFSET;
149 break;
150
151 case 4:
152 *reg = RK3562_PULL_GPIO4_OFFSET;
153 break;
154
155 default:
156 *reg = 0;
157 dev_err(priv->dev, "unsupported bank_num %d\n", bank->bank_num);
158 break;
159 }
160
161 *reg += ((pin_num / RK3562_PULL_PINS_PER_REG) * 4);
162 *bit = pin_num % RK3562_PULL_PINS_PER_REG;
163 *bit *= RK3562_PULL_BITS_PER_PIN;
164 }
165
rk3562_set_pull(struct rockchip_pin_bank * bank,int pin_num,int pull)166 static int rk3562_set_pull(struct rockchip_pin_bank *bank,
167 int pin_num, int pull)
168 {
169 struct regmap *regmap;
170 int reg, ret;
171 u8 bit, type;
172 u32 data;
173
174 if (pull == PIN_CONFIG_BIAS_PULL_PIN_DEFAULT)
175 return -ENOTSUPP;
176
177 rk3562_calc_pull_reg_and_bit(bank, pin_num, ®map, ®, &bit);
178 type = bank->pull_type[pin_num / 8];
179 ret = rockchip_translate_pull_value(type, pull);
180 if (ret < 0) {
181 debug("unsupported pull setting %d\n", pull);
182 return ret;
183 }
184
185 /* enable the write to the equivalent lower bits */
186 data = ((1 << RK3562_PULL_BITS_PER_PIN) - 1) << (bit + 16);
187
188 data |= (ret << bit);
189 ret = regmap_write(regmap, reg, data);
190
191 return ret;
192 }
193
194 #define RK3562_SMT_BITS_PER_PIN 2
195 #define RK3562_SMT_PINS_PER_REG 8
196 #define RK3562_SMT_GPIO0_OFFSET 0x20030
197 #define RK3562_SMT_GPIO1_OFFSET 0xC0
198 #define RK3562_SMT_GPIO2_OFFSET 0xD0
199 #define RK3562_SMT_GPIO3_OFFSET 0x100E0
200 #define RK3562_SMT_GPIO4_OFFSET 0x100F0
201
rk3562_calc_schmitt_reg_and_bit(struct rockchip_pin_bank * bank,int pin_num,struct regmap ** regmap,int * reg,u8 * bit)202 static int rk3562_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank,
203 int pin_num,
204 struct regmap **regmap,
205 int *reg, u8 *bit)
206 {
207 struct rockchip_pinctrl_priv *priv = bank->priv;
208
209 *regmap = priv->regmap_base;
210 switch (bank->bank_num) {
211 case 0:
212 *reg = RK3562_SMT_GPIO0_OFFSET;
213 break;
214
215 case 1:
216 *reg = RK3562_SMT_GPIO1_OFFSET;
217 break;
218
219 case 2:
220 *reg = RK3562_SMT_GPIO2_OFFSET;
221 break;
222
223 case 3:
224 *reg = RK3562_SMT_GPIO3_OFFSET;
225 break;
226
227 case 4:
228 *reg = RK3562_SMT_GPIO4_OFFSET;
229 break;
230
231 default:
232 *reg = 0;
233 dev_err(priv->dev, "unsupported bank_num %d\n", bank->bank_num);
234 break;
235 }
236
237 *reg += ((pin_num / RK3562_SMT_PINS_PER_REG) * 4);
238 *bit = pin_num % RK3562_SMT_PINS_PER_REG;
239 *bit *= RK3562_SMT_BITS_PER_PIN;
240
241 return 0;
242 }
243
rk3562_set_schmitt(struct rockchip_pin_bank * bank,int pin_num,int enable)244 static int rk3562_set_schmitt(struct rockchip_pin_bank *bank,
245 int pin_num, int enable)
246 {
247 struct regmap *regmap;
248 int reg, ret;
249 u32 data;
250 u8 bit;
251
252 rk3562_calc_schmitt_reg_and_bit(bank, pin_num, ®map, ®, &bit);
253
254 /* enable the write to the equivalent lower bits */
255 data = ((1 << RK3562_SMT_BITS_PER_PIN) - 1) << (bit + 16);
256 data |= (enable << bit);
257 ret = regmap_write(regmap, reg, data);
258
259 return ret;
260 }
261
262 static struct rockchip_pin_bank rk3562_pin_banks[] = {
263 PIN_BANK_IOMUX_FLAGS_OFFSET(0, 32, "gpio0",
264 IOMUX_WIDTH_4BIT,
265 IOMUX_WIDTH_4BIT,
266 IOMUX_WIDTH_4BIT,
267 IOMUX_WIDTH_4BIT,
268 0x20000, 0x20008, 0x20010, 0x20018),
269 PIN_BANK_IOMUX_FLAGS_OFFSET(1, 32, "gpio1",
270 IOMUX_WIDTH_4BIT,
271 IOMUX_WIDTH_4BIT,
272 IOMUX_WIDTH_4BIT,
273 IOMUX_WIDTH_4BIT,
274 0, 0x08, 0x10, 0x18),
275 PIN_BANK_IOMUX_FLAGS_OFFSET(2, 32, "gpio2",
276 IOMUX_WIDTH_4BIT,
277 IOMUX_WIDTH_4BIT,
278 IOMUX_WIDTH_4BIT,
279 IOMUX_WIDTH_4BIT,
280 0x20, 0, 0, 0),
281 PIN_BANK_IOMUX_FLAGS_OFFSET(3, 32, "gpio3",
282 IOMUX_WIDTH_4BIT,
283 IOMUX_WIDTH_4BIT,
284 IOMUX_WIDTH_4BIT,
285 IOMUX_WIDTH_4BIT,
286 0x10040, 0x10048, 0x10050, 0x10058),
287 PIN_BANK_IOMUX_FLAGS_OFFSET(4, 16, "gpio4",
288 IOMUX_WIDTH_4BIT,
289 IOMUX_WIDTH_4BIT,
290 0,
291 0,
292 0x10060, 0x10068, 0, 0),
293 };
294
295 static const struct rockchip_pin_ctrl rk3562_pin_ctrl = {
296 .pin_banks = rk3562_pin_banks,
297 .nr_banks = ARRAY_SIZE(rk3562_pin_banks),
298 .nr_pins = 144,
299 .grf_mux_offset = 0x0,
300 .set_mux = rk3562_set_mux,
301 .set_pull = rk3562_set_pull,
302 .set_drive = rk3562_set_drive,
303 .set_schmitt = rk3562_set_schmitt,
304 };
305
306 static const struct udevice_id rk3562_pinctrl_ids[] = {
307 {
308 .compatible = "rockchip,rk3562-pinctrl",
309 .data = (ulong)&rk3562_pin_ctrl
310 },
311 { }
312 };
313
314 U_BOOT_DRIVER(pinctrl_rk3562) = {
315 .name = "rockchip_rk3562_pinctrl",
316 .id = UCLASS_PINCTRL,
317 .of_match = rk3562_pinctrl_ids,
318 .priv_auto_alloc_size = sizeof(struct rockchip_pinctrl_priv),
319 .ops = &rockchip_pinctrl_ops,
320 #if !CONFIG_IS_ENABLED(OF_PLATDATA)
321 .bind = dm_scan_fdt_dev,
322 #endif
323 .probe = rockchip_pinctrl_probe,
324 };
325