1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * (C) Copyright 2019 Rockchip Electronics Co., Ltd
4 */
5
6 #include <common.h>
7 #include <dm.h>
8 #include <dm/pinctrl.h>
9 #include <regmap.h>
10 #include <syscon.h>
11
12 #include "pinctrl-rockchip.h"
13
14 static struct rockchip_mux_route_data rk3228_mux_route_data[] = {
15 {
16 /* pwm0-0 */
17 .bank_num = 0,
18 .pin = 26,
19 .func = 1,
20 .route_offset = 0x50,
21 .route_val = BIT(16),
22 }, {
23 /* pwm0-1 */
24 .bank_num = 3,
25 .pin = 21,
26 .func = 1,
27 .route_offset = 0x50,
28 .route_val = BIT(16) | BIT(0),
29 }, {
30 /* pwm1-0 */
31 .bank_num = 0,
32 .pin = 27,
33 .func = 1,
34 .route_offset = 0x50,
35 .route_val = BIT(16 + 1),
36 }, {
37 /* pwm1-1 */
38 .bank_num = 0,
39 .pin = 30,
40 .func = 2,
41 .route_offset = 0x50,
42 .route_val = BIT(16 + 1) | BIT(1),
43 }, {
44 /* pwm2-0 */
45 .bank_num = 0,
46 .pin = 28,
47 .func = 1,
48 .route_offset = 0x50,
49 .route_val = BIT(16 + 2),
50 }, {
51 /* pwm2-1 */
52 .bank_num = 1,
53 .pin = 12,
54 .func = 2,
55 .route_offset = 0x50,
56 .route_val = BIT(16 + 2) | BIT(2),
57 }, {
58 /* pwm3-0 */
59 .bank_num = 3,
60 .pin = 26,
61 .func = 1,
62 .route_offset = 0x50,
63 .route_val = BIT(16 + 3),
64 }, {
65 /* pwm3-1 */
66 .bank_num = 1,
67 .pin = 11,
68 .func = 2,
69 .route_offset = 0x50,
70 .route_val = BIT(16 + 3) | BIT(3),
71 }, {
72 /* sdio-0_d0 */
73 .bank_num = 1,
74 .pin = 1,
75 .func = 1,
76 .route_offset = 0x50,
77 .route_val = BIT(16 + 4),
78 }, {
79 /* sdio-1_d0 */
80 .bank_num = 3,
81 .pin = 2,
82 .func = 1,
83 .route_offset = 0x50,
84 .route_val = BIT(16 + 4) | BIT(4),
85 }, {
86 /* spi-0_rx */
87 .bank_num = 0,
88 .pin = 13,
89 .func = 2,
90 .route_offset = 0x50,
91 .route_val = BIT(16 + 5),
92 }, {
93 /* spi-1_rx */
94 .bank_num = 2,
95 .pin = 0,
96 .func = 2,
97 .route_offset = 0x50,
98 .route_val = BIT(16 + 5) | BIT(5),
99 }, {
100 /* emmc-0_cmd */
101 .bank_num = 1,
102 .pin = 22,
103 .func = 2,
104 .route_offset = 0x50,
105 .route_val = BIT(16 + 7),
106 }, {
107 /* emmc-1_cmd */
108 .bank_num = 2,
109 .pin = 4,
110 .func = 2,
111 .route_offset = 0x50,
112 .route_val = BIT(16 + 7) | BIT(7),
113 }, {
114 /* uart2-0_rx */
115 .bank_num = 1,
116 .pin = 19,
117 .func = 2,
118 .route_offset = 0x50,
119 .route_val = BIT(16 + 8),
120 }, {
121 /* uart2-1_rx */
122 .bank_num = 1,
123 .pin = 10,
124 .func = 2,
125 .route_offset = 0x50,
126 .route_val = BIT(16 + 8) | BIT(8),
127 }, {
128 /* uart1-0_rx */
129 .bank_num = 1,
130 .pin = 10,
131 .func = 1,
132 .route_offset = 0x50,
133 .route_val = BIT(16 + 11),
134 }, {
135 /* uart1-1_rx */
136 .bank_num = 3,
137 .pin = 13,
138 .func = 1,
139 .route_offset = 0x50,
140 .route_val = BIT(16 + 11) | BIT(11),
141 },
142 };
143
rk3228_set_mux(struct rockchip_pin_bank * bank,int pin,int mux)144 static int rk3228_set_mux(struct rockchip_pin_bank *bank, int pin, int mux)
145 {
146 struct rockchip_pinctrl_priv *priv = bank->priv;
147 int iomux_num = (pin / 8);
148 struct regmap *regmap;
149 int reg, ret, mask, mux_type;
150 u8 bit;
151 u32 data;
152
153 regmap = (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU)
154 ? priv->regmap_pmu : priv->regmap_base;
155
156 /* get basic quadrupel of mux registers and the correct reg inside */
157 mux_type = bank->iomux[iomux_num].type;
158 reg = bank->iomux[iomux_num].offset;
159 reg += rockchip_get_mux_data(mux_type, pin, &bit, &mask);
160
161 data = (mask << (bit + 16));
162 data |= (mux & mask) << bit;
163 ret = regmap_write(regmap, reg, data);
164
165 return ret;
166 }
167
168 #define RK3228_PULL_OFFSET 0x100
169
rk3228_calc_pull_reg_and_bit(struct rockchip_pin_bank * bank,int pin_num,struct regmap ** regmap,int * reg,u8 * bit)170 static void rk3228_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
171 int pin_num, struct regmap **regmap,
172 int *reg, u8 *bit)
173 {
174 struct rockchip_pinctrl_priv *priv = bank->priv;
175
176 *regmap = priv->regmap_base;
177 *reg = RK3228_PULL_OFFSET;
178 *reg += bank->bank_num * ROCKCHIP_PULL_BANK_STRIDE;
179 *reg += ((pin_num / ROCKCHIP_PULL_PINS_PER_REG) * 4);
180
181 *bit = (pin_num % ROCKCHIP_PULL_PINS_PER_REG);
182 *bit *= ROCKCHIP_PULL_BITS_PER_PIN;
183 }
184
rk3228_set_pull(struct rockchip_pin_bank * bank,int pin_num,int pull)185 static int rk3228_set_pull(struct rockchip_pin_bank *bank,
186 int pin_num, int pull)
187 {
188 struct regmap *regmap;
189 int reg, ret;
190 u8 bit, type;
191 u32 data;
192
193 if (pull == PIN_CONFIG_BIAS_PULL_PIN_DEFAULT)
194 return -ENOTSUPP;
195
196 rk3228_calc_pull_reg_and_bit(bank, pin_num, ®map, ®, &bit);
197 type = bank->pull_type[pin_num / 8];
198 ret = rockchip_translate_pull_value(type, pull);
199 if (ret < 0) {
200 debug("unsupported pull setting %d\n", pull);
201 return ret;
202 }
203
204 /* enable the write to the equivalent lower bits */
205 data = ((1 << ROCKCHIP_PULL_BITS_PER_PIN) - 1) << (bit + 16);
206 data |= (ret << bit);
207 ret = regmap_write(regmap, reg, data);
208
209 return ret;
210 }
211
212 #define RK3228_DRV_GRF_OFFSET 0x200
213
rk3228_calc_drv_reg_and_bit(struct rockchip_pin_bank * bank,int pin_num,struct regmap ** regmap,int * reg,u8 * bit)214 static void rk3228_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
215 int pin_num, struct regmap **regmap,
216 int *reg, u8 *bit)
217 {
218 struct rockchip_pinctrl_priv *priv = bank->priv;
219
220 *regmap = priv->regmap_base;
221 *reg = RK3228_DRV_GRF_OFFSET;
222 *reg += bank->bank_num * ROCKCHIP_DRV_BANK_STRIDE;
223 *reg += ((pin_num / ROCKCHIP_DRV_PINS_PER_REG) * 4);
224
225 *bit = (pin_num % ROCKCHIP_DRV_PINS_PER_REG);
226 *bit *= ROCKCHIP_DRV_BITS_PER_PIN;
227 }
228
rk3228_set_drive(struct rockchip_pin_bank * bank,int pin_num,int strength)229 static int rk3228_set_drive(struct rockchip_pin_bank *bank,
230 int pin_num, int strength)
231 {
232 struct regmap *regmap;
233 int reg, ret;
234 u32 data;
235 u8 bit;
236 int type = bank->drv[pin_num / 8].drv_type;
237
238 rk3228_calc_drv_reg_and_bit(bank, pin_num, ®map, ®, &bit);
239 ret = rockchip_translate_drive_value(type, strength);
240 if (ret < 0) {
241 debug("unsupported driver strength %d\n", strength);
242 return ret;
243 }
244
245 /* enable the write to the equivalent lower bits */
246 data = ((1 << ROCKCHIP_DRV_BITS_PER_PIN) - 1) << (bit + 16);
247 data |= (ret << bit);
248 ret = regmap_write(regmap, reg, data);
249 return ret;
250 }
251
252 static struct rockchip_pin_bank rk3228_pin_banks[] = {
253 PIN_BANK(0, 32, "gpio0"),
254 PIN_BANK(1, 32, "gpio1"),
255 PIN_BANK(2, 32, "gpio2"),
256 PIN_BANK(3, 32, "gpio3"),
257 };
258
259 static struct rockchip_pin_ctrl rk3228_pin_ctrl = {
260 .pin_banks = rk3228_pin_banks,
261 .nr_banks = ARRAY_SIZE(rk3228_pin_banks),
262 .nr_pins = 128,
263 .grf_mux_offset = 0x0,
264 .iomux_routes = rk3228_mux_route_data,
265 .niomux_routes = ARRAY_SIZE(rk3228_mux_route_data),
266 .set_mux = rk3228_set_mux,
267 .set_pull = rk3228_set_pull,
268 .set_drive = rk3228_set_drive,
269 };
270
271 static const struct udevice_id rk3228_pinctrl_ids[] = {
272 {
273 .compatible = "rockchip,rk3228-pinctrl",
274 .data = (ulong)&rk3228_pin_ctrl
275 },
276 { }
277 };
278
279 U_BOOT_DRIVER(pinctrl_rk3228) = {
280 .name = "rockchip_rk3228_pinctrl",
281 .id = UCLASS_PINCTRL,
282 .of_match = rk3228_pinctrl_ids,
283 .priv_auto_alloc_size = sizeof(struct rockchip_pinctrl_priv),
284 .ops = &rockchip_pinctrl_ops,
285 #if !CONFIG_IS_ENABLED(OF_PLATDATA)
286 .bind = dm_scan_fdt_dev,
287 #endif
288 .probe = rockchip_pinctrl_probe,
289 };
290