1 /*
2 * (C) Copyright 2018 Rockchip Electronics Co., Ltd
3 *
4 * SPDX-License-Identifier: GPL-2.0+
5 */
6
7 #include <common.h>
8 #include <dm.h>
9 #include <dm/pinctrl.h>
10 #include <dm/ofnode.h>
11 #include <linux/bitops.h>
12 #include <regmap.h>
13 #include <syscon.h>
14 #include <asm/arch/cpu.h>
15 #include <dt-bindings/pinctrl/rockchip.h>
16
17 #define MAX_ROCKCHIP_GPIO_PER_BANK 32
18 #define RK_FUNC_GPIO 0
19 #define MAX_ROCKCHIP_PINS_ENTRIES 30
20
21 enum rockchip_pinctrl_type {
22 PX30,
23 RV1108,
24 RV1126,
25 RK1808,
26 RK2928,
27 RK3066B,
28 RK3128,
29 RK3188,
30 RK3288,
31 RK3308,
32 RK3368,
33 RK3399,
34 };
35
36 #define RK_GENMASK_VAL(h, l, v) \
37 (GENMASK(((h) + 16), ((l) + 16)) | (((v) << (l)) & GENMASK((h), (l))))
38
39 /**
40 * Encode variants of iomux registers into a type variable
41 */
42 #define IOMUX_GPIO_ONLY BIT(0)
43 #define IOMUX_WIDTH_4BIT BIT(1)
44 #define IOMUX_SOURCE_PMU BIT(2)
45 #define IOMUX_UNROUTED BIT(3)
46 #define IOMUX_WIDTH_3BIT BIT(4)
47 #define IOMUX_8WIDTH_2BIT BIT(5)
48 #define IOMUX_WRITABLE_32BIT BIT(6)
49 #define IOMUX_L_SOURCE_PMU BIT(7)
50
51 /**
52 * @type: iomux variant using IOMUX_* constants
53 * @offset: if initialized to -1 it will be autocalculated, by specifying
54 * an initial offset value the relevant source offset can be reset
55 * to a new value for autocalculating the following iomux registers.
56 */
57 struct rockchip_iomux {
58 int type;
59 int offset;
60 };
61
62 #define DRV_TYPE_IO_MASK GENMASK(31, 16)
63 #define DRV_TYPE_WRITABLE_32BIT BIT(31)
64
65 /**
66 * enum type index corresponding to rockchip_perpin_drv_list arrays index.
67 */
68 enum rockchip_pin_drv_type {
69 DRV_TYPE_IO_DEFAULT = 0,
70 DRV_TYPE_IO_1V8_OR_3V0,
71 DRV_TYPE_IO_1V8_ONLY,
72 DRV_TYPE_IO_1V8_3V0_AUTO,
73 DRV_TYPE_IO_3V3_ONLY,
74 DRV_TYPE_IO_SMIC,
75 DRV_TYPE_MAX
76 };
77
78 #define PULL_TYPE_IO_MASK GENMASK(31, 16)
79 #define PULL_TYPE_WRITABLE_32BIT BIT(31)
80
81 /**
82 * enum type index corresponding to rockchip_pull_list arrays index.
83 */
84 enum rockchip_pin_pull_type {
85 PULL_TYPE_IO_DEFAULT = 0,
86 PULL_TYPE_IO_1V8_ONLY,
87 PULL_TYPE_MAX
88 };
89
90 /**
91 * enum mux route register type, should be invalid/default/topgrf/pmugrf.
92 * INVALID: means do not need to set mux route
93 * DEFAULT: means same regmap as pin iomux
94 * TOPGRF: means mux route setting in topgrf
95 * PMUGRF: means mux route setting in pmugrf
96 */
97 enum rockchip_pin_route_type {
98 ROUTE_TYPE_DEFAULT = 0,
99 ROUTE_TYPE_TOPGRF = 1,
100 ROUTE_TYPE_PMUGRF = 2,
101
102 ROUTE_TYPE_INVALID = -1,
103 };
104
105 /**
106 * @drv_type: drive strength variant using rockchip_perpin_drv_type
107 * @offset: if initialized to -1 it will be autocalculated, by specifying
108 * an initial offset value the relevant source offset can be reset
109 * to a new value for autocalculating the following drive strength
110 * registers. if used chips own cal_drv func instead to calculate
111 * registers offset, the variant could be ignored.
112 */
113 struct rockchip_drv {
114 enum rockchip_pin_drv_type drv_type;
115 int offset;
116 };
117
118 /**
119 * @priv: common pinctrl private basedata
120 * @pin_base: first pin number
121 * @nr_pins: number of pins in this bank
122 * @name: name of the bank
123 * @bank_num: number of the bank, to account for holes
124 * @iomux: array describing the 4 iomux sources of the bank
125 * @drv: array describing the 4 drive strength sources of the bank
126 * @pull_type: array describing the 4 pull type sources of the bank
127 * @recalced_mask: bits describing the mux recalced pins of per bank
128 * @route_mask: bits describing the routing pins of per bank
129 */
130 struct rockchip_pin_bank {
131 struct rockchip_pinctrl_priv *priv;
132 u32 pin_base;
133 u8 nr_pins;
134 char *name;
135 u8 bank_num;
136 struct rockchip_iomux iomux[4];
137 struct rockchip_drv drv[4];
138 enum rockchip_pin_pull_type pull_type[4];
139 u32 recalced_mask;
140 u32 route_mask;
141 };
142
143 #define PIN_BANK(id, pins, label) \
144 { \
145 .bank_num = id, \
146 .nr_pins = pins, \
147 .name = label, \
148 .iomux = { \
149 { .offset = -1 }, \
150 { .offset = -1 }, \
151 { .offset = -1 }, \
152 { .offset = -1 }, \
153 }, \
154 }
155
156 #define PIN_BANK_IOMUX_FLAGS(id, pins, label, iom0, iom1, iom2, iom3) \
157 { \
158 .bank_num = id, \
159 .nr_pins = pins, \
160 .name = label, \
161 .iomux = { \
162 { .type = iom0, .offset = -1 }, \
163 { .type = iom1, .offset = -1 }, \
164 { .type = iom2, .offset = -1 }, \
165 { .type = iom3, .offset = -1 }, \
166 }, \
167 }
168
169 #define PIN_BANK_IOMUX_FLAGS_OFFSET(id, pins, label, iom0, iom1, iom2, \
170 iom3, offset0, offset1, offset2, \
171 offset3) \
172 { \
173 .bank_num = id, \
174 .nr_pins = pins, \
175 .name = label, \
176 .iomux = { \
177 { .type = iom0, .offset = offset0 }, \
178 { .type = iom1, .offset = offset1 }, \
179 { .type = iom2, .offset = offset2 }, \
180 { .type = iom3, .offset = offset3 }, \
181 }, \
182 }
183
184 #define PIN_BANK_DRV_FLAGS(id, pins, label, type0, type1, type2, type3) \
185 { \
186 .bank_num = id, \
187 .nr_pins = pins, \
188 .name = label, \
189 .iomux = { \
190 { .offset = -1 }, \
191 { .offset = -1 }, \
192 { .offset = -1 }, \
193 { .offset = -1 }, \
194 }, \
195 .drv = { \
196 { .drv_type = type0, .offset = -1 }, \
197 { .drv_type = type1, .offset = -1 }, \
198 { .drv_type = type2, .offset = -1 }, \
199 { .drv_type = type3, .offset = -1 }, \
200 }, \
201 }
202
203 #define PIN_BANK_DRV_FLAGS_PULL_FLAGS(id, pins, label, drv0, drv1, \
204 drv2, drv3, pull0, pull1, \
205 pull2, pull3) \
206 { \
207 .bank_num = id, \
208 .nr_pins = pins, \
209 .name = label, \
210 .iomux = { \
211 { .offset = -1 }, \
212 { .offset = -1 }, \
213 { .offset = -1 }, \
214 { .offset = -1 }, \
215 }, \
216 .drv = { \
217 { .drv_type = drv0, .offset = -1 }, \
218 { .drv_type = drv1, .offset = -1 }, \
219 { .drv_type = drv2, .offset = -1 }, \
220 { .drv_type = drv3, .offset = -1 }, \
221 }, \
222 .pull_type[0] = pull0, \
223 .pull_type[1] = pull1, \
224 .pull_type[2] = pull2, \
225 .pull_type[3] = pull3, \
226 }
227
228 #define PIN_BANK_IOMUX_DRV_FLAGS_OFFSET(id, pins, label, iom0, iom1, \
229 iom2, iom3, drv0, drv1, drv2, \
230 drv3, offset0, offset1, \
231 offset2, offset3) \
232 { \
233 .bank_num = id, \
234 .nr_pins = pins, \
235 .name = label, \
236 .iomux = { \
237 { .type = iom0, .offset = -1 }, \
238 { .type = iom1, .offset = -1 }, \
239 { .type = iom2, .offset = -1 }, \
240 { .type = iom3, .offset = -1 }, \
241 }, \
242 .drv = { \
243 { .drv_type = drv0, .offset = offset0 }, \
244 { .drv_type = drv1, .offset = offset1 }, \
245 { .drv_type = drv2, .offset = offset2 }, \
246 { .drv_type = drv3, .offset = offset3 }, \
247 }, \
248 }
249
250 #define PIN_BANK_IOMUX_DRV_PULL_FLAGS(id, pins, label, iom0, iom1, \
251 iom2, iom3, drv0, drv1, drv2, \
252 drv3, pull0, pull1, pull2, \
253 pull3) \
254 { \
255 .bank_num = id, \
256 .nr_pins = pins, \
257 .name = label, \
258 .iomux = { \
259 { .type = iom0, .offset = -1 }, \
260 { .type = iom1, .offset = -1 }, \
261 { .type = iom2, .offset = -1 }, \
262 { .type = iom3, .offset = -1 }, \
263 }, \
264 .drv = { \
265 { .drv_type = drv0, .offset = -1 }, \
266 { .drv_type = drv1, .offset = -1 }, \
267 { .drv_type = drv2, .offset = -1 }, \
268 { .drv_type = drv3, .offset = -1 }, \
269 }, \
270 .pull_type[0] = pull0, \
271 .pull_type[1] = pull1, \
272 .pull_type[2] = pull2, \
273 .pull_type[3] = pull3, \
274 }
275
276 #define PIN_BANK_IOMUX_FLAGS_DRV_FLAGS_OFFSET_PULL_FLAGS(id, pins, \
277 label, iom0, iom1, iom2, \
278 iom3, drv0, drv1, drv2, \
279 drv3, offset0, offset1, \
280 offset2, offset3, pull0, \
281 pull1, pull2, pull3) \
282 { \
283 .bank_num = id, \
284 .nr_pins = pins, \
285 .name = label, \
286 .iomux = { \
287 { .type = iom0, .offset = -1 }, \
288 { .type = iom1, .offset = -1 }, \
289 { .type = iom2, .offset = -1 }, \
290 { .type = iom3, .offset = -1 }, \
291 }, \
292 .drv = { \
293 { .drv_type = drv0, .offset = offset0 }, \
294 { .drv_type = drv1, .offset = offset1 }, \
295 { .drv_type = drv2, .offset = offset2 }, \
296 { .drv_type = drv3, .offset = offset3 }, \
297 }, \
298 .pull_type[0] = pull0, \
299 .pull_type[1] = pull1, \
300 .pull_type[2] = pull2, \
301 .pull_type[3] = pull3, \
302 }
303
304 #define PIN_BANK_MUX_ROUTE_FLAGS(ID, PIN, FUNC, REG, VAL, FLAG) \
305 { \
306 .bank_num = ID, \
307 .pin = PIN, \
308 .func = FUNC, \
309 .route_offset = REG, \
310 .route_val = VAL, \
311 .route_type = FLAG, \
312 }
313
314 #define MR_DEFAULT(ID, PIN, FUNC, REG, VAL) \
315 PIN_BANK_MUX_ROUTE_FLAGS(ID, PIN, FUNC, REG, VAL, ROUTE_TYPE_DEFAULT)
316
317 #define MR_TOPGRF(ID, PIN, FUNC, REG, VAL) \
318 PIN_BANK_MUX_ROUTE_FLAGS(ID, PIN, FUNC, REG, VAL, ROUTE_TYPE_TOPGRF)
319
320 #define MR_PMUGRF(ID, PIN, FUNC, REG, VAL) \
321 PIN_BANK_MUX_ROUTE_FLAGS(ID, PIN, FUNC, REG, VAL, ROUTE_TYPE_PMUGRF)
322
323 /**
324 * struct rockchip_mux_recalced_data: represent a pin iomux data.
325 * @num: bank number.
326 * @pin: pin number.
327 * @bit: index at register.
328 * @reg: register offset.
329 * @mask: mask bit
330 */
331 struct rockchip_mux_recalced_data {
332 u8 num;
333 u8 pin;
334 u32 reg;
335 u8 bit;
336 u8 mask;
337 };
338
339 /**
340 * struct rockchip_mux_recalced_data: represent a pin iomux data.
341 * @bank_num: bank number.
342 * @pin: index at register or used to calc index.
343 * @func: the min pin.
344 * @route_type: the register type.
345 * @route_offset: the max pin.
346 * @route_val: the register offset.
347 */
348 struct rockchip_mux_route_data {
349 u8 bank_num;
350 u8 pin;
351 u8 func;
352 enum rockchip_pin_route_type route_type : 8;
353 u32 route_offset;
354 u32 route_val;
355 };
356
357 /**
358 */
359 struct rockchip_pin_ctrl {
360 struct rockchip_pin_bank *pin_banks;
361 u32 nr_banks;
362 u32 nr_pins;
363 char *label;
364 enum rockchip_pinctrl_type type;
365 int grf_mux_offset;
366 int pmu_mux_offset;
367 int grf_drv_offset;
368 int pmu_drv_offset;
369 struct rockchip_mux_recalced_data *iomux_recalced;
370 u32 niomux_recalced;
371 struct rockchip_mux_route_data *iomux_routes;
372 u32 niomux_routes;
373
374 int (*ctrl_data_re_init)(const struct rockchip_pin_ctrl *ctrl);
375
376 int (*soc_data_init)(struct rockchip_pinctrl_priv *info);
377
378 void (*pull_calc_reg)(struct rockchip_pin_bank *bank,
379 int pin_num, struct regmap **regmap,
380 int *reg, u8 *bit);
381 void (*drv_calc_reg)(struct rockchip_pin_bank *bank,
382 int pin_num, struct regmap **regmap,
383 int *reg, u8 *bit);
384 int (*schmitt_calc_reg)(struct rockchip_pin_bank *bank,
385 int pin_num, struct regmap **regmap,
386 int *reg, u8 *bit);
387 int (*slew_rate_calc_reg)(struct rockchip_pin_bank *bank,
388 int pin_num, struct regmap **regmap,
389 int *reg, u8 *bit);
390 };
391
392 /**
393 */
394 struct rockchip_pinctrl_priv {
395 struct rockchip_pin_ctrl *ctrl;
396 struct regmap *regmap_base;
397 struct regmap *regmap_pmu;
398
399 };
400
rockchip_verify_config(struct udevice * dev,u32 bank,u32 pin)401 static int rockchip_verify_config(struct udevice *dev, u32 bank, u32 pin)
402 {
403 struct rockchip_pinctrl_priv *priv = dev_get_priv(dev);
404 struct rockchip_pin_ctrl *ctrl = priv->ctrl;
405
406 if (bank >= ctrl->nr_banks) {
407 debug("pin conf bank %d >= nbanks %d\n", bank, ctrl->nr_banks);
408 return -EINVAL;
409 }
410
411 if (pin >= MAX_ROCKCHIP_GPIO_PER_BANK) {
412 debug("pin conf pin %d >= %d\n", pin,
413 MAX_ROCKCHIP_GPIO_PER_BANK);
414 return -EINVAL;
415 }
416
417 return 0;
418 }
419
420 static struct rockchip_mux_recalced_data rv1108_mux_recalced_data[] = {
421 {
422 .num = 1,
423 .pin = 0,
424 .reg = 0x418,
425 .bit = 0,
426 .mask = 0x3
427 }, {
428 .num = 1,
429 .pin = 1,
430 .reg = 0x418,
431 .bit = 2,
432 .mask = 0x3
433 }, {
434 .num = 1,
435 .pin = 2,
436 .reg = 0x418,
437 .bit = 4,
438 .mask = 0x3
439 }, {
440 .num = 1,
441 .pin = 3,
442 .reg = 0x418,
443 .bit = 6,
444 .mask = 0x3
445 }, {
446 .num = 1,
447 .pin = 4,
448 .reg = 0x418,
449 .bit = 8,
450 .mask = 0x3
451 }, {
452 .num = 1,
453 .pin = 5,
454 .reg = 0x418,
455 .bit = 10,
456 .mask = 0x3
457 }, {
458 .num = 1,
459 .pin = 6,
460 .reg = 0x418,
461 .bit = 12,
462 .mask = 0x3
463 }, {
464 .num = 1,
465 .pin = 7,
466 .reg = 0x418,
467 .bit = 14,
468 .mask = 0x3
469 }, {
470 .num = 1,
471 .pin = 8,
472 .reg = 0x41c,
473 .bit = 0,
474 .mask = 0x3
475 }, {
476 .num = 1,
477 .pin = 9,
478 .reg = 0x41c,
479 .bit = 2,
480 .mask = 0x3
481 },
482 };
483
484 static struct rockchip_mux_recalced_data rv1126_mux_recalced_data[] = {
485 {
486 .num = 0,
487 .pin = 20,
488 .reg = 0x10000,
489 .bit = 0,
490 .mask = 0xf
491 },
492 {
493 .num = 0,
494 .pin = 21,
495 .reg = 0x10000,
496 .bit = 4,
497 .mask = 0xf
498 },
499 {
500 .num = 0,
501 .pin = 22,
502 .reg = 0x10000,
503 .bit = 8,
504 .mask = 0xf
505 },
506 {
507 .num = 0,
508 .pin = 23,
509 .reg = 0x10000,
510 .bit = 12,
511 .mask = 0xf
512 },
513 };
514
515 static struct rockchip_mux_recalced_data rk3128_mux_recalced_data[] = {
516 {
517 .num = 2,
518 .pin = 20,
519 .reg = 0xe8,
520 .bit = 0,
521 .mask = 0x7
522 }, {
523 .num = 2,
524 .pin = 21,
525 .reg = 0xe8,
526 .bit = 4,
527 .mask = 0x7
528 }, {
529 .num = 2,
530 .pin = 22,
531 .reg = 0xe8,
532 .bit = 8,
533 .mask = 0x7
534 }, {
535 .num = 2,
536 .pin = 23,
537 .reg = 0xe8,
538 .bit = 12,
539 .mask = 0x7
540 }, {
541 .num = 2,
542 .pin = 24,
543 .reg = 0xd4,
544 .bit = 12,
545 .mask = 0x7
546 },
547 };
548
549 static struct rockchip_mux_recalced_data rk3308_mux_recalced_data[] = {
550 {
551 .num = 1,
552 .pin = 14,
553 .reg = 0x28,
554 .bit = 12,
555 .mask = 0x7
556 }, {
557 .num = 1,
558 .pin = 15,
559 .reg = 0x2c,
560 .bit = 0,
561 .mask = 0x3
562 }, {
563 .num = 1,
564 .pin = 18,
565 .reg = 0x30,
566 .bit = 4,
567 .mask = 0x7
568 }, {
569 .num = 1,
570 .pin = 19,
571 .reg = 0x30,
572 .bit = 8,
573 .mask = 0x7
574 }, {
575 .num = 1,
576 .pin = 20,
577 .reg = 0x30,
578 .bit = 12,
579 .mask = 0x7
580 }, {
581 .num = 1,
582 .pin = 21,
583 .reg = 0x34,
584 .bit = 0,
585 .mask = 0x7
586 }, {
587 .num = 1,
588 .pin = 22,
589 .reg = 0x34,
590 .bit = 4,
591 .mask = 0x7
592 }, {
593 .num = 1,
594 .pin = 23,
595 .reg = 0x34,
596 .bit = 8,
597 .mask = 0x7
598 }, {
599 .num = 3,
600 .pin = 12,
601 .reg = 0x68,
602 .bit = 8,
603 .mask = 0x7
604 }, {
605 .num = 3,
606 .pin = 13,
607 .reg = 0x68,
608 .bit = 12,
609 .mask = 0x7
610 },
611 };
612
613 static struct rockchip_mux_recalced_data rk3308b_mux_recalced_data[] = {
614 {
615 .num = 1,
616 .pin = 14,
617 .reg = 0x28,
618 .bit = 12,
619 .mask = 0xf
620 }, {
621 .num = 1,
622 .pin = 15,
623 .reg = 0x2c,
624 .bit = 0,
625 .mask = 0x3
626 }, {
627 .num = 1,
628 .pin = 18,
629 .reg = 0x30,
630 .bit = 4,
631 .mask = 0xf
632 }, {
633 .num = 1,
634 .pin = 19,
635 .reg = 0x30,
636 .bit = 8,
637 .mask = 0xf
638 }, {
639 .num = 1,
640 .pin = 20,
641 .reg = 0x30,
642 .bit = 12,
643 .mask = 0xf
644 }, {
645 .num = 1,
646 .pin = 21,
647 .reg = 0x34,
648 .bit = 0,
649 .mask = 0xf
650 }, {
651 .num = 1,
652 .pin = 22,
653 .reg = 0x34,
654 .bit = 4,
655 .mask = 0xf
656 }, {
657 .num = 1,
658 .pin = 23,
659 .reg = 0x34,
660 .bit = 8,
661 .mask = 0xf
662 }, {
663 .num = 3,
664 .pin = 12,
665 .reg = 0x68,
666 .bit = 8,
667 .mask = 0xf
668 }, {
669 .num = 3,
670 .pin = 13,
671 .reg = 0x68,
672 .bit = 12,
673 .mask = 0xf
674 }, {
675 .num = 2,
676 .pin = 2,
677 .reg = 0x608,
678 .bit = 0,
679 .mask = 0x7
680 }, {
681 .num = 2,
682 .pin = 3,
683 .reg = 0x608,
684 .bit = 4,
685 .mask = 0x7
686 }, {
687 .num = 2,
688 .pin = 16,
689 .reg = 0x610,
690 .bit = 8,
691 .mask = 0x7
692 }, {
693 .num = 3,
694 .pin = 10,
695 .reg = 0x610,
696 .bit = 0,
697 .mask = 0x7
698 }, {
699 .num = 3,
700 .pin = 11,
701 .reg = 0x610,
702 .bit = 4,
703 .mask = 0x7
704 },
705 };
706
707 static struct rockchip_mux_recalced_data rk3328_mux_recalced_data[] = {
708 {
709 .num = 2,
710 .pin = 12,
711 .reg = 0x24,
712 .bit = 8,
713 .mask = 0x3
714 }, {
715 .num = 2,
716 .pin = 15,
717 .reg = 0x28,
718 .bit = 0,
719 .mask = 0x7
720 }, {
721 .num = 2,
722 .pin = 23,
723 .reg = 0x30,
724 .bit = 14,
725 .mask = 0x3
726 },
727 };
728
729 static struct rockchip_mux_route_data rv1126_mux_route_data[] = {
730 MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x10260, RK_GENMASK_VAL(0, 0, 0)), /* I2S0_MCLK_M0 */
731 MR_TOPGRF(RK_GPIO3, RK_PB0, RK_FUNC_3, 0x10260, RK_GENMASK_VAL(0, 0, 1)), /* I2S0_MCLK_M1 */
732
733 MR_TOPGRF(RK_GPIO0, RK_PD4, RK_FUNC_4, 0x10260, RK_GENMASK_VAL(3, 2, 0)), /* I2S1_MCLK_M0 */
734 MR_TOPGRF(RK_GPIO1, RK_PD5, RK_FUNC_2, 0x10260, RK_GENMASK_VAL(3, 2, 1)), /* I2S1_MCLK_M1 */
735 MR_TOPGRF(RK_GPIO2, RK_PC7, RK_FUNC_6, 0x10260, RK_GENMASK_VAL(3, 2, 2)), /* I2S1_MCLK_M2 */
736
737 MR_TOPGRF(RK_GPIO1, RK_PD0, RK_FUNC_1, 0x10260, RK_GENMASK_VAL(4, 4, 0)), /* I2S2_MCLK_M0 */
738 MR_TOPGRF(RK_GPIO2, RK_PB3, RK_FUNC_2, 0x10260, RK_GENMASK_VAL(4, 4, 1)), /* I2S2_MCLK_M1 */
739
740 MR_TOPGRF(RK_GPIO3, RK_PD4, RK_FUNC_2, 0x10260, RK_GENMASK_VAL(12, 12, 0)), /* PDM_CLK0_M0 */
741 MR_TOPGRF(RK_GPIO3, RK_PC0, RK_FUNC_3, 0x10260, RK_GENMASK_VAL(12, 12, 1)), /* PDM_CLK0_M1 */
742
743 MR_TOPGRF(RK_GPIO3, RK_PC6, RK_FUNC_1, 0x10264, RK_GENMASK_VAL(0, 0, 0)), /* CIF_CLKOUT_M0 */
744 MR_TOPGRF(RK_GPIO2, RK_PD1, RK_FUNC_3, 0x10264, RK_GENMASK_VAL(0, 0, 1)), /* CIF_CLKOUT_M1 */
745
746 MR_TOPGRF(RK_GPIO3, RK_PA4, RK_FUNC_5, 0x10264, RK_GENMASK_VAL(5, 4, 0)), /* I2C3_SCL_M0 */
747 MR_TOPGRF(RK_GPIO2, RK_PD4, RK_FUNC_7, 0x10264, RK_GENMASK_VAL(5, 4, 1)), /* I2C3_SCL_M1 */
748 MR_TOPGRF(RK_GPIO1, RK_PD6, RK_FUNC_3, 0x10264, RK_GENMASK_VAL(5, 4, 2)), /* I2C3_SCL_M2 */
749
750 MR_TOPGRF(RK_GPIO3, RK_PA0, RK_FUNC_7, 0x10264, RK_GENMASK_VAL(6, 6, 0)), /* I2C4_SCL_M0 */
751 MR_TOPGRF(RK_GPIO4, RK_PA0, RK_FUNC_4, 0x10264, RK_GENMASK_VAL(6, 6, 1)), /* I2C4_SCL_M1 */
752
753 MR_TOPGRF(RK_GPIO2, RK_PA5, RK_FUNC_7, 0x10264, RK_GENMASK_VAL(9, 8, 0)), /* I2C5_SCL_M0 */
754 MR_TOPGRF(RK_GPIO3, RK_PB0, RK_FUNC_5, 0x10264, RK_GENMASK_VAL(9, 8, 1)), /* I2C5_SCL_M1 */
755 MR_TOPGRF(RK_GPIO1, RK_PD0, RK_FUNC_4, 0x10264, RK_GENMASK_VAL(9, 8, 2)), /* I2C5_SCL_M2 */
756
757 MR_TOPGRF(RK_GPIO3, RK_PC0, RK_FUNC_5, 0x10264, RK_GENMASK_VAL(11, 10, 0)), /* SPI1_CLK_M0 */
758 MR_TOPGRF(RK_GPIO1, RK_PC6, RK_FUNC_3, 0x10264, RK_GENMASK_VAL(11, 10, 1)), /* SPI1_CLK_M1 */
759 MR_TOPGRF(RK_GPIO2, RK_PD5, RK_FUNC_6, 0x10264, RK_GENMASK_VAL(11, 10, 2)), /* SPI1_CLK_M2 */
760
761 MR_TOPGRF(RK_GPIO3, RK_PC0, RK_FUNC_2, 0x10264, RK_GENMASK_VAL(12, 12, 0)), /* RGMII_CLK_M0 */
762 MR_TOPGRF(RK_GPIO2, RK_PB7, RK_FUNC_2, 0x10264, RK_GENMASK_VAL(12, 12, 1)), /* RGMII_CLK_M1 */
763
764 MR_TOPGRF(RK_GPIO3, RK_PA1, RK_FUNC_3, 0x10264, RK_GENMASK_VAL(13, 13, 0)), /* CAN_TXD_M0 */
765 MR_TOPGRF(RK_GPIO3, RK_PA7, RK_FUNC_5, 0x10264, RK_GENMASK_VAL(13, 13, 1)), /* CAN_TXD_M1 */
766
767 MR_TOPGRF(RK_GPIO3, RK_PA4, RK_FUNC_6, 0x10268, RK_GENMASK_VAL(0, 0, 0)), /* PWM8_M0 */
768 MR_TOPGRF(RK_GPIO2, RK_PD7, RK_FUNC_5, 0x10268, RK_GENMASK_VAL(0, 0, 1)), /* PWM8_M1 */
769
770 MR_TOPGRF(RK_GPIO3, RK_PA5, RK_FUNC_6, 0x10268, RK_GENMASK_VAL(2, 2, 0)), /* PWM9_M0 */
771 MR_TOPGRF(RK_GPIO2, RK_PD6, RK_FUNC_5, 0x10268, RK_GENMASK_VAL(2, 2, 1)), /* PWM9_M1 */
772
773 MR_TOPGRF(RK_GPIO3, RK_PA6, RK_FUNC_6, 0x10268, RK_GENMASK_VAL(4, 4, 0)), /* PWM10_M0 */
774 MR_TOPGRF(RK_GPIO2, RK_PD5, RK_FUNC_5, 0x10268, RK_GENMASK_VAL(4, 4, 1)), /* PWM10_M1 */
775
776 MR_TOPGRF(RK_GPIO3, RK_PA7, RK_FUNC_6, 0x10268, RK_GENMASK_VAL(6, 6, 0)), /* PWM11_IR_M0 */
777 MR_TOPGRF(RK_GPIO3, RK_PA1, RK_FUNC_5, 0x10268, RK_GENMASK_VAL(6, 6, 1)), /* PWM11_IR_M1 */
778
779 MR_TOPGRF(RK_GPIO1, RK_PA5, RK_FUNC_3, 0x10268, RK_GENMASK_VAL(8, 8, 0)), /* UART2_TX_M0 */
780 MR_TOPGRF(RK_GPIO3, RK_PA2, RK_FUNC_1, 0x10268, RK_GENMASK_VAL(8, 8, 1)), /* UART2_TX_M1 */
781
782 MR_TOPGRF(RK_GPIO3, RK_PC6, RK_FUNC_3, 0x10268, RK_GENMASK_VAL(11, 10, 0)), /* UART3_TX_M0 */
783 MR_TOPGRF(RK_GPIO1, RK_PA7, RK_FUNC_2, 0x10268, RK_GENMASK_VAL(11, 10, 1)), /* UART3_TX_M1 */
784 MR_TOPGRF(RK_GPIO3, RK_PA0, RK_FUNC_4, 0x10268, RK_GENMASK_VAL(11, 10, 2)), /* UART3_TX_M2 */
785
786 MR_TOPGRF(RK_GPIO3, RK_PA4, RK_FUNC_4, 0x10268, RK_GENMASK_VAL(13, 12, 0)), /* UART4_TX_M0 */
787 MR_TOPGRF(RK_GPIO2, RK_PA6, RK_FUNC_4, 0x10268, RK_GENMASK_VAL(13, 12, 1)), /* UART4_TX_M1 */
788 MR_TOPGRF(RK_GPIO1, RK_PD5, RK_FUNC_3, 0x10268, RK_GENMASK_VAL(13, 12, 2)), /* UART4_TX_M2 */
789
790 MR_TOPGRF(RK_GPIO3, RK_PA6, RK_FUNC_4, 0x10268, RK_GENMASK_VAL(15, 14, 0)), /* UART5_TX_M0 */
791 MR_TOPGRF(RK_GPIO2, RK_PB0, RK_FUNC_4, 0x10268, RK_GENMASK_VAL(15, 14, 1)), /* UART5_TX_M1 */
792 MR_TOPGRF(RK_GPIO2, RK_PA0, RK_FUNC_3, 0x10268, RK_GENMASK_VAL(15, 14, 2)), /* UART5_TX_M2 */
793
794 MR_PMUGRF(RK_GPIO0, RK_PB6, RK_FUNC_3, 0x0114, RK_GENMASK_VAL(0, 0, 0)), /* PWM0_M0 */
795 MR_PMUGRF(RK_GPIO2, RK_PB3, RK_FUNC_5, 0x0114, RK_GENMASK_VAL(0, 0, 1)), /* PWM0_M1 */
796
797 MR_PMUGRF(RK_GPIO0, RK_PB7, RK_FUNC_3, 0x0114, RK_GENMASK_VAL(2, 2, 0)), /* PWM1_M0 */
798 MR_PMUGRF(RK_GPIO2, RK_PB2, RK_FUNC_5, 0x0114, RK_GENMASK_VAL(2, 2, 1)), /* PWM1_M1 */
799
800 MR_PMUGRF(RK_GPIO0, RK_PC0, RK_FUNC_3, 0x0114, RK_GENMASK_VAL(4, 4, 0)), /* PWM2_M0 */
801 MR_PMUGRF(RK_GPIO2, RK_PB1, RK_FUNC_5, 0x0114, RK_GENMASK_VAL(4, 4, 1)), /* PWM2_M1 */
802
803 MR_PMUGRF(RK_GPIO0, RK_PC1, RK_FUNC_3, 0x0114, RK_GENMASK_VAL(6, 6, 0)), /* PWM3_IR_M0 */
804 MR_PMUGRF(RK_GPIO2, RK_PB0, RK_FUNC_5, 0x0114, RK_GENMASK_VAL(6, 6, 1)), /* PWM3_IR_M1 */
805
806 MR_PMUGRF(RK_GPIO0, RK_PC2, RK_FUNC_3, 0x0114, RK_GENMASK_VAL(8, 8, 0)), /* PWM4_M0 */
807 MR_PMUGRF(RK_GPIO2, RK_PA7, RK_FUNC_5, 0x0114, RK_GENMASK_VAL(8, 8, 1)), /* PWM4_M1 */
808
809 MR_PMUGRF(RK_GPIO0, RK_PC3, RK_FUNC_3, 0x0114, RK_GENMASK_VAL(10, 10, 0)), /* PWM5_M0 */
810 MR_PMUGRF(RK_GPIO2, RK_PA6, RK_FUNC_5, 0x0114, RK_GENMASK_VAL(10, 10, 1)), /* PWM5_M1 */
811
812 MR_PMUGRF(RK_GPIO0, RK_PB2, RK_FUNC_3, 0x0114, RK_GENMASK_VAL(12, 12, 0)), /* PWM6_M0 */
813 MR_PMUGRF(RK_GPIO2, RK_PD4, RK_FUNC_5, 0x0114, RK_GENMASK_VAL(12, 12, 1)), /* PWM6_M1 */
814
815 MR_PMUGRF(RK_GPIO0, RK_PB1, RK_FUNC_3, 0x0114, RK_GENMASK_VAL(14, 14, 0)), /* PWM7_IR_M0 */
816 MR_PMUGRF(RK_GPIO3, RK_PA0, RK_FUNC_5, 0x0114, RK_GENMASK_VAL(14, 14, 1)), /* PWM7_IR_M1 */
817
818 MR_PMUGRF(RK_GPIO0, RK_PB0, RK_FUNC_1, 0x0118, RK_GENMASK_VAL(1, 0, 0)), /* SPI0_CLK_M0 */
819 MR_PMUGRF(RK_GPIO2, RK_PA1, RK_FUNC_1, 0x0118, RK_GENMASK_VAL(1, 0, 1)), /* SPI0_CLK_M1 */
820 MR_PMUGRF(RK_GPIO2, RK_PB2, RK_FUNC_6, 0x0118, RK_GENMASK_VAL(1, 0, 2)), /* SPI0_CLK_M2 */
821
822 MR_PMUGRF(RK_GPIO0, RK_PB6, RK_FUNC_2, 0x0118, RK_GENMASK_VAL(2, 2, 0)), /* UART1_TX_M0 */
823 MR_PMUGRF(RK_GPIO1, RK_PD0, RK_FUNC_5, 0x0118, RK_GENMASK_VAL(2, 2, 1)), /* UART1_TX_M1 */
824 MR_PMUGRF(RK_GPIO0, RK_PC3, RK_FUNC_1, 0x0118, RK_GENMASK_VAL(4, 4, 1)), /* I2C2 */
825 };
826
rockchip_get_recalced_mux(struct rockchip_pin_bank * bank,int pin,int * reg,u8 * bit,int * mask)827 static void rockchip_get_recalced_mux(struct rockchip_pin_bank *bank, int pin,
828 int *reg, u8 *bit, int *mask)
829 {
830 struct rockchip_pinctrl_priv *priv = bank->priv;
831 struct rockchip_pin_ctrl *ctrl = priv->ctrl;
832 struct rockchip_mux_recalced_data *data;
833 int i;
834
835 for (i = 0; i < ctrl->niomux_recalced; i++) {
836 data = &ctrl->iomux_recalced[i];
837 if (data->num == bank->bank_num &&
838 data->pin == pin)
839 break;
840 }
841
842 if (i >= ctrl->niomux_recalced)
843 return;
844
845 *reg = data->reg;
846 *mask = data->mask;
847 *bit = data->bit;
848 }
849
850 static struct rockchip_mux_route_data px30_mux_route_data[] = {
851 {
852 /* cif-d2m0 */
853 .bank_num = 2,
854 .pin = 0,
855 .func = 1,
856 .route_offset = 0x184,
857 .route_val = BIT(16 + 7),
858 }, {
859 /* cif-d2m1 */
860 .bank_num = 3,
861 .pin = 3,
862 .func = 3,
863 .route_offset = 0x184,
864 .route_val = BIT(16 + 7) | BIT(7),
865 }, {
866 /* pdm-m0 */
867 .bank_num = 3,
868 .pin = 22,
869 .func = 2,
870 .route_offset = 0x184,
871 .route_val = BIT(16 + 8),
872 }, {
873 /* pdm-m1 */
874 .bank_num = 2,
875 .pin = 22,
876 .func = 1,
877 .route_offset = 0x184,
878 .route_val = BIT(16 + 8) | BIT(8),
879 }, {
880 /* uart2-rxm0 */
881 .bank_num = 1,
882 .pin = 27,
883 .func = 2,
884 .route_offset = 0x184,
885 .route_val = BIT(16 + 10),
886 }, {
887 /* uart2-rxm1 */
888 .bank_num = 2,
889 .pin = 14,
890 .func = 2,
891 .route_offset = 0x184,
892 .route_val = BIT(16 + 10) | BIT(10),
893 }, {
894 /* uart3-rxm0 */
895 .bank_num = 0,
896 .pin = 17,
897 .func = 2,
898 .route_offset = 0x184,
899 .route_val = BIT(16 + 9),
900 }, {
901 /* uart3-rxm1 */
902 .bank_num = 1,
903 .pin = 15,
904 .func = 2,
905 .route_offset = 0x184,
906 .route_val = BIT(16 + 9) | BIT(9),
907 },
908 };
909
910 static struct rockchip_mux_route_data rk1808_mux_route_data[] = {
911 {
912 /* i2c2m0_sda */
913 .bank_num = 3,
914 .pin = 12,
915 .func = 2,
916 .route_offset = 0x190,
917 .route_val = BIT(16 + 3),
918 }, {
919 /* i2c2m1_sda */
920 .bank_num = 1,
921 .pin = 13,
922 .func = 2,
923 .route_offset = 0x190,
924 .route_val = BIT(16 + 3) | BIT(3),
925 }, {
926 /* uart2_rxm0 */
927 .bank_num = 4,
928 .pin = 3,
929 .func = 2,
930 .route_offset = 0x190,
931 .route_val = BIT(16 + 14) | BIT(16 + 15),
932 }, {
933 /* uart2_rxm1 */
934 .bank_num = 2,
935 .pin = 25,
936 .func = 2,
937 .route_offset = 0x190,
938 .route_val = BIT(16 + 14) | BIT(14) | BIT(16 + 15),
939 }, {
940 /* uart2_rxm2 */
941 .bank_num = 3,
942 .pin = 4,
943 .func = 2,
944 .route_offset = 0x190,
945 .route_val = BIT(16 + 14) | BIT(16 + 15) | BIT(15),
946 },
947 };
948
949 static struct rockchip_mux_route_data rk3128_mux_route_data[] = {
950 {
951 /* spi-0 */
952 .bank_num = 1,
953 .pin = 10,
954 .func = 1,
955 .route_offset = 0x144,
956 .route_val = BIT(16 + 3) | BIT(16 + 4),
957 }, {
958 /* spi-1 */
959 .bank_num = 1,
960 .pin = 27,
961 .func = 3,
962 .route_offset = 0x144,
963 .route_val = BIT(16 + 3) | BIT(16 + 4) | BIT(3),
964 }, {
965 /* spi-2 */
966 .bank_num = 0,
967 .pin = 13,
968 .func = 2,
969 .route_offset = 0x144,
970 .route_val = BIT(16 + 3) | BIT(16 + 4) | BIT(4),
971 }, {
972 /* i2s-0 */
973 .bank_num = 1,
974 .pin = 5,
975 .func = 1,
976 .route_offset = 0x144,
977 .route_val = BIT(16 + 5),
978 }, {
979 /* i2s-1 */
980 .bank_num = 0,
981 .pin = 14,
982 .func = 1,
983 .route_offset = 0x144,
984 .route_val = BIT(16 + 5) | BIT(5),
985 }, {
986 /* emmc-0 */
987 .bank_num = 1,
988 .pin = 22,
989 .func = 2,
990 .route_offset = 0x144,
991 .route_val = BIT(16 + 6),
992 }, {
993 /* emmc-1 */
994 .bank_num = 2,
995 .pin = 4,
996 .func = 2,
997 .route_offset = 0x144,
998 .route_val = BIT(16 + 6) | BIT(6),
999 },
1000 };
1001
1002 static struct rockchip_mux_route_data rk3228_mux_route_data[] = {
1003 {
1004 /* pwm0-0 */
1005 .bank_num = 0,
1006 .pin = 26,
1007 .func = 1,
1008 .route_offset = 0x50,
1009 .route_val = BIT(16),
1010 }, {
1011 /* pwm0-1 */
1012 .bank_num = 3,
1013 .pin = 21,
1014 .func = 1,
1015 .route_offset = 0x50,
1016 .route_val = BIT(16) | BIT(0),
1017 }, {
1018 /* pwm1-0 */
1019 .bank_num = 0,
1020 .pin = 27,
1021 .func = 1,
1022 .route_offset = 0x50,
1023 .route_val = BIT(16 + 1),
1024 }, {
1025 /* pwm1-1 */
1026 .bank_num = 0,
1027 .pin = 30,
1028 .func = 2,
1029 .route_offset = 0x50,
1030 .route_val = BIT(16 + 1) | BIT(1),
1031 }, {
1032 /* pwm2-0 */
1033 .bank_num = 0,
1034 .pin = 28,
1035 .func = 1,
1036 .route_offset = 0x50,
1037 .route_val = BIT(16 + 2),
1038 }, {
1039 /* pwm2-1 */
1040 .bank_num = 1,
1041 .pin = 12,
1042 .func = 2,
1043 .route_offset = 0x50,
1044 .route_val = BIT(16 + 2) | BIT(2),
1045 }, {
1046 /* pwm3-0 */
1047 .bank_num = 3,
1048 .pin = 26,
1049 .func = 1,
1050 .route_offset = 0x50,
1051 .route_val = BIT(16 + 3),
1052 }, {
1053 /* pwm3-1 */
1054 .bank_num = 1,
1055 .pin = 11,
1056 .func = 2,
1057 .route_offset = 0x50,
1058 .route_val = BIT(16 + 3) | BIT(3),
1059 }, {
1060 /* sdio-0_d0 */
1061 .bank_num = 1,
1062 .pin = 1,
1063 .func = 1,
1064 .route_offset = 0x50,
1065 .route_val = BIT(16 + 4),
1066 }, {
1067 /* sdio-1_d0 */
1068 .bank_num = 3,
1069 .pin = 2,
1070 .func = 1,
1071 .route_offset = 0x50,
1072 .route_val = BIT(16 + 4) | BIT(4),
1073 }, {
1074 /* spi-0_rx */
1075 .bank_num = 0,
1076 .pin = 13,
1077 .func = 2,
1078 .route_offset = 0x50,
1079 .route_val = BIT(16 + 5),
1080 }, {
1081 /* spi-1_rx */
1082 .bank_num = 2,
1083 .pin = 0,
1084 .func = 2,
1085 .route_offset = 0x50,
1086 .route_val = BIT(16 + 5) | BIT(5),
1087 }, {
1088 /* emmc-0_cmd */
1089 .bank_num = 1,
1090 .pin = 22,
1091 .func = 2,
1092 .route_offset = 0x50,
1093 .route_val = BIT(16 + 7),
1094 }, {
1095 /* emmc-1_cmd */
1096 .bank_num = 2,
1097 .pin = 4,
1098 .func = 2,
1099 .route_offset = 0x50,
1100 .route_val = BIT(16 + 7) | BIT(7),
1101 }, {
1102 /* uart2-0_rx */
1103 .bank_num = 1,
1104 .pin = 19,
1105 .func = 2,
1106 .route_offset = 0x50,
1107 .route_val = BIT(16 + 8),
1108 }, {
1109 /* uart2-1_rx */
1110 .bank_num = 1,
1111 .pin = 10,
1112 .func = 2,
1113 .route_offset = 0x50,
1114 .route_val = BIT(16 + 8) | BIT(8),
1115 }, {
1116 /* uart1-0_rx */
1117 .bank_num = 1,
1118 .pin = 10,
1119 .func = 1,
1120 .route_offset = 0x50,
1121 .route_val = BIT(16 + 11),
1122 }, {
1123 /* uart1-1_rx */
1124 .bank_num = 3,
1125 .pin = 13,
1126 .func = 1,
1127 .route_offset = 0x50,
1128 .route_val = BIT(16 + 11) | BIT(11),
1129 },
1130 };
1131
1132 static struct rockchip_mux_route_data rk3288_mux_route_data[] = {
1133 {
1134 /* edphdmi_cecinoutt1 */
1135 .bank_num = 7,
1136 .pin = 16,
1137 .func = 2,
1138 .route_offset = 0x264,
1139 .route_val = BIT(16 + 12) | BIT(12),
1140 }, {
1141 /* edphdmi_cecinout */
1142 .bank_num = 7,
1143 .pin = 23,
1144 .func = 4,
1145 .route_offset = 0x264,
1146 .route_val = BIT(16 + 12),
1147 },
1148 };
1149
1150 static struct rockchip_mux_route_data rk3308_mux_route_data[] = {
1151 {
1152 /* rtc_clk */
1153 .bank_num = 0,
1154 .pin = 19,
1155 .func = 1,
1156 .route_offset = 0x314,
1157 .route_val = BIT(16 + 0) | BIT(0),
1158 }, {
1159 /* uart2_rxm0 */
1160 .bank_num = 1,
1161 .pin = 22,
1162 .func = 2,
1163 .route_offset = 0x314,
1164 .route_val = BIT(16 + 2) | BIT(16 + 3),
1165 }, {
1166 /* uart2_rxm1 */
1167 .bank_num = 4,
1168 .pin = 26,
1169 .func = 2,
1170 .route_offset = 0x314,
1171 .route_val = BIT(16 + 2) | BIT(16 + 3) | BIT(2),
1172 }, {
1173 /* i2c3_sdam0 */
1174 .bank_num = 0,
1175 .pin = 23,
1176 .func = 2,
1177 .route_offset = 0x314,
1178 .route_val = BIT(16 + 4),
1179 }, {
1180 /* i2c3_sdam1 */
1181 .bank_num = 3,
1182 .pin = 12,
1183 .func = 2,
1184 .route_offset = 0x314,
1185 .route_val = BIT(16 + 4) | BIT(4),
1186 }, {
1187 /* i2s-8ch-1-sclktxm0 */
1188 .bank_num = 1,
1189 .pin = 3,
1190 .func = 2,
1191 .route_offset = 0x308,
1192 .route_val = BIT(16 + 3),
1193 }, {
1194 /* i2s-8ch-1-sclkrxm0 */
1195 .bank_num = 1,
1196 .pin = 4,
1197 .func = 2,
1198 .route_offset = 0x308,
1199 .route_val = BIT(16 + 3),
1200 }, {
1201 /* i2s-8ch-1-sclktxm1 */
1202 .bank_num = 1,
1203 .pin = 13,
1204 .func = 2,
1205 .route_offset = 0x308,
1206 .route_val = BIT(16 + 3) | BIT(3),
1207 }, {
1208 /* i2s-8ch-1-sclkrxm1 */
1209 .bank_num = 1,
1210 .pin = 14,
1211 .func = 2,
1212 .route_offset = 0x308,
1213 .route_val = BIT(16 + 3) | BIT(3),
1214 }, {
1215 /* pdm-clkm0 */
1216 .bank_num = 1,
1217 .pin = 4,
1218 .func = 3,
1219 .route_offset = 0x308,
1220 .route_val = BIT(16 + 12) | BIT(16 + 13),
1221 }, {
1222 /* pdm-clkm1 */
1223 .bank_num = 1,
1224 .pin = 14,
1225 .func = 4,
1226 .route_offset = 0x308,
1227 .route_val = BIT(16 + 12) | BIT(16 + 13) | BIT(12),
1228 }, {
1229 /* pdm-clkm2 */
1230 .bank_num = 2,
1231 .pin = 6,
1232 .func = 2,
1233 .route_offset = 0x308,
1234 .route_val = BIT(16 + 12) | BIT(16 + 13) | BIT(13),
1235 }, {
1236 /* pdm-clkm-m2 */
1237 .bank_num = 2,
1238 .pin = 4,
1239 .func = 3,
1240 .route_offset = 0x600,
1241 .route_val = BIT(16 + 2) | BIT(2),
1242 },
1243 };
1244
1245 static struct rockchip_mux_route_data rk3308b_mux_route_data[] = {
1246 {
1247 /* rtc_clk */
1248 .bank_num = 0,
1249 .pin = 19,
1250 .func = 1,
1251 .route_offset = 0x314,
1252 .route_val = BIT(16 + 0) | BIT(0),
1253 }, {
1254 /* uart2_rxm0 */
1255 .bank_num = 1,
1256 .pin = 22,
1257 .func = 2,
1258 .route_offset = 0x314,
1259 .route_val = BIT(16 + 2) | BIT(16 + 3),
1260 }, {
1261 /* uart2_rxm1 */
1262 .bank_num = 4,
1263 .pin = 26,
1264 .func = 2,
1265 .route_offset = 0x314,
1266 .route_val = BIT(16 + 2) | BIT(16 + 3) | BIT(2),
1267 }, {
1268 /* i2c3_sdam0 */
1269 .bank_num = 0,
1270 .pin = 15,
1271 .func = 2,
1272 .route_offset = 0x608,
1273 .route_val = BIT(16 + 8) | BIT(16 + 9),
1274 }, {
1275 /* i2c3_sdam1 */
1276 .bank_num = 3,
1277 .pin = 12,
1278 .func = 2,
1279 .route_offset = 0x608,
1280 .route_val = BIT(16 + 8) | BIT(16 + 9) | BIT(8),
1281 }, {
1282 /* i2c3_sdam2 */
1283 .bank_num = 2,
1284 .pin = 0,
1285 .func = 3,
1286 .route_offset = 0x608,
1287 .route_val = BIT(16 + 8) | BIT(16 + 9) | BIT(9),
1288 }, {
1289 /* i2s-8ch-1-sclktxm0 */
1290 .bank_num = 1,
1291 .pin = 3,
1292 .func = 2,
1293 .route_offset = 0x308,
1294 .route_val = BIT(16 + 3),
1295 }, {
1296 /* i2s-8ch-1-sclkrxm0 */
1297 .bank_num = 1,
1298 .pin = 4,
1299 .func = 2,
1300 .route_offset = 0x308,
1301 .route_val = BIT(16 + 3),
1302 }, {
1303 /* i2s-8ch-1-sclktxm1 */
1304 .bank_num = 1,
1305 .pin = 13,
1306 .func = 2,
1307 .route_offset = 0x308,
1308 .route_val = BIT(16 + 3) | BIT(3),
1309 }, {
1310 /* i2s-8ch-1-sclkrxm1 */
1311 .bank_num = 1,
1312 .pin = 14,
1313 .func = 2,
1314 .route_offset = 0x308,
1315 .route_val = BIT(16 + 3) | BIT(3),
1316 }, {
1317 /* pdm-clkm0 */
1318 .bank_num = 1,
1319 .pin = 4,
1320 .func = 3,
1321 .route_offset = 0x308,
1322 .route_val = BIT(16 + 12) | BIT(16 + 13),
1323 }, {
1324 /* pdm-clkm1 */
1325 .bank_num = 1,
1326 .pin = 14,
1327 .func = 4,
1328 .route_offset = 0x308,
1329 .route_val = BIT(16 + 12) | BIT(16 + 13) | BIT(12),
1330 }, {
1331 /* pdm-clkm2 */
1332 .bank_num = 2,
1333 .pin = 6,
1334 .func = 2,
1335 .route_offset = 0x308,
1336 .route_val = BIT(16 + 12) | BIT(16 + 13) | BIT(13),
1337 }, {
1338 /* pdm-clkm-m2 */
1339 .bank_num = 2,
1340 .pin = 4,
1341 .func = 3,
1342 .route_offset = 0x600,
1343 .route_val = BIT(16 + 2) | BIT(2),
1344 }, {
1345 /* spi1_miso */
1346 .bank_num = 3,
1347 .pin = 10,
1348 .func = 3,
1349 .route_offset = 0x314,
1350 .route_val = BIT(16 + 9),
1351 }, {
1352 /* spi1_miso_m1 */
1353 .bank_num = 2,
1354 .pin = 4,
1355 .func = 2,
1356 .route_offset = 0x314,
1357 .route_val = BIT(16 + 9) | BIT(9),
1358 }, {
1359 /* owire_m0 */
1360 .bank_num = 0,
1361 .pin = 11,
1362 .func = 3,
1363 .route_offset = 0x314,
1364 .route_val = BIT(16 + 10) | BIT(16 + 11),
1365 }, {
1366 /* owire_m1 */
1367 .bank_num = 1,
1368 .pin = 22,
1369 .func = 7,
1370 .route_offset = 0x314,
1371 .route_val = BIT(16 + 10) | BIT(16 + 11) | BIT(10),
1372 }, {
1373 /* owire_m2 */
1374 .bank_num = 2,
1375 .pin = 2,
1376 .func = 5,
1377 .route_offset = 0x314,
1378 .route_val = BIT(16 + 10) | BIT(16 + 11) | BIT(11),
1379 }, {
1380 /* can_rxd_m0 */
1381 .bank_num = 0,
1382 .pin = 11,
1383 .func = 2,
1384 .route_offset = 0x314,
1385 .route_val = BIT(16 + 12) | BIT(16 + 13),
1386 }, {
1387 /* can_rxd_m1 */
1388 .bank_num = 1,
1389 .pin = 22,
1390 .func = 5,
1391 .route_offset = 0x314,
1392 .route_val = BIT(16 + 12) | BIT(16 + 13) | BIT(12),
1393 }, {
1394 /* can_rxd_m2 */
1395 .bank_num = 2,
1396 .pin = 2,
1397 .func = 4,
1398 .route_offset = 0x314,
1399 .route_val = BIT(16 + 12) | BIT(16 + 13) | BIT(13),
1400 }, {
1401 /* mac_rxd0_m0 */
1402 .bank_num = 1,
1403 .pin = 20,
1404 .func = 3,
1405 .route_offset = 0x314,
1406 .route_val = BIT(16 + 14),
1407 }, {
1408 /* mac_rxd0_m1 */
1409 .bank_num = 4,
1410 .pin = 2,
1411 .func = 2,
1412 .route_offset = 0x314,
1413 .route_val = BIT(16 + 14) | BIT(14),
1414 }, {
1415 /* uart3_rx */
1416 .bank_num = 3,
1417 .pin = 12,
1418 .func = 4,
1419 .route_offset = 0x314,
1420 .route_val = BIT(16 + 15),
1421 }, {
1422 /* uart3_rx_m1 */
1423 .bank_num = 0,
1424 .pin = 17,
1425 .func = 3,
1426 .route_offset = 0x314,
1427 .route_val = BIT(16 + 15) | BIT(15),
1428 },
1429 };
1430
1431 static struct rockchip_mux_route_data rk3328_mux_route_data[] = {
1432 {
1433 /* uart2dbg_rxm0 */
1434 .bank_num = 1,
1435 .pin = 1,
1436 .func = 2,
1437 .route_offset = 0x50,
1438 .route_val = BIT(16) | BIT(16 + 1),
1439 }, {
1440 /* uart2dbg_rxm1 */
1441 .bank_num = 2,
1442 .pin = 1,
1443 .func = 1,
1444 .route_offset = 0x50,
1445 .route_val = BIT(16) | BIT(16 + 1) | BIT(0),
1446 }, {
1447 /* gmac-m1_rxd0 */
1448 .bank_num = 1,
1449 .pin = 11,
1450 .func = 2,
1451 .route_offset = 0x50,
1452 .route_val = BIT(16 + 2) | BIT(2),
1453 }, {
1454 /* gmac-m1-optimized_rxd3 */
1455 .bank_num = 1,
1456 .pin = 14,
1457 .func = 2,
1458 .route_offset = 0x50,
1459 .route_val = BIT(16 + 10) | BIT(10),
1460 }, {
1461 /* pdm_sdi0m0 */
1462 .bank_num = 2,
1463 .pin = 19,
1464 .func = 2,
1465 .route_offset = 0x50,
1466 .route_val = BIT(16 + 3),
1467 }, {
1468 /* pdm_sdi0m1 */
1469 .bank_num = 1,
1470 .pin = 23,
1471 .func = 3,
1472 .route_offset = 0x50,
1473 .route_val = BIT(16 + 3) | BIT(3),
1474 }, {
1475 /* spi_rxdm2 */
1476 .bank_num = 3,
1477 .pin = 2,
1478 .func = 4,
1479 .route_offset = 0x50,
1480 .route_val = BIT(16 + 4) | BIT(16 + 5) | BIT(5),
1481 }, {
1482 /* i2s2_sdim0 */
1483 .bank_num = 1,
1484 .pin = 24,
1485 .func = 1,
1486 .route_offset = 0x50,
1487 .route_val = BIT(16 + 6),
1488 }, {
1489 /* i2s2_sdim1 */
1490 .bank_num = 3,
1491 .pin = 2,
1492 .func = 6,
1493 .route_offset = 0x50,
1494 .route_val = BIT(16 + 6) | BIT(6),
1495 }, {
1496 /* card_iom1 */
1497 .bank_num = 2,
1498 .pin = 22,
1499 .func = 3,
1500 .route_offset = 0x50,
1501 .route_val = BIT(16 + 7) | BIT(7),
1502 }, {
1503 /* tsp_d5m1 */
1504 .bank_num = 2,
1505 .pin = 16,
1506 .func = 3,
1507 .route_offset = 0x50,
1508 .route_val = BIT(16 + 8) | BIT(8),
1509 }, {
1510 /* cif_data5m1 */
1511 .bank_num = 2,
1512 .pin = 16,
1513 .func = 4,
1514 .route_offset = 0x50,
1515 .route_val = BIT(16 + 9) | BIT(9),
1516 },
1517 };
1518
1519 static struct rockchip_mux_route_data rk3399_mux_route_data[] = {
1520 {
1521 /* uart2dbga_rx */
1522 .bank_num = 4,
1523 .pin = 8,
1524 .func = 2,
1525 .route_offset = 0xe21c,
1526 .route_val = BIT(16 + 10) | BIT(16 + 11),
1527 }, {
1528 /* uart2dbgb_rx */
1529 .bank_num = 4,
1530 .pin = 16,
1531 .func = 2,
1532 .route_offset = 0xe21c,
1533 .route_val = BIT(16 + 10) | BIT(16 + 11) | BIT(10),
1534 }, {
1535 /* uart2dbgc_rx */
1536 .bank_num = 4,
1537 .pin = 19,
1538 .func = 1,
1539 .route_offset = 0xe21c,
1540 .route_val = BIT(16 + 10) | BIT(16 + 11) | BIT(11),
1541 }, {
1542 /* pcie_clkreqn */
1543 .bank_num = 2,
1544 .pin = 26,
1545 .func = 2,
1546 .route_offset = 0xe21c,
1547 .route_val = BIT(16 + 14),
1548 }, {
1549 /* pcie_clkreqnb */
1550 .bank_num = 4,
1551 .pin = 24,
1552 .func = 1,
1553 .route_offset = 0xe21c,
1554 .route_val = BIT(16 + 14) | BIT(14),
1555 },
1556 };
1557
1558 static enum rockchip_pin_route_type
rockchip_get_mux_route(struct rockchip_pin_bank * bank,int pin,int mux,u32 * reg,u32 * value)1559 rockchip_get_mux_route(struct rockchip_pin_bank *bank, int pin,
1560 int mux, u32 *reg, u32 *value)
1561 {
1562 struct rockchip_pinctrl_priv *priv = bank->priv;
1563 struct rockchip_pin_ctrl *ctrl = priv->ctrl;
1564 struct rockchip_mux_route_data *data;
1565 int i;
1566
1567 for (i = 0; i < ctrl->niomux_routes; i++) {
1568 data = &ctrl->iomux_routes[i];
1569 if ((data->bank_num == bank->bank_num) &&
1570 (data->pin == pin) && (data->func == mux))
1571 break;
1572 }
1573
1574 if (i >= ctrl->niomux_routes)
1575 return ROUTE_TYPE_INVALID;
1576
1577 *reg = data->route_offset;
1578 *value = data->route_val;
1579
1580 return data->route_type;
1581 }
1582
rockchip_get_mux(struct rockchip_pin_bank * bank,int pin)1583 static int rockchip_get_mux(struct rockchip_pin_bank *bank, int pin)
1584 {
1585 struct rockchip_pinctrl_priv *priv = bank->priv;
1586 int iomux_num = (pin / 8);
1587 struct regmap *regmap;
1588 unsigned int val;
1589 int reg, ret, mask, mux_type;
1590 u8 bit;
1591
1592 if (iomux_num > 3)
1593 return -EINVAL;
1594
1595 if (bank->iomux[iomux_num].type & IOMUX_UNROUTED) {
1596 debug("pin %d is unrouted\n", pin);
1597 return -EINVAL;
1598 }
1599
1600 if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY)
1601 return RK_FUNC_GPIO;
1602
1603 if (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU)
1604 regmap = priv->regmap_pmu;
1605 else if (bank->iomux[iomux_num].type & IOMUX_L_SOURCE_PMU)
1606 regmap = (pin % 8 < 4) ? priv->regmap_pmu : priv->regmap_base;
1607 else
1608 regmap = priv->regmap_base;
1609
1610 /* get basic quadrupel of mux registers and the correct reg inside */
1611 mux_type = bank->iomux[iomux_num].type;
1612 reg = bank->iomux[iomux_num].offset;
1613 if (mux_type & IOMUX_WIDTH_4BIT) {
1614 if ((pin % 8) >= 4)
1615 reg += 0x4;
1616 bit = (pin % 4) * 4;
1617 mask = 0xf;
1618 } else if (mux_type & IOMUX_WIDTH_3BIT) {
1619 if ((pin % 8) >= 5)
1620 reg += 0x4;
1621 bit = (pin % 8 % 5) * 3;
1622 mask = 0x7;
1623 } else {
1624 bit = (pin % 8) * 2;
1625 mask = 0x3;
1626 }
1627
1628 if (bank->recalced_mask & BIT(pin))
1629 rockchip_get_recalced_mux(bank, pin, ®, &bit, &mask);
1630
1631 ret = regmap_read(regmap, reg, &val);
1632 if (ret)
1633 return ret;
1634
1635 return ((val >> bit) & mask);
1636 }
1637
rockchip_pinctrl_get_gpio_mux(struct udevice * dev,int banknum,int index)1638 static int rockchip_pinctrl_get_gpio_mux(struct udevice *dev, int banknum,
1639 int index)
1640 { struct rockchip_pinctrl_priv *priv = dev_get_priv(dev);
1641 struct rockchip_pin_ctrl *ctrl = priv->ctrl;
1642
1643 return rockchip_get_mux(&ctrl->pin_banks[banknum], index);
1644 }
1645
rockchip_verify_mux(struct rockchip_pin_bank * bank,int pin,int mux)1646 static int rockchip_verify_mux(struct rockchip_pin_bank *bank,
1647 int pin, int mux)
1648 {
1649 int iomux_num = (pin / 8);
1650
1651 if (iomux_num > 3)
1652 return -EINVAL;
1653
1654 if (bank->iomux[iomux_num].type & IOMUX_UNROUTED) {
1655 debug("pin %d is unrouted\n", pin);
1656 return -EINVAL;
1657 }
1658
1659 if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY) {
1660 if (mux != IOMUX_GPIO_ONLY) {
1661 debug("pin %d only supports a gpio mux\n", pin);
1662 return -ENOTSUPP;
1663 }
1664 }
1665
1666 return 0;
1667 }
1668
1669 /*
1670 * Set a new mux function for a pin.
1671 *
1672 * The register is divided into the upper and lower 16 bit. When changing
1673 * a value, the previous register value is not read and changed. Instead
1674 * it seems the changed bits are marked in the upper 16 bit, while the
1675 * changed value gets set in the same offset in the lower 16 bit.
1676 * All pin settings seem to be 2 bit wide in both the upper and lower
1677 * parts.
1678 * @bank: pin bank to change
1679 * @pin: pin to change
1680 * @mux: new mux function to set
1681 */
rockchip_set_mux(struct rockchip_pin_bank * bank,int pin,int mux)1682 static int rockchip_set_mux(struct rockchip_pin_bank *bank, int pin, int mux)
1683 {
1684 struct rockchip_pinctrl_priv *priv = bank->priv;
1685 int iomux_num = (pin / 8);
1686 struct regmap *regmap;
1687 int reg, ret, mask, mux_type;
1688 u8 bit;
1689 u32 data;
1690
1691 ret = rockchip_verify_mux(bank, pin, mux);
1692 if (ret < 0)
1693 return ret;
1694
1695 if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY)
1696 return 0;
1697
1698 debug("setting mux of GPIO%d-%d to %d\n", bank->bank_num, pin, mux);
1699
1700 if (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU)
1701 regmap = priv->regmap_pmu;
1702 else if (bank->iomux[iomux_num].type & IOMUX_L_SOURCE_PMU)
1703 regmap = (pin % 8 < 4) ? priv->regmap_pmu : priv->regmap_base;
1704 else
1705 regmap = priv->regmap_base;
1706
1707 /* get basic quadrupel of mux registers and the correct reg inside */
1708 mux_type = bank->iomux[iomux_num].type;
1709 reg = bank->iomux[iomux_num].offset;
1710 if (mux_type & IOMUX_WIDTH_4BIT) {
1711 if ((pin % 8) >= 4)
1712 reg += 0x4;
1713 bit = (pin % 4) * 4;
1714 mask = 0xf;
1715 } else if (mux_type & IOMUX_WIDTH_3BIT) {
1716 if ((pin % 8) >= 5)
1717 reg += 0x4;
1718 bit = (pin % 8 % 5) * 3;
1719 mask = 0x7;
1720 } else {
1721 bit = (pin % 8) * 2;
1722 mask = 0x3;
1723 }
1724
1725 if (bank->recalced_mask & BIT(pin))
1726 rockchip_get_recalced_mux(bank, pin, ®, &bit, &mask);
1727
1728 if (bank->route_mask & BIT(pin)) {
1729 u32 route_reg = 0, route_val = 0;
1730
1731 ret = rockchip_get_mux_route(bank, pin, mux,
1732 &route_reg, &route_val);
1733 switch (ret) {
1734 case ROUTE_TYPE_DEFAULT:
1735 regmap_write(regmap, route_reg, route_val);
1736 break;
1737 case ROUTE_TYPE_TOPGRF:
1738 regmap_write(priv->regmap_base, route_reg, route_val);
1739 break;
1740 case ROUTE_TYPE_PMUGRF:
1741 regmap_write(priv->regmap_pmu, route_reg, route_val);
1742 break;
1743 case ROUTE_TYPE_INVALID: /* Fall through */
1744 default:
1745 break;
1746 }
1747 }
1748
1749 if (mux_type & IOMUX_WRITABLE_32BIT) {
1750 regmap_read(regmap, reg, &data);
1751 data &= ~(mask << bit);
1752 } else {
1753 data = (mask << (bit + 16));
1754 }
1755
1756 data |= (mux & mask) << bit;
1757 ret = regmap_write(regmap, reg, data);
1758
1759 return ret;
1760 }
1761
1762 #define PX30_PULL_PMU_OFFSET 0x10
1763 #define PX30_PULL_GRF_OFFSET 0x60
1764 #define PX30_PULL_BITS_PER_PIN 2
1765 #define PX30_PULL_PINS_PER_REG 8
1766 #define PX30_PULL_BANK_STRIDE 16
1767
px30_calc_pull_reg_and_bit(struct rockchip_pin_bank * bank,int pin_num,struct regmap ** regmap,int * reg,u8 * bit)1768 static void px30_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
1769 int pin_num, struct regmap **regmap,
1770 int *reg, u8 *bit)
1771 {
1772 struct rockchip_pinctrl_priv *priv = bank->priv;
1773
1774 /* The first 32 pins of the first bank are located in PMU */
1775 if (bank->bank_num == 0) {
1776 *regmap = priv->regmap_pmu;
1777 *reg = PX30_PULL_PMU_OFFSET;
1778 } else {
1779 *regmap = priv->regmap_base;
1780 *reg = PX30_PULL_GRF_OFFSET;
1781
1782 /* correct the offset, as we're starting with the 2nd bank */
1783 *reg -= 0x10;
1784 *reg += bank->bank_num * PX30_PULL_BANK_STRIDE;
1785 }
1786
1787 *reg += ((pin_num / PX30_PULL_PINS_PER_REG) * 4);
1788 *bit = (pin_num % PX30_PULL_PINS_PER_REG);
1789 *bit *= PX30_PULL_BITS_PER_PIN;
1790 }
1791
1792 #define PX30_DRV_PMU_OFFSET 0x20
1793 #define PX30_DRV_GRF_OFFSET 0xf0
1794 #define PX30_DRV_BITS_PER_PIN 2
1795 #define PX30_DRV_PINS_PER_REG 8
1796 #define PX30_DRV_BANK_STRIDE 16
1797
px30_calc_drv_reg_and_bit(struct rockchip_pin_bank * bank,int pin_num,struct regmap ** regmap,int * reg,u8 * bit)1798 static void px30_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
1799 int pin_num, struct regmap **regmap,
1800 int *reg, u8 *bit)
1801 {
1802 struct rockchip_pinctrl_priv *priv = bank->priv;
1803
1804 /* The first 32 pins of the first bank are located in PMU */
1805 if (bank->bank_num == 0) {
1806 *regmap = priv->regmap_pmu;
1807 *reg = PX30_DRV_PMU_OFFSET;
1808 } else {
1809 *regmap = priv->regmap_base;
1810 *reg = PX30_DRV_GRF_OFFSET;
1811
1812 /* correct the offset, as we're starting with the 2nd bank */
1813 *reg -= 0x10;
1814 *reg += bank->bank_num * PX30_DRV_BANK_STRIDE;
1815 }
1816
1817 *reg += ((pin_num / PX30_DRV_PINS_PER_REG) * 4);
1818 *bit = (pin_num % PX30_DRV_PINS_PER_REG);
1819 *bit *= PX30_DRV_BITS_PER_PIN;
1820 }
1821
1822 #define PX30_SCHMITT_PMU_OFFSET 0x38
1823 #define PX30_SCHMITT_GRF_OFFSET 0xc0
1824 #define PX30_SCHMITT_PINS_PER_PMU_REG 16
1825 #define PX30_SCHMITT_BANK_STRIDE 16
1826 #define PX30_SCHMITT_PINS_PER_GRF_REG 8
1827
px30_calc_schmitt_reg_and_bit(struct rockchip_pin_bank * bank,int pin_num,struct regmap ** regmap,int * reg,u8 * bit)1828 static int px30_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank,
1829 int pin_num,
1830 struct regmap **regmap,
1831 int *reg, u8 *bit)
1832 {
1833 struct rockchip_pinctrl_priv *priv = bank->priv;
1834 int pins_per_reg;
1835
1836 if (bank->bank_num == 0) {
1837 *regmap = priv->regmap_pmu;
1838 *reg = PX30_SCHMITT_PMU_OFFSET;
1839 pins_per_reg = PX30_SCHMITT_PINS_PER_PMU_REG;
1840 } else {
1841 *regmap = priv->regmap_base;
1842 *reg = PX30_SCHMITT_GRF_OFFSET;
1843 pins_per_reg = PX30_SCHMITT_PINS_PER_GRF_REG;
1844 *reg += (bank->bank_num - 1) * PX30_SCHMITT_BANK_STRIDE;
1845 }
1846 *reg += ((pin_num / pins_per_reg) * 4);
1847 *bit = pin_num % pins_per_reg;
1848
1849 return 0;
1850 }
1851
1852 #define RV1108_PULL_PMU_OFFSET 0x10
1853 #define RV1108_PULL_OFFSET 0x110
1854 #define RV1108_PULL_PINS_PER_REG 8
1855 #define RV1108_PULL_BITS_PER_PIN 2
1856 #define RV1108_PULL_BANK_STRIDE 16
1857
rv1108_calc_pull_reg_and_bit(struct rockchip_pin_bank * bank,int pin_num,struct regmap ** regmap,int * reg,u8 * bit)1858 static void rv1108_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
1859 int pin_num, struct regmap **regmap,
1860 int *reg, u8 *bit)
1861 {
1862 struct rockchip_pinctrl_priv *priv = bank->priv;
1863
1864 /* The first 24 pins of the first bank are located in PMU */
1865 if (bank->bank_num == 0) {
1866 *regmap = priv->regmap_pmu;
1867 *reg = RV1108_PULL_PMU_OFFSET;
1868 } else {
1869 *reg = RV1108_PULL_OFFSET;
1870 *regmap = priv->regmap_base;
1871 /* correct the offset, as we're starting with the 2nd bank */
1872 *reg -= 0x10;
1873 *reg += bank->bank_num * RV1108_PULL_BANK_STRIDE;
1874 }
1875
1876 *reg += ((pin_num / RV1108_PULL_PINS_PER_REG) * 4);
1877 *bit = (pin_num % RV1108_PULL_PINS_PER_REG);
1878 *bit *= RV1108_PULL_BITS_PER_PIN;
1879 }
1880
1881 #define RV1108_DRV_PMU_OFFSET 0x20
1882 #define RV1108_DRV_GRF_OFFSET 0x210
1883 #define RV1108_DRV_BITS_PER_PIN 2
1884 #define RV1108_DRV_PINS_PER_REG 8
1885 #define RV1108_DRV_BANK_STRIDE 16
1886
rv1108_calc_drv_reg_and_bit(struct rockchip_pin_bank * bank,int pin_num,struct regmap ** regmap,int * reg,u8 * bit)1887 static void rv1108_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
1888 int pin_num, struct regmap **regmap,
1889 int *reg, u8 *bit)
1890 {
1891 struct rockchip_pinctrl_priv *priv = bank->priv;
1892
1893 /* The first 24 pins of the first bank are located in PMU */
1894 if (bank->bank_num == 0) {
1895 *regmap = priv->regmap_pmu;
1896 *reg = RV1108_DRV_PMU_OFFSET;
1897 } else {
1898 *regmap = priv->regmap_base;
1899 *reg = RV1108_DRV_GRF_OFFSET;
1900
1901 /* correct the offset, as we're starting with the 2nd bank */
1902 *reg -= 0x10;
1903 *reg += bank->bank_num * RV1108_DRV_BANK_STRIDE;
1904 }
1905
1906 *reg += ((pin_num / RV1108_DRV_PINS_PER_REG) * 4);
1907 *bit = pin_num % RV1108_DRV_PINS_PER_REG;
1908 *bit *= RV1108_DRV_BITS_PER_PIN;
1909 }
1910
1911 #define RV1108_SCHMITT_PMU_OFFSET 0x30
1912 #define RV1108_SCHMITT_GRF_OFFSET 0x388
1913 #define RV1108_SCHMITT_BANK_STRIDE 8
1914 #define RV1108_SCHMITT_PINS_PER_GRF_REG 16
1915 #define RV1108_SCHMITT_PINS_PER_PMU_REG 8
1916
rv1108_calc_schmitt_reg_and_bit(struct rockchip_pin_bank * bank,int pin_num,struct regmap ** regmap,int * reg,u8 * bit)1917 static int rv1108_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank,
1918 int pin_num,
1919 struct regmap **regmap,
1920 int *reg, u8 *bit)
1921 {
1922 struct rockchip_pinctrl_priv *priv = bank->priv;
1923 int pins_per_reg;
1924
1925 if (bank->bank_num == 0) {
1926 *regmap = priv->regmap_pmu;
1927 *reg = RV1108_SCHMITT_PMU_OFFSET;
1928 pins_per_reg = RV1108_SCHMITT_PINS_PER_PMU_REG;
1929 } else {
1930 *regmap = priv->regmap_base;
1931 *reg = RV1108_SCHMITT_GRF_OFFSET;
1932 pins_per_reg = RV1108_SCHMITT_PINS_PER_GRF_REG;
1933 *reg += (bank->bank_num - 1) * RV1108_SCHMITT_BANK_STRIDE;
1934 }
1935 *reg += ((pin_num / pins_per_reg) * 4);
1936 *bit = pin_num % pins_per_reg;
1937
1938 return 0;
1939 }
1940
1941 #define RV1126_PULL_PMU_OFFSET 0x40
1942 #define RV1126_PULL_GRF_GPIO1A0_OFFSET 0x10108
1943 #define RV1126_PULL_PINS_PER_REG 8
1944 #define RV1126_PULL_BITS_PER_PIN 2
1945 #define RV1126_PULL_BANK_STRIDE 16
1946 #define RV1126_GPIO_C4_D7(p) (p >= 20 && p <= 31) /* GPIO0_C4 ~ GPIO0_D7 */
1947
rv1126_calc_pull_reg_and_bit(struct rockchip_pin_bank * bank,int pin_num,struct regmap ** regmap,int * reg,u8 * bit)1948 static void rv1126_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
1949 int pin_num, struct regmap **regmap,
1950 int *reg, u8 *bit)
1951 {
1952 struct rockchip_pinctrl_priv *priv = bank->priv;
1953
1954 /* The first 24 pins of the first bank are located in PMU */
1955 if (bank->bank_num == 0) {
1956 if (RV1126_GPIO_C4_D7(pin_num)) {
1957 *regmap = priv->regmap_base;
1958 *reg = RV1126_PULL_GRF_GPIO1A0_OFFSET;
1959 *reg -= (((31 - pin_num) / RV1126_PULL_PINS_PER_REG + 1) * 4);
1960 *bit = pin_num % RV1126_PULL_PINS_PER_REG;
1961 *bit *= RV1126_PULL_BITS_PER_PIN;
1962 return;
1963 }
1964 *regmap = priv->regmap_pmu;
1965 *reg = RV1126_PULL_PMU_OFFSET;
1966 } else {
1967 *reg = RV1126_PULL_GRF_GPIO1A0_OFFSET;
1968 *regmap = priv->regmap_base;
1969 *reg += (bank->bank_num - 1) * RV1126_PULL_BANK_STRIDE;
1970 }
1971
1972 *reg += ((pin_num / RV1126_PULL_PINS_PER_REG) * 4);
1973 *bit = (pin_num % RV1126_PULL_PINS_PER_REG);
1974 *bit *= RV1126_PULL_BITS_PER_PIN;
1975 }
1976
1977 #define RV1126_DRV_PMU_OFFSET 0x20
1978 #define RV1126_DRV_GRF_GPIO1A0_OFFSET 0x10090
1979 #define RV1126_DRV_BITS_PER_PIN 4
1980 #define RV1126_DRV_PINS_PER_REG 4
1981 #define RV1126_DRV_BANK_STRIDE 32
1982
rv1126_calc_drv_reg_and_bit(struct rockchip_pin_bank * bank,int pin_num,struct regmap ** regmap,int * reg,u8 * bit)1983 static void rv1126_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
1984 int pin_num, struct regmap **regmap,
1985 int *reg, u8 *bit)
1986 {
1987 struct rockchip_pinctrl_priv *priv = bank->priv;
1988
1989 /* The first 24 pins of the first bank are located in PMU */
1990 if (bank->bank_num == 0) {
1991 if (RV1126_GPIO_C4_D7(pin_num)) {
1992 *regmap = priv->regmap_base;
1993 *reg = RV1126_DRV_GRF_GPIO1A0_OFFSET;
1994 *reg -= (((31 - pin_num) / RV1126_DRV_PINS_PER_REG + 1) * 4);
1995 *reg -= 0x4;
1996 *bit = pin_num % RV1126_DRV_PINS_PER_REG;
1997 *bit *= RV1126_DRV_BITS_PER_PIN;
1998 return;
1999 }
2000 *regmap = priv->regmap_pmu;
2001 *reg = RV1126_DRV_PMU_OFFSET;
2002 } else {
2003 *regmap = priv->regmap_base;
2004 *reg = RV1126_DRV_GRF_GPIO1A0_OFFSET;
2005 *reg += (bank->bank_num - 1) * RV1126_DRV_BANK_STRIDE;
2006 }
2007
2008 *reg += ((pin_num / RV1126_DRV_PINS_PER_REG) * 4);
2009 *bit = pin_num % RV1126_DRV_PINS_PER_REG;
2010 *bit *= RV1126_DRV_BITS_PER_PIN;
2011 }
2012
2013 #define RV1126_SCHMITT_PMU_OFFSET 0x60
2014 #define RV1126_SCHMITT_GRF_GPIO1A0_OFFSET 0x10188
2015 #define RV1126_SCHMITT_BANK_STRIDE 16
2016 #define RV1126_SCHMITT_PINS_PER_GRF_REG 8
2017 #define RV1126_SCHMITT_PINS_PER_PMU_REG 8
2018
rv1126_calc_schmitt_reg_and_bit(struct rockchip_pin_bank * bank,int pin_num,struct regmap ** regmap,int * reg,u8 * bit)2019 static int rv1126_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank,
2020 int pin_num,
2021 struct regmap **regmap,
2022 int *reg, u8 *bit)
2023 {
2024 struct rockchip_pinctrl_priv *priv = bank->priv;
2025 int pins_per_reg;
2026
2027 if (bank->bank_num == 0) {
2028 if (RV1126_GPIO_C4_D7(pin_num)) {
2029 *regmap = priv->regmap_base;
2030 *reg = RV1126_SCHMITT_GRF_GPIO1A0_OFFSET;
2031 *reg -= (((31 - pin_num) / RV1126_SCHMITT_PINS_PER_GRF_REG + 1) * 4);
2032 *bit = pin_num % RV1126_SCHMITT_PINS_PER_GRF_REG;
2033 return 0;
2034 }
2035 *regmap = priv->regmap_pmu;
2036 *reg = RV1126_SCHMITT_PMU_OFFSET;
2037 pins_per_reg = RV1126_SCHMITT_PINS_PER_PMU_REG;
2038 } else {
2039 *regmap = priv->regmap_base;
2040 *reg = RV1126_SCHMITT_GRF_GPIO1A0_OFFSET;
2041 pins_per_reg = RV1126_SCHMITT_PINS_PER_GRF_REG;
2042 *reg += (bank->bank_num - 1) * RV1126_SCHMITT_BANK_STRIDE;
2043 }
2044 *reg += ((pin_num / pins_per_reg) * 4);
2045 *bit = pin_num % pins_per_reg;
2046
2047 return 0;
2048 }
2049
2050 #define RK1808_PULL_PMU_OFFSET 0x10
2051 #define RK1808_PULL_GRF_OFFSET 0x80
2052 #define RK1808_PULL_PINS_PER_REG 8
2053 #define RK1808_PULL_BITS_PER_PIN 2
2054 #define RK1808_PULL_BANK_STRIDE 16
2055
rk1808_calc_pull_reg_and_bit(struct rockchip_pin_bank * bank,int pin_num,struct regmap ** regmap,int * reg,u8 * bit)2056 static void rk1808_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
2057 int pin_num,
2058 struct regmap **regmap,
2059 int *reg, u8 *bit)
2060 {
2061 struct rockchip_pinctrl_priv *priv = bank->priv;
2062
2063 if (bank->bank_num == 0) {
2064 *regmap = priv->regmap_pmu;
2065 *reg = RK1808_PULL_PMU_OFFSET;
2066 } else {
2067 *reg = RK1808_PULL_GRF_OFFSET;
2068 *regmap = priv->regmap_base;
2069 }
2070
2071 *reg += ((pin_num / RK1808_PULL_PINS_PER_REG) * 4);
2072 *bit = (pin_num % RK1808_PULL_PINS_PER_REG);
2073 *bit *= RK1808_PULL_BITS_PER_PIN;
2074 }
2075
2076 #define RK1808_DRV_PMU_OFFSET 0x20
2077 #define RK1808_DRV_GRF_OFFSET 0x140
2078 #define RK1808_DRV_BITS_PER_PIN 2
2079 #define RK1808_DRV_PINS_PER_REG 8
2080 #define RK1808_DRV_BANK_STRIDE 16
2081
rk1808_calc_drv_reg_and_bit(struct rockchip_pin_bank * bank,int pin_num,struct regmap ** regmap,int * reg,u8 * bit)2082 static void rk1808_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
2083 int pin_num,
2084 struct regmap **regmap,
2085 int *reg, u8 *bit)
2086 {
2087 struct rockchip_pinctrl_priv *priv = bank->priv;
2088
2089 if (bank->bank_num == 0) {
2090 *regmap = priv->regmap_pmu;
2091 *reg = RK1808_DRV_PMU_OFFSET;
2092 } else {
2093 *regmap = priv->regmap_base;
2094 *reg = RK1808_DRV_GRF_OFFSET;
2095 }
2096
2097 *reg += ((pin_num / RK1808_DRV_PINS_PER_REG) * 4);
2098 *bit = pin_num % RK1808_DRV_PINS_PER_REG;
2099 *bit *= RK1808_DRV_BITS_PER_PIN;
2100 }
2101
2102 #define RK1808_SCHMITT_PMU_OFFSET 0x0040
2103 #define RK1808_SCHMITT_GRF_OFFSET 0x0100
2104 #define RK1808_SCHMITT_BANK_STRIDE 16
2105 #define RK1808_SCHMITT_PINS_PER_REG 8
2106
rk1808_calc_schmitt_reg_and_bit(struct rockchip_pin_bank * bank,int pin_num,struct regmap ** regmap,int * reg,u8 * bit)2107 static int rk1808_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank,
2108 int pin_num,
2109 struct regmap **regmap,
2110 int *reg, u8 *bit)
2111 {
2112 struct rockchip_pinctrl_priv *priv = bank->priv;
2113
2114 if (bank->bank_num == 0) {
2115 *regmap = priv->regmap_pmu;
2116 *reg = RK1808_SCHMITT_PMU_OFFSET;
2117 } else {
2118 *regmap = priv->regmap_base;
2119 *reg = RK1808_SCHMITT_GRF_OFFSET;
2120 *reg += (bank->bank_num - 1) * RK1808_SCHMITT_BANK_STRIDE;
2121 }
2122 *reg += ((pin_num / RK1808_SCHMITT_PINS_PER_REG) * 4);
2123 *bit = pin_num % RK1808_SCHMITT_PINS_PER_REG;
2124
2125 return 0;
2126 }
2127
2128 #define RK2928_PULL_OFFSET 0x118
2129 #define RK2928_PULL_PINS_PER_REG 16
2130 #define RK2928_PULL_BANK_STRIDE 8
2131
rk2928_calc_pull_reg_and_bit(struct rockchip_pin_bank * bank,int pin_num,struct regmap ** regmap,int * reg,u8 * bit)2132 static void rk2928_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
2133 int pin_num, struct regmap **regmap,
2134 int *reg, u8 *bit)
2135 {
2136 struct rockchip_pinctrl_priv *priv = bank->priv;
2137
2138 *regmap = priv->regmap_base;
2139 *reg = RK2928_PULL_OFFSET;
2140 *reg += bank->bank_num * RK2928_PULL_BANK_STRIDE;
2141 *reg += (pin_num / RK2928_PULL_PINS_PER_REG) * 4;
2142
2143 *bit = pin_num % RK2928_PULL_PINS_PER_REG;
2144 };
2145
2146 #define RK3128_PULL_OFFSET 0x118
2147
rk3128_calc_pull_reg_and_bit(struct rockchip_pin_bank * bank,int pin_num,struct regmap ** regmap,int * reg,u8 * bit)2148 static void rk3128_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
2149 int pin_num, struct regmap **regmap,
2150 int *reg, u8 *bit)
2151 {
2152 struct rockchip_pinctrl_priv *priv = bank->priv;
2153
2154 *regmap = priv->regmap_base;
2155 *reg = RK3128_PULL_OFFSET;
2156 *reg += bank->bank_num * RK2928_PULL_BANK_STRIDE;
2157 *reg += ((pin_num / RK2928_PULL_PINS_PER_REG) * 4);
2158
2159 *bit = pin_num % RK2928_PULL_PINS_PER_REG;
2160 }
2161
2162 #define RK3188_PULL_OFFSET 0x164
2163 #define RK3188_PULL_BITS_PER_PIN 2
2164 #define RK3188_PULL_PINS_PER_REG 8
2165 #define RK3188_PULL_BANK_STRIDE 16
2166 #define RK3188_PULL_PMU_OFFSET 0x64
2167
rk3188_calc_pull_reg_and_bit(struct rockchip_pin_bank * bank,int pin_num,struct regmap ** regmap,int * reg,u8 * bit)2168 static void rk3188_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
2169 int pin_num, struct regmap **regmap,
2170 int *reg, u8 *bit)
2171 {
2172 struct rockchip_pinctrl_priv *priv = bank->priv;
2173
2174 /* The first 12 pins of the first bank are located elsewhere */
2175 if (bank->bank_num == 0 && pin_num < 12) {
2176 *regmap = priv->regmap_pmu;
2177 *reg = RK3188_PULL_PMU_OFFSET;
2178
2179 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
2180 *bit = pin_num % RK3188_PULL_PINS_PER_REG;
2181 *bit *= RK3188_PULL_BITS_PER_PIN;
2182 } else {
2183 *regmap = priv->regmap_base;
2184 *reg = RK3188_PULL_OFFSET;
2185
2186 /* correct the offset, as it is the 2nd pull register */
2187 *reg -= 4;
2188 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
2189 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
2190
2191 /*
2192 * The bits in these registers have an inverse ordering
2193 * with the lowest pin being in bits 15:14 and the highest
2194 * pin in bits 1:0
2195 */
2196 *bit = 7 - (pin_num % RK3188_PULL_PINS_PER_REG);
2197 *bit *= RK3188_PULL_BITS_PER_PIN;
2198 }
2199 }
2200
2201 #define RK3288_PULL_OFFSET 0x140
rk3288_calc_pull_reg_and_bit(struct rockchip_pin_bank * bank,int pin_num,struct regmap ** regmap,int * reg,u8 * bit)2202 static void rk3288_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
2203 int pin_num, struct regmap **regmap,
2204 int *reg, u8 *bit)
2205 {
2206 struct rockchip_pinctrl_priv *priv = bank->priv;
2207
2208 /* The first 24 pins of the first bank are located in PMU */
2209 if (bank->bank_num == 0) {
2210 *regmap = priv->regmap_pmu;
2211 *reg = RK3188_PULL_PMU_OFFSET;
2212
2213 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
2214 *bit = pin_num % RK3188_PULL_PINS_PER_REG;
2215 *bit *= RK3188_PULL_BITS_PER_PIN;
2216 } else {
2217 *regmap = priv->regmap_base;
2218 *reg = RK3288_PULL_OFFSET;
2219
2220 /* correct the offset, as we're starting with the 2nd bank */
2221 *reg -= 0x10;
2222 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
2223 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
2224
2225 *bit = (pin_num % RK3188_PULL_PINS_PER_REG);
2226 *bit *= RK3188_PULL_BITS_PER_PIN;
2227 }
2228 }
2229
2230 #define RK3288_DRV_PMU_OFFSET 0x70
2231 #define RK3288_DRV_GRF_OFFSET 0x1c0
2232 #define RK3288_DRV_BITS_PER_PIN 2
2233 #define RK3288_DRV_PINS_PER_REG 8
2234 #define RK3288_DRV_BANK_STRIDE 16
2235
rk3288_calc_drv_reg_and_bit(struct rockchip_pin_bank * bank,int pin_num,struct regmap ** regmap,int * reg,u8 * bit)2236 static void rk3288_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
2237 int pin_num, struct regmap **regmap,
2238 int *reg, u8 *bit)
2239 {
2240 struct rockchip_pinctrl_priv *priv = bank->priv;
2241
2242 /* The first 24 pins of the first bank are located in PMU */
2243 if (bank->bank_num == 0) {
2244 *regmap = priv->regmap_pmu;
2245 *reg = RK3288_DRV_PMU_OFFSET;
2246
2247 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4);
2248 *bit = pin_num % RK3288_DRV_PINS_PER_REG;
2249 *bit *= RK3288_DRV_BITS_PER_PIN;
2250 } else {
2251 *regmap = priv->regmap_base;
2252 *reg = RK3288_DRV_GRF_OFFSET;
2253
2254 /* correct the offset, as we're starting with the 2nd bank */
2255 *reg -= 0x10;
2256 *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE;
2257 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4);
2258
2259 *bit = (pin_num % RK3288_DRV_PINS_PER_REG);
2260 *bit *= RK3288_DRV_BITS_PER_PIN;
2261 }
2262 }
2263
2264 #define RK3228_PULL_OFFSET 0x100
2265
rk3228_calc_pull_reg_and_bit(struct rockchip_pin_bank * bank,int pin_num,struct regmap ** regmap,int * reg,u8 * bit)2266 static void rk3228_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
2267 int pin_num, struct regmap **regmap,
2268 int *reg, u8 *bit)
2269 {
2270 struct rockchip_pinctrl_priv *priv = bank->priv;
2271
2272 *regmap = priv->regmap_base;
2273 *reg = RK3228_PULL_OFFSET;
2274 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
2275 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
2276
2277 *bit = (pin_num % RK3188_PULL_PINS_PER_REG);
2278 *bit *= RK3188_PULL_BITS_PER_PIN;
2279 }
2280
2281 #define RK3228_DRV_GRF_OFFSET 0x200
2282
rk3228_calc_drv_reg_and_bit(struct rockchip_pin_bank * bank,int pin_num,struct regmap ** regmap,int * reg,u8 * bit)2283 static void rk3228_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
2284 int pin_num, struct regmap **regmap,
2285 int *reg, u8 *bit)
2286 {
2287 struct rockchip_pinctrl_priv *priv = bank->priv;
2288
2289 *regmap = priv->regmap_base;
2290 *reg = RK3228_DRV_GRF_OFFSET;
2291 *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE;
2292 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4);
2293
2294 *bit = (pin_num % RK3288_DRV_PINS_PER_REG);
2295 *bit *= RK3288_DRV_BITS_PER_PIN;
2296 }
2297
2298 #define RK3308_PULL_OFFSET 0xa0
2299
rk3308_calc_pull_reg_and_bit(struct rockchip_pin_bank * bank,int pin_num,struct regmap ** regmap,int * reg,u8 * bit)2300 static void rk3308_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
2301 int pin_num, struct regmap **regmap,
2302 int *reg, u8 *bit)
2303 {
2304 struct rockchip_pinctrl_priv *priv = bank->priv;
2305
2306 *regmap = priv->regmap_base;
2307 *reg = RK3308_PULL_OFFSET;
2308 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
2309 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
2310
2311 *bit = (pin_num % RK3188_PULL_PINS_PER_REG);
2312 *bit *= RK3188_PULL_BITS_PER_PIN;
2313 }
2314
2315 #define RK3308_DRV_GRF_OFFSET 0x100
2316
rk3308_calc_drv_reg_and_bit(struct rockchip_pin_bank * bank,int pin_num,struct regmap ** regmap,int * reg,u8 * bit)2317 static void rk3308_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
2318 int pin_num, struct regmap **regmap,
2319 int *reg, u8 *bit)
2320 {
2321 struct rockchip_pinctrl_priv *priv = bank->priv;
2322
2323 *regmap = priv->regmap_base;
2324 *reg = RK3308_DRV_GRF_OFFSET;
2325 *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE;
2326 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4);
2327
2328 *bit = (pin_num % RK3288_DRV_PINS_PER_REG);
2329 *bit *= RK3288_DRV_BITS_PER_PIN;
2330 }
2331
2332 #define RK3308_SCHMITT_PINS_PER_REG 8
2333 #define RK3308_SCHMITT_BANK_STRIDE 16
2334 #define RK3308_SCHMITT_GRF_OFFSET 0x1a0
2335
rk3308_calc_schmitt_reg_and_bit(struct rockchip_pin_bank * bank,int pin_num,struct regmap ** regmap,int * reg,u8 * bit)2336 static int rk3308_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank,
2337 int pin_num,
2338 struct regmap **regmap,
2339 int *reg, u8 *bit)
2340 {
2341 struct rockchip_pinctrl_priv *priv = bank->priv;
2342
2343 *regmap = priv->regmap_base;
2344 *reg = RK3308_SCHMITT_GRF_OFFSET;
2345
2346 *reg += bank->bank_num * RK3308_SCHMITT_BANK_STRIDE;
2347 *reg += ((pin_num / RK3308_SCHMITT_PINS_PER_REG) * 4);
2348 *bit = pin_num % RK3308_SCHMITT_PINS_PER_REG;
2349
2350 return 0;
2351 }
2352
2353 #define RK3368_PULL_GRF_OFFSET 0x100
2354 #define RK3368_PULL_PMU_OFFSET 0x10
2355
rk3368_calc_pull_reg_and_bit(struct rockchip_pin_bank * bank,int pin_num,struct regmap ** regmap,int * reg,u8 * bit)2356 static void rk3368_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
2357 int pin_num, struct regmap **regmap,
2358 int *reg, u8 *bit)
2359 {
2360 struct rockchip_pinctrl_priv *priv = bank->priv;
2361
2362 /* The first 32 pins of the first bank are located in PMU */
2363 if (bank->bank_num == 0) {
2364 *regmap = priv->regmap_pmu;
2365 *reg = RK3368_PULL_PMU_OFFSET;
2366
2367 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
2368 *bit = pin_num % RK3188_PULL_PINS_PER_REG;
2369 *bit *= RK3188_PULL_BITS_PER_PIN;
2370 } else {
2371 *regmap = priv->regmap_base;
2372 *reg = RK3368_PULL_GRF_OFFSET;
2373
2374 /* correct the offset, as we're starting with the 2nd bank */
2375 *reg -= 0x10;
2376 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
2377 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
2378
2379 *bit = (pin_num % RK3188_PULL_PINS_PER_REG);
2380 *bit *= RK3188_PULL_BITS_PER_PIN;
2381 }
2382 }
2383
2384 #define RK3368_DRV_PMU_OFFSET 0x20
2385 #define RK3368_DRV_GRF_OFFSET 0x200
2386
rk3368_calc_drv_reg_and_bit(struct rockchip_pin_bank * bank,int pin_num,struct regmap ** regmap,int * reg,u8 * bit)2387 static void rk3368_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
2388 int pin_num, struct regmap **regmap,
2389 int *reg, u8 *bit)
2390 {
2391 struct rockchip_pinctrl_priv *priv = bank->priv;
2392
2393 /* The first 32 pins of the first bank are located in PMU */
2394 if (bank->bank_num == 0) {
2395 *regmap = priv->regmap_pmu;
2396 *reg = RK3368_DRV_PMU_OFFSET;
2397
2398 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4);
2399 *bit = pin_num % RK3288_DRV_PINS_PER_REG;
2400 *bit *= RK3288_DRV_BITS_PER_PIN;
2401 } else {
2402 *regmap = priv->regmap_base;
2403 *reg = RK3368_DRV_GRF_OFFSET;
2404
2405 /* correct the offset, as we're starting with the 2nd bank */
2406 *reg -= 0x10;
2407 *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE;
2408 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4);
2409
2410 *bit = (pin_num % RK3288_DRV_PINS_PER_REG);
2411 *bit *= RK3288_DRV_BITS_PER_PIN;
2412 }
2413 }
2414
2415 #define RK3399_PULL_GRF_OFFSET 0xe040
2416 #define RK3399_PULL_PMU_OFFSET 0x40
2417 #define RK3399_DRV_3BITS_PER_PIN 3
2418
rk3399_calc_pull_reg_and_bit(struct rockchip_pin_bank * bank,int pin_num,struct regmap ** regmap,int * reg,u8 * bit)2419 static void rk3399_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
2420 int pin_num, struct regmap **regmap,
2421 int *reg, u8 *bit)
2422 {
2423 struct rockchip_pinctrl_priv *priv = bank->priv;
2424
2425 /* The bank0:16 and bank1:32 pins are located in PMU */
2426 if ((bank->bank_num == 0) || (bank->bank_num == 1)) {
2427 *regmap = priv->regmap_pmu;
2428 *reg = RK3399_PULL_PMU_OFFSET;
2429
2430 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
2431
2432 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
2433 *bit = pin_num % RK3188_PULL_PINS_PER_REG;
2434 *bit *= RK3188_PULL_BITS_PER_PIN;
2435 } else {
2436 *regmap = priv->regmap_base;
2437 *reg = RK3399_PULL_GRF_OFFSET;
2438
2439 /* correct the offset, as we're starting with the 3rd bank */
2440 *reg -= 0x20;
2441 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
2442 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
2443
2444 *bit = (pin_num % RK3188_PULL_PINS_PER_REG);
2445 *bit *= RK3188_PULL_BITS_PER_PIN;
2446 }
2447 }
2448
rk3399_calc_drv_reg_and_bit(struct rockchip_pin_bank * bank,int pin_num,struct regmap ** regmap,int * reg,u8 * bit)2449 static void rk3399_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
2450 int pin_num, struct regmap **regmap,
2451 int *reg, u8 *bit)
2452 {
2453 struct rockchip_pinctrl_priv *priv = bank->priv;
2454 int drv_num = (pin_num / 8);
2455
2456 /* The bank0:16 and bank1:32 pins are located in PMU */
2457 if ((bank->bank_num == 0) || (bank->bank_num == 1))
2458 *regmap = priv->regmap_pmu;
2459 else
2460 *regmap = priv->regmap_base;
2461
2462 *reg = bank->drv[drv_num].offset;
2463 if ((bank->drv[drv_num].drv_type == DRV_TYPE_IO_1V8_3V0_AUTO) ||
2464 (bank->drv[drv_num].drv_type == DRV_TYPE_IO_3V3_ONLY))
2465 *bit = (pin_num % 8) * 3;
2466 else
2467 *bit = (pin_num % 8) * 2;
2468 }
2469
2470 #define RK3308_SLEW_RATE_GRF_OFFSET 0x150
2471 #define RK3308_SLEW_RATE_BANK_STRIDE 16
2472 #define RK3308_SLEW_RATE_PINS_PER_GRF_REG 8
2473
rk3308_calc_slew_rate_reg_and_bit(struct rockchip_pin_bank * bank,int pin_num,struct regmap ** regmap,int * reg,u8 * bit)2474 static void rk3308_calc_slew_rate_reg_and_bit(struct rockchip_pin_bank *bank,
2475 int pin_num,
2476 struct regmap **regmap,
2477 int *reg, u8 *bit)
2478 {
2479 struct rockchip_pinctrl_priv *priv = bank->priv;
2480 int pins_per_reg;
2481
2482 *regmap = priv->regmap_base;
2483 *reg = RK3308_SLEW_RATE_GRF_OFFSET;
2484 *reg += (bank->bank_num) * RK3308_SLEW_RATE_BANK_STRIDE;
2485 pins_per_reg = RK3308_SLEW_RATE_PINS_PER_GRF_REG;
2486
2487 *reg += ((pin_num / pins_per_reg) * 4);
2488 *bit = pin_num % pins_per_reg;
2489 }
2490
2491 static int rockchip_perpin_drv_list[DRV_TYPE_MAX][8] = {
2492 { 2, 4, 8, 12, -1, -1, -1, -1 },
2493 { 3, 6, 9, 12, -1, -1, -1, -1 },
2494 { 5, 10, 15, 20, -1, -1, -1, -1 },
2495 { 4, 6, 8, 10, 12, 14, 16, 18 },
2496 { 4, 7, 10, 13, 16, 19, 22, 26 },
2497 { 0, 2, 4, 6, 6, 8, 10, 12 }
2498 };
2499
rockchip_set_drive_perpin(struct rockchip_pin_bank * bank,int pin_num,int strength)2500 static int rockchip_set_drive_perpin(struct rockchip_pin_bank *bank,
2501 int pin_num, int strength)
2502 {
2503 struct rockchip_pinctrl_priv *priv = bank->priv;
2504 struct rockchip_pin_ctrl *ctrl = priv->ctrl;
2505 struct regmap *regmap;
2506 int reg, ret, i;
2507 u32 data, rmask_bits, temp;
2508 u8 bit;
2509 /* Where need to clean the special mask for rockchip_perpin_drv_list */
2510 int drv_type = bank->drv[pin_num / 8].drv_type & (~DRV_TYPE_IO_MASK);
2511
2512 debug("setting drive of GPIO%d-%d to %d\n", bank->bank_num,
2513 pin_num, strength);
2514
2515 ctrl->drv_calc_reg(bank, pin_num, ®map, ®, &bit);
2516 if (ctrl->type == RV1126) {
2517 rmask_bits = RV1126_DRV_BITS_PER_PIN;
2518 ret = strength;
2519 goto config;
2520 }
2521 if (soc_is_rk3308bs())
2522 drv_type = DRV_TYPE_IO_SMIC;
2523
2524 ret = -EINVAL;
2525 for (i = 0; i < ARRAY_SIZE(rockchip_perpin_drv_list[drv_type]); i++) {
2526 if (rockchip_perpin_drv_list[drv_type][i] == strength) {
2527 ret = i;
2528 break;
2529 } else if (rockchip_perpin_drv_list[drv_type][i] < 0) {
2530 ret = rockchip_perpin_drv_list[drv_type][i];
2531 break;
2532 }
2533 }
2534
2535 if (ret < 0) {
2536 debug("unsupported driver strength %d\n", strength);
2537 return ret;
2538 }
2539
2540 switch (drv_type) {
2541 case DRV_TYPE_IO_SMIC:
2542 if (ctrl->type == RK3308) { /* RK3308B-S */
2543 int regval = ret;
2544
2545 data = 0x3 << (bit + 16);
2546 data |= ((regval & 0x3) << bit);
2547
2548 ret = regmap_write(regmap, reg, data);
2549 if (ret < 0)
2550 return ret;
2551
2552 rk3308_calc_slew_rate_reg_and_bit(bank, pin_num, ®map, ®, &bit);
2553 data = BIT(bit + 16) | (((regval > 3) ? 1 : 0) << bit);
2554
2555 return regmap_write(regmap, reg, data);
2556 }
2557
2558 dev_err(info->dev, "unsupported type DRV_TYPE_IO_SMIC\n");
2559 return -EINVAL;
2560 case DRV_TYPE_IO_1V8_3V0_AUTO:
2561 case DRV_TYPE_IO_3V3_ONLY:
2562 rmask_bits = RK3399_DRV_3BITS_PER_PIN;
2563 switch (bit) {
2564 case 0 ... 12:
2565 /* regular case, nothing to do */
2566 break;
2567 case 15:
2568 /*
2569 * drive-strength offset is special, as it is spread
2570 * over 2 registers, the bit data[15] contains bit 0
2571 * of the value while temp[1:0] contains bits 2 and 1
2572 */
2573 data = (ret & 0x1) << 15;
2574 temp = (ret >> 0x1) & 0x3;
2575
2576 data |= BIT(31);
2577 ret = regmap_write(regmap, reg, data);
2578 if (ret)
2579 return ret;
2580
2581 temp |= (0x3 << 16);
2582 reg += 0x4;
2583 ret = regmap_write(regmap, reg, temp);
2584
2585 return ret;
2586 case 18 ... 21:
2587 /* setting fully enclosed in the second register */
2588 reg += 4;
2589 bit -= 16;
2590 break;
2591 default:
2592 debug("unsupported bit: %d for pinctrl drive type: %d\n",
2593 bit, drv_type);
2594 return -EINVAL;
2595 }
2596 break;
2597 case DRV_TYPE_IO_DEFAULT:
2598 case DRV_TYPE_IO_1V8_OR_3V0:
2599 case DRV_TYPE_IO_1V8_ONLY:
2600 rmask_bits = RK3288_DRV_BITS_PER_PIN;
2601 break;
2602 default:
2603 debug("unsupported pinctrl drive type: %d\n",
2604 drv_type);
2605 return -EINVAL;
2606 }
2607
2608 config:
2609 if (bank->drv[pin_num / 8].drv_type & DRV_TYPE_WRITABLE_32BIT) {
2610 regmap_read(regmap, reg, &data);
2611 data &= ~(((1 << rmask_bits) - 1) << bit);
2612 } else {
2613 /* enable the write to the equivalent lower bits */
2614 data = ((1 << rmask_bits) - 1) << (bit + 16);
2615 }
2616
2617 data |= (ret << bit);
2618 ret = regmap_write(regmap, reg, data);
2619 return ret;
2620 }
2621
2622 static int rockchip_pull_list[PULL_TYPE_MAX][4] = {
2623 {
2624 PIN_CONFIG_BIAS_DISABLE,
2625 PIN_CONFIG_BIAS_PULL_UP,
2626 PIN_CONFIG_BIAS_PULL_DOWN,
2627 PIN_CONFIG_BIAS_BUS_HOLD
2628 },
2629 {
2630 PIN_CONFIG_BIAS_DISABLE,
2631 PIN_CONFIG_BIAS_PULL_DOWN,
2632 PIN_CONFIG_BIAS_DISABLE,
2633 PIN_CONFIG_BIAS_PULL_UP
2634 },
2635 };
2636
rockchip_set_pull(struct rockchip_pin_bank * bank,int pin_num,int pull)2637 static int rockchip_set_pull(struct rockchip_pin_bank *bank,
2638 int pin_num, int pull)
2639 {
2640 struct rockchip_pinctrl_priv *priv = bank->priv;
2641 struct rockchip_pin_ctrl *ctrl = priv->ctrl;
2642 struct regmap *regmap;
2643 int reg, ret, i, pull_type;
2644 u8 bit;
2645 u32 data;
2646
2647 debug("setting pull of GPIO%d-%d to %d\n", bank->bank_num,
2648 pin_num, pull);
2649
2650 /* rk3066b does support any pulls */
2651 if (ctrl->type == RK3066B)
2652 return pull ? -EINVAL : 0;
2653
2654 ctrl->pull_calc_reg(bank, pin_num, ®map, ®, &bit);
2655
2656 switch (ctrl->type) {
2657 case RK2928:
2658 case RK3128:
2659 data = BIT(bit + 16);
2660 if (pull == PIN_CONFIG_BIAS_DISABLE)
2661 data |= BIT(bit);
2662 ret = regmap_write(regmap, reg, data);
2663 break;
2664 case PX30:
2665 case RV1108:
2666 case RV1126:
2667 case RK1808:
2668 case RK3188:
2669 case RK3288:
2670 case RK3308:
2671 case RK3368:
2672 case RK3399:
2673 /*
2674 * Where need to clean the special mask for
2675 * rockchip_pull_list.
2676 */
2677 pull_type = bank->pull_type[pin_num / 8] & (~PULL_TYPE_IO_MASK);
2678 ret = -EINVAL;
2679 for (i = 0; i < ARRAY_SIZE(rockchip_pull_list[pull_type]);
2680 i++) {
2681 if (rockchip_pull_list[pull_type][i] == pull) {
2682 ret = i;
2683 break;
2684 }
2685 }
2686
2687 if (ret < 0) {
2688 debug("unsupported pull setting %d\n", pull);
2689 return ret;
2690 }
2691
2692 if (bank->pull_type[pin_num / 8] & PULL_TYPE_WRITABLE_32BIT) {
2693 regmap_read(regmap, reg, &data);
2694 data &= ~(((1 << RK3188_PULL_BITS_PER_PIN) - 1) << bit);
2695 } else {
2696 /* enable the write to the equivalent lower bits */
2697 data = ((1 << RK3188_PULL_BITS_PER_PIN) - 1) << (bit + 16);
2698 }
2699
2700 data |= (ret << bit);
2701 ret = regmap_write(regmap, reg, data);
2702 break;
2703 default:
2704 debug("unsupported pinctrl type\n");
2705 return -EINVAL;
2706 }
2707
2708 return ret;
2709 }
2710
2711 #define RK3328_SCHMITT_BITS_PER_PIN 1
2712 #define RK3328_SCHMITT_PINS_PER_REG 16
2713 #define RK3328_SCHMITT_BANK_STRIDE 8
2714 #define RK3328_SCHMITT_GRF_OFFSET 0x380
2715
rk3328_calc_schmitt_reg_and_bit(struct rockchip_pin_bank * bank,int pin_num,struct regmap ** regmap,int * reg,u8 * bit)2716 static int rk3328_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank,
2717 int pin_num,
2718 struct regmap **regmap,
2719 int *reg, u8 *bit)
2720 {
2721 struct rockchip_pinctrl_priv *priv = bank->priv;
2722
2723 *regmap = priv->regmap_base;
2724 *reg = RK3328_SCHMITT_GRF_OFFSET;
2725
2726 *reg += bank->bank_num * RK3328_SCHMITT_BANK_STRIDE;
2727 *reg += ((pin_num / RK3328_SCHMITT_PINS_PER_REG) * 4);
2728 *bit = pin_num % RK3328_SCHMITT_PINS_PER_REG;
2729
2730 return 0;
2731 }
2732
rockchip_set_schmitt(struct rockchip_pin_bank * bank,int pin_num,int enable)2733 static int rockchip_set_schmitt(struct rockchip_pin_bank *bank,
2734 int pin_num, int enable)
2735 {
2736 struct rockchip_pinctrl_priv *priv = bank->priv;
2737 struct rockchip_pin_ctrl *ctrl = priv->ctrl;
2738 struct regmap *regmap;
2739 int reg, ret;
2740 u8 bit;
2741 u32 data;
2742
2743 debug("setting input schmitt of GPIO%d-%d to %d\n", bank->bank_num,
2744 pin_num, enable);
2745
2746 ret = ctrl->schmitt_calc_reg(bank, pin_num, ®map, ®, &bit);
2747 if (ret)
2748 return ret;
2749
2750 /* enable the write to the equivalent lower bits */
2751 data = BIT(bit + 16) | (enable << bit);
2752
2753 return regmap_write(regmap, reg, data);
2754 }
2755
2756 #define PX30_SLEW_RATE_PMU_OFFSET 0x30
2757 #define PX30_SLEW_RATE_GRF_OFFSET 0x90
2758 #define PX30_SLEW_RATE_PINS_PER_PMU_REG 16
2759 #define PX30_SLEW_RATE_BANK_STRIDE 16
2760 #define PX30_SLEW_RATE_PINS_PER_GRF_REG 8
2761
px30_calc_slew_rate_reg_and_bit(struct rockchip_pin_bank * bank,int pin_num,struct regmap ** regmap,int * reg,u8 * bit)2762 static int px30_calc_slew_rate_reg_and_bit(struct rockchip_pin_bank *bank,
2763 int pin_num,
2764 struct regmap **regmap,
2765 int *reg, u8 *bit)
2766 {
2767 struct rockchip_pinctrl_priv *priv = bank->priv;
2768 int pins_per_reg;
2769
2770 if (bank->bank_num == 0) {
2771 *regmap = priv->regmap_pmu;
2772 *reg = PX30_SLEW_RATE_PMU_OFFSET;
2773 pins_per_reg = PX30_SCHMITT_PINS_PER_PMU_REG;
2774 } else {
2775 *regmap = priv->regmap_base;
2776 *reg = PX30_SCHMITT_GRF_OFFSET;
2777 pins_per_reg = PX30_SCHMITT_PINS_PER_GRF_REG;
2778 *reg += (bank->bank_num - 1) * PX30_SCHMITT_BANK_STRIDE;
2779 }
2780 *reg += ((pin_num / pins_per_reg) * 4);
2781 *bit = pin_num % pins_per_reg;
2782
2783 return 0;
2784 }
2785
rockchip_set_slew_rate(struct rockchip_pin_bank * bank,int pin_num,int speed)2786 static int rockchip_set_slew_rate(struct rockchip_pin_bank *bank,
2787 int pin_num, int speed)
2788 {
2789 struct rockchip_pinctrl_priv *priv = bank->priv;
2790 struct rockchip_pin_ctrl *ctrl = priv->ctrl;
2791 struct regmap *regmap;
2792 int reg, ret;
2793 u8 bit;
2794 u32 data;
2795
2796 debug("setting slew rate of GPIO%d-%d to %d\n", bank->bank_num,
2797 pin_num, speed);
2798
2799 ret = ctrl->slew_rate_calc_reg(bank, pin_num, ®map, ®, &bit);
2800 if (ret)
2801 return ret;
2802
2803 /* enable the write to the equivalent lower bits */
2804 data = BIT(bit + 16) | (speed << bit);
2805
2806 return regmap_write(regmap, reg, data);
2807 }
2808
2809 /*
2810 * Pinconf_ops handling
2811 */
rockchip_pinconf_pull_valid(struct rockchip_pin_ctrl * ctrl,unsigned int pull)2812 static bool rockchip_pinconf_pull_valid(struct rockchip_pin_ctrl *ctrl,
2813 unsigned int pull)
2814 {
2815 switch (ctrl->type) {
2816 case RK2928:
2817 case RK3128:
2818 return (pull == PIN_CONFIG_BIAS_PULL_PIN_DEFAULT ||
2819 pull == PIN_CONFIG_BIAS_DISABLE);
2820 case RK3066B:
2821 return pull ? false : true;
2822 case PX30:
2823 case RV1108:
2824 case RV1126:
2825 case RK1808:
2826 case RK3188:
2827 case RK3288:
2828 case RK3308:
2829 case RK3368:
2830 case RK3399:
2831 return (pull != PIN_CONFIG_BIAS_PULL_PIN_DEFAULT);
2832 }
2833
2834 return false;
2835 }
2836
2837 /* set the pin config settings for a specified pin */
rockchip_pinconf_set(struct rockchip_pin_bank * bank,u32 pin,u32 param,u32 arg)2838 static int rockchip_pinconf_set(struct rockchip_pin_bank *bank,
2839 u32 pin, u32 param, u32 arg)
2840 {
2841 struct rockchip_pinctrl_priv *priv = bank->priv;
2842 struct rockchip_pin_ctrl *ctrl = priv->ctrl;
2843 int rc;
2844
2845 switch (param) {
2846 case PIN_CONFIG_BIAS_DISABLE:
2847 rc = rockchip_set_pull(bank, pin, param);
2848 if (rc)
2849 return rc;
2850 break;
2851
2852 case PIN_CONFIG_BIAS_PULL_UP:
2853 case PIN_CONFIG_BIAS_PULL_DOWN:
2854 case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT:
2855 case PIN_CONFIG_BIAS_BUS_HOLD:
2856 if (!rockchip_pinconf_pull_valid(ctrl, param))
2857 return -ENOTSUPP;
2858
2859 if (!arg)
2860 return -EINVAL;
2861
2862 rc = rockchip_set_pull(bank, pin, param);
2863 if (rc)
2864 return rc;
2865 break;
2866
2867 case PIN_CONFIG_DRIVE_STRENGTH:
2868 if (!ctrl->drv_calc_reg)
2869 return -ENOTSUPP;
2870
2871 rc = rockchip_set_drive_perpin(bank, pin, arg);
2872 if (rc < 0)
2873 return rc;
2874 break;
2875
2876 case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
2877 if (!ctrl->schmitt_calc_reg)
2878 return -ENOTSUPP;
2879
2880 rc = rockchip_set_schmitt(bank, pin, arg);
2881 if (rc < 0)
2882 return rc;
2883 break;
2884
2885 case PIN_CONFIG_SLEW_RATE:
2886 if (!ctrl->slew_rate_calc_reg)
2887 return -ENOTSUPP;
2888
2889 rc = rockchip_set_slew_rate(bank,
2890 pin - bank->pin_base, arg);
2891 if (rc < 0)
2892 return rc;
2893 break;
2894
2895 default:
2896 break;
2897 }
2898
2899 return 0;
2900 }
2901
2902 static const struct pinconf_param rockchip_conf_params[] = {
2903 { "bias-disable", PIN_CONFIG_BIAS_DISABLE, 0 },
2904 { "bias-bus-hold", PIN_CONFIG_BIAS_BUS_HOLD, 0 },
2905 { "bias-pull-up", PIN_CONFIG_BIAS_PULL_UP, 1 },
2906 { "bias-pull-down", PIN_CONFIG_BIAS_PULL_DOWN, 1 },
2907 { "drive-strength", PIN_CONFIG_DRIVE_STRENGTH, 0 },
2908 { "input-enable", PIN_CONFIG_INPUT_ENABLE, 1 },
2909 { "input-disable", PIN_CONFIG_INPUT_ENABLE, 0 },
2910 { "input-schmitt-disable", PIN_CONFIG_INPUT_SCHMITT_ENABLE, 0 },
2911 { "input-schmitt-enable", PIN_CONFIG_INPUT_SCHMITT_ENABLE, 1 },
2912 { "slew-rate", PIN_CONFIG_SLEW_RATE, 0 },
2913 };
2914
rockchip_pinconf_prop_name_to_param(const char * property,u32 * default_value)2915 static int rockchip_pinconf_prop_name_to_param(const char *property,
2916 u32 *default_value)
2917 {
2918 const struct pinconf_param *p, *end;
2919
2920 p = rockchip_conf_params;
2921 end = p + sizeof(rockchip_conf_params) / sizeof(struct pinconf_param);
2922
2923 /* See if this pctldev supports this parameter */
2924 for (; p < end; p++) {
2925 if (!strcmp(property, p->property)) {
2926 *default_value = p->default_value;
2927 return p->param;
2928 }
2929 }
2930
2931 *default_value = 0;
2932 return -EPERM;
2933 }
2934
rockchip_pinctrl_set_state(struct udevice * dev,struct udevice * config)2935 static int rockchip_pinctrl_set_state(struct udevice *dev,
2936 struct udevice *config)
2937 {
2938 struct rockchip_pinctrl_priv *priv = dev_get_priv(dev);
2939 struct rockchip_pin_ctrl *ctrl = priv->ctrl;
2940 u32 cells[MAX_ROCKCHIP_PINS_ENTRIES * 4];
2941 u32 bank, pin, mux, conf, arg, default_val;
2942 int ret, count, i;
2943 const char *prop_name;
2944 const void *value;
2945 int prop_len, param;
2946 const u32 *data;
2947 ofnode node;
2948 #if defined(CONFIG_OF_LIVE) && !defined(CONFIG_SPL_BUILD)
2949 const struct device_node *np;
2950 struct property *pp;
2951 #else
2952 int property_offset, pcfg_node;
2953 const void *blob = gd->fdt_blob;
2954 #endif
2955 data = dev_read_prop(config, "rockchip,pins", &count);
2956 if (count < 0) {
2957 debug("%s: bad array size %d\n", __func__, count);
2958 return -EINVAL;
2959 }
2960
2961 count /= sizeof(u32);
2962 if (count > MAX_ROCKCHIP_PINS_ENTRIES * 4) {
2963 debug("%s: unsupported pins array count %d\n",
2964 __func__, count);
2965 return -EINVAL;
2966 }
2967
2968 for (i = 0; i < count; i++)
2969 cells[i] = fdt32_to_cpu(data[i]);
2970
2971 for (i = 0; i < (count >> 2); i++) {
2972 bank = cells[4 * i + 0];
2973 pin = cells[4 * i + 1];
2974 mux = cells[4 * i + 2];
2975 conf = cells[4 * i + 3];
2976
2977 ret = rockchip_verify_config(dev, bank, pin);
2978 if (ret)
2979 return ret;
2980
2981 ret = rockchip_set_mux(&ctrl->pin_banks[bank], pin, mux);
2982 if (ret)
2983 return ret;
2984
2985 node = ofnode_get_by_phandle(conf);
2986 if (!ofnode_valid(node))
2987 return -ENODEV;
2988 #if defined(CONFIG_OF_LIVE) && !defined(CONFIG_SPL_BUILD)
2989 np = ofnode_to_np(node);
2990 for (pp = np->properties; pp; pp = pp->next) {
2991 prop_name = pp->name;
2992 prop_len = pp->length;
2993 value = pp->value;
2994 #else
2995 pcfg_node = ofnode_to_offset(node);
2996 fdt_for_each_property_offset(property_offset, blob, pcfg_node) {
2997 value = fdt_getprop_by_offset(blob, property_offset,
2998 &prop_name, &prop_len);
2999 if (!value)
3000 return -ENOENT;
3001 #endif
3002 param = rockchip_pinconf_prop_name_to_param(prop_name,
3003 &default_val);
3004 if (param < 0)
3005 break;
3006
3007 if (prop_len >= sizeof(fdt32_t))
3008 arg = fdt32_to_cpu(*(fdt32_t *)value);
3009 else
3010 arg = default_val;
3011
3012 ret = rockchip_pinconf_set(&ctrl->pin_banks[bank], pin,
3013 param, arg);
3014 if (ret) {
3015 debug("%s: rockchip_pinconf_set fail: %d\n",
3016 __func__, ret);
3017 return ret;
3018 }
3019 }
3020 }
3021
3022 return 0;
3023 }
3024
3025 static int rockchip_pinctrl_get_pins_count(struct udevice *dev)
3026 {
3027 struct rockchip_pinctrl_priv *priv = dev_get_priv(dev);
3028 struct rockchip_pin_ctrl *ctrl = priv->ctrl;
3029
3030 return ctrl->nr_pins;
3031 }
3032
3033 static struct pinctrl_ops rockchip_pinctrl_ops = {
3034 .get_pins_count = rockchip_pinctrl_get_pins_count,
3035 .set_state = rockchip_pinctrl_set_state,
3036 .get_gpio_mux = rockchip_pinctrl_get_gpio_mux,
3037 };
3038
3039 static const struct rockchip_pin_ctrl rk3308b_pin_ctrl;
3040
3041 /* retrieve the soc specific data */
3042 static const struct rockchip_pin_ctrl *
3043 rockchip_pinctrl_get_soc_data(struct udevice *dev)
3044 {
3045 struct rockchip_pinctrl_priv *priv = dev_get_priv(dev);
3046 const struct rockchip_pin_ctrl *ctrl =
3047 (const struct rockchip_pin_ctrl *)dev_get_driver_data(dev);
3048 struct rockchip_pin_bank *bank;
3049 int grf_offs, pmu_offs, drv_grf_offs, drv_pmu_offs, i, j;
3050 u32 nr_pins;
3051
3052 if (soc_is_rk3308b() || soc_is_rk3308bs())
3053 ctrl = &rk3308b_pin_ctrl;
3054
3055 grf_offs = ctrl->grf_mux_offset;
3056 pmu_offs = ctrl->pmu_mux_offset;
3057 drv_pmu_offs = ctrl->pmu_drv_offset;
3058 drv_grf_offs = ctrl->grf_drv_offset;
3059 bank = ctrl->pin_banks;
3060
3061 /* Ctrl data re-initialize for some Socs */
3062 if (ctrl->ctrl_data_re_init) {
3063 if (ctrl->ctrl_data_re_init(ctrl))
3064 return NULL;
3065 }
3066
3067 nr_pins = 0;
3068 for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
3069 int bank_pins = 0;
3070
3071 bank->priv = priv;
3072 bank->pin_base = nr_pins;
3073 nr_pins += bank->nr_pins;
3074
3075 /* calculate iomux and drv offsets */
3076 for (j = 0; j < 4; j++) {
3077 struct rockchip_iomux *iom = &bank->iomux[j];
3078 struct rockchip_drv *drv = &bank->drv[j];
3079 int inc;
3080
3081 if (bank_pins >= bank->nr_pins)
3082 break;
3083
3084 /* preset iomux offset value, set new start value */
3085 if (iom->offset >= 0) {
3086 if ((iom->type & IOMUX_SOURCE_PMU) || (iom->type & IOMUX_L_SOURCE_PMU))
3087 pmu_offs = iom->offset;
3088 else
3089 grf_offs = iom->offset;
3090 } else { /* set current iomux offset */
3091 iom->offset = ((iom->type & IOMUX_SOURCE_PMU) ||
3092 (iom->type & IOMUX_L_SOURCE_PMU)) ?
3093 pmu_offs : grf_offs;
3094 }
3095
3096 /* preset drv offset value, set new start value */
3097 if (drv->offset >= 0) {
3098 if (iom->type & IOMUX_SOURCE_PMU)
3099 drv_pmu_offs = drv->offset;
3100 else
3101 drv_grf_offs = drv->offset;
3102 } else { /* set current drv offset */
3103 drv->offset = (iom->type & IOMUX_SOURCE_PMU) ?
3104 drv_pmu_offs : drv_grf_offs;
3105 }
3106
3107 debug("bank %d, iomux %d has iom_offset 0x%x drv_offset 0x%x\n",
3108 i, j, iom->offset, drv->offset);
3109
3110 /*
3111 * Increase offset according to iomux width.
3112 * 4bit iomux'es are spread over two registers.
3113 */
3114 inc = (iom->type & (IOMUX_WIDTH_4BIT |
3115 IOMUX_WIDTH_3BIT |
3116 IOMUX_8WIDTH_2BIT)) ? 8 : 4;
3117 if ((iom->type & IOMUX_SOURCE_PMU) || (iom->type & IOMUX_L_SOURCE_PMU))
3118 pmu_offs += inc;
3119 else
3120 grf_offs += inc;
3121
3122 /*
3123 * Increase offset according to drv width.
3124 * 3bit drive-strenth'es are spread over two registers.
3125 */
3126 if ((drv->drv_type == DRV_TYPE_IO_1V8_3V0_AUTO) ||
3127 (drv->drv_type == DRV_TYPE_IO_3V3_ONLY))
3128 inc = 8;
3129 else
3130 inc = 4;
3131
3132 if (iom->type & IOMUX_SOURCE_PMU)
3133 drv_pmu_offs += inc;
3134 else
3135 drv_grf_offs += inc;
3136
3137 bank_pins += 8;
3138 }
3139
3140 /* calculate the per-bank recalced_mask */
3141 for (j = 0; j < ctrl->niomux_recalced; j++) {
3142 int pin = 0;
3143
3144 if (ctrl->iomux_recalced[j].num == bank->bank_num) {
3145 pin = ctrl->iomux_recalced[j].pin;
3146 bank->recalced_mask |= BIT(pin);
3147 }
3148 }
3149
3150 /* calculate the per-bank route_mask */
3151 for (j = 0; j < ctrl->niomux_routes; j++) {
3152 int pin = 0;
3153
3154 if (ctrl->iomux_routes[j].bank_num == bank->bank_num) {
3155 pin = ctrl->iomux_routes[j].pin;
3156 bank->route_mask |= BIT(pin);
3157 }
3158 }
3159 }
3160
3161 WARN_ON(nr_pins != ctrl->nr_pins);
3162
3163 return ctrl;
3164 }
3165
3166 /* SoC data specially handle */
3167
3168 /* rk3308b SoC data initialize */
3169 #define RK3308B_GRF_SOC_CON13 0x608
3170 #define RK3308B_GRF_SOC_CON15 0x610
3171
3172 /* RK3308B_GRF_SOC_CON13 */
3173 #define RK3308B_GRF_I2C3_IOFUNC_SRC_CTRL (BIT(16 + 10) | BIT(10))
3174 #define RK3308B_GRF_GPIO2A3_SEL_SRC_CTRL (BIT(16 + 7) | BIT(7))
3175 #define RK3308B_GRF_GPIO2A2_SEL_SRC_CTRL (BIT(16 + 3) | BIT(3))
3176
3177 /* RK3308B_GRF_SOC_CON15 */
3178 #define RK3308B_GRF_GPIO2C0_SEL_SRC_CTRL (BIT(16 + 11) | BIT(11))
3179 #define RK3308B_GRF_GPIO3B3_SEL_SRC_CTRL (BIT(16 + 7) | BIT(7))
3180 #define RK3308B_GRF_GPIO3B2_SEL_SRC_CTRL (BIT(16 + 3) | BIT(3))
3181
3182 static int rk3308b_soc_data_init(struct rockchip_pinctrl_priv *priv)
3183 {
3184 int ret;
3185
3186 /*
3187 * Enable the special ctrl of selected sources.
3188 */
3189 ret = regmap_write(priv->regmap_base, RK3308B_GRF_SOC_CON13,
3190 RK3308B_GRF_I2C3_IOFUNC_SRC_CTRL |
3191 RK3308B_GRF_GPIO2A3_SEL_SRC_CTRL |
3192 RK3308B_GRF_GPIO2A2_SEL_SRC_CTRL);
3193 if (ret)
3194 return ret;
3195
3196 ret = regmap_write(priv->regmap_base, RK3308B_GRF_SOC_CON15,
3197 RK3308B_GRF_GPIO2C0_SEL_SRC_CTRL |
3198 RK3308B_GRF_GPIO3B3_SEL_SRC_CTRL |
3199 RK3308B_GRF_GPIO3B2_SEL_SRC_CTRL);
3200 if (ret)
3201 return ret;
3202
3203 return 0;
3204 }
3205
3206 static int rockchip_pinctrl_probe(struct udevice *dev)
3207 {
3208 struct rockchip_pinctrl_priv *priv = dev_get_priv(dev);
3209 const struct rockchip_pin_ctrl *ctrl;
3210 struct udevice *syscon;
3211 struct regmap *regmap;
3212 int ret = 0;
3213
3214 /* get rockchip grf syscon phandle */
3215 ret = uclass_get_device_by_phandle(UCLASS_SYSCON, dev, "rockchip,grf",
3216 &syscon);
3217 if (ret) {
3218 debug("unable to find rockchip,grf syscon device (%d)\n", ret);
3219 return ret;
3220 }
3221
3222 /* get grf-reg base address */
3223 regmap = syscon_get_regmap(syscon);
3224 if (!regmap) {
3225 debug("unable to find rockchip grf regmap\n");
3226 return -ENODEV;
3227 }
3228 priv->regmap_base = regmap;
3229
3230 /* option: get pmu-reg base address */
3231 ret = uclass_get_device_by_phandle(UCLASS_SYSCON, dev, "rockchip,pmu",
3232 &syscon);
3233 if (!ret) {
3234 /* get pmugrf-reg base address */
3235 regmap = syscon_get_regmap(syscon);
3236 if (!regmap) {
3237 debug("unable to find rockchip pmu regmap\n");
3238 return -ENODEV;
3239 }
3240 priv->regmap_pmu = regmap;
3241 }
3242
3243 ctrl = rockchip_pinctrl_get_soc_data(dev);
3244 if (!ctrl) {
3245 debug("driver data not available\n");
3246 return -EINVAL;
3247 }
3248
3249 /* Special handle for some Socs */
3250 if (ctrl->soc_data_init) {
3251 ret = ctrl->soc_data_init(priv);
3252 if (ret)
3253 return ret;
3254 }
3255
3256 priv->ctrl = (struct rockchip_pin_ctrl *)ctrl;
3257 return 0;
3258 }
3259
3260 static struct rockchip_pin_bank px30_pin_banks[] = {
3261 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_SOURCE_PMU,
3262 IOMUX_SOURCE_PMU,
3263 IOMUX_SOURCE_PMU,
3264 IOMUX_SOURCE_PMU
3265 ),
3266 PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", IOMUX_WIDTH_4BIT,
3267 IOMUX_WIDTH_4BIT,
3268 IOMUX_WIDTH_4BIT,
3269 IOMUX_WIDTH_4BIT
3270 ),
3271 PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", IOMUX_WIDTH_4BIT,
3272 IOMUX_WIDTH_4BIT,
3273 IOMUX_WIDTH_4BIT,
3274 IOMUX_WIDTH_4BIT
3275 ),
3276 PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", IOMUX_WIDTH_4BIT,
3277 IOMUX_WIDTH_4BIT,
3278 IOMUX_WIDTH_4BIT,
3279 IOMUX_WIDTH_4BIT
3280 ),
3281 };
3282
3283 static const struct rockchip_pin_ctrl px30_pin_ctrl = {
3284 .pin_banks = px30_pin_banks,
3285 .nr_banks = ARRAY_SIZE(px30_pin_banks),
3286 .nr_pins = 128,
3287 .label = "PX30-GPIO",
3288 .type = PX30,
3289 .grf_mux_offset = 0x0,
3290 .pmu_mux_offset = 0x0,
3291 .iomux_routes = px30_mux_route_data,
3292 .niomux_routes = ARRAY_SIZE(px30_mux_route_data),
3293 .pull_calc_reg = px30_calc_pull_reg_and_bit,
3294 .drv_calc_reg = px30_calc_drv_reg_and_bit,
3295 .schmitt_calc_reg = px30_calc_schmitt_reg_and_bit,
3296 .slew_rate_calc_reg = px30_calc_slew_rate_reg_and_bit,
3297 };
3298
3299 static struct rockchip_pin_bank rv1108_pin_banks[] = {
3300 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_SOURCE_PMU,
3301 IOMUX_SOURCE_PMU,
3302 IOMUX_SOURCE_PMU,
3303 IOMUX_SOURCE_PMU),
3304 PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", 0, 0, 0, 0),
3305 PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", 0, 0, 0, 0),
3306 PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", 0, 0, 0, 0),
3307 };
3308
3309 static const struct rockchip_pin_ctrl rv1108_pin_ctrl = {
3310 .pin_banks = rv1108_pin_banks,
3311 .nr_banks = ARRAY_SIZE(rv1108_pin_banks),
3312 .nr_pins = 128,
3313 .label = "RV1108-GPIO",
3314 .type = RV1108,
3315 .grf_mux_offset = 0x10,
3316 .pmu_mux_offset = 0x0,
3317 .iomux_recalced = rv1108_mux_recalced_data,
3318 .niomux_recalced = ARRAY_SIZE(rv1108_mux_recalced_data),
3319 .pull_calc_reg = rv1108_calc_pull_reg_and_bit,
3320 .drv_calc_reg = rv1108_calc_drv_reg_and_bit,
3321 .schmitt_calc_reg = rv1108_calc_schmitt_reg_and_bit,
3322 };
3323
3324 static struct rockchip_pin_bank rv1126_pin_banks[] = {
3325 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0",
3326 IOMUX_WIDTH_4BIT | IOMUX_SOURCE_PMU,
3327 IOMUX_WIDTH_4BIT | IOMUX_SOURCE_PMU,
3328 IOMUX_WIDTH_4BIT | IOMUX_L_SOURCE_PMU,
3329 IOMUX_WIDTH_4BIT),
3330 PIN_BANK_IOMUX_FLAGS_OFFSET(1, 32, "gpio1",
3331 IOMUX_WIDTH_4BIT,
3332 IOMUX_WIDTH_4BIT,
3333 IOMUX_WIDTH_4BIT,
3334 IOMUX_WIDTH_4BIT,
3335 0x10010, 0x10018, 0x10020, 0x10028),
3336 PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2",
3337 IOMUX_WIDTH_4BIT,
3338 IOMUX_WIDTH_4BIT,
3339 IOMUX_WIDTH_4BIT,
3340 IOMUX_WIDTH_4BIT),
3341 PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3",
3342 IOMUX_WIDTH_4BIT,
3343 IOMUX_WIDTH_4BIT,
3344 IOMUX_WIDTH_4BIT,
3345 IOMUX_WIDTH_4BIT),
3346 PIN_BANK_IOMUX_FLAGS(4, 2, "gpio4",
3347 IOMUX_WIDTH_4BIT, 0, 0, 0),
3348 };
3349
3350 static const struct rockchip_pin_ctrl rv1126_pin_ctrl = {
3351 .pin_banks = rv1126_pin_banks,
3352 .nr_banks = ARRAY_SIZE(rv1126_pin_banks),
3353 .nr_pins = 130,
3354 .label = "RV1126-GPIO",
3355 .type = RV1126,
3356 .grf_mux_offset = 0x10004, /* mux offset from GPIO0_D0 */
3357 .pmu_mux_offset = 0x0,
3358 .iomux_routes = rv1126_mux_route_data,
3359 .niomux_routes = ARRAY_SIZE(rv1126_mux_route_data),
3360 .iomux_recalced = rv1126_mux_recalced_data,
3361 .niomux_recalced = ARRAY_SIZE(rv1126_mux_recalced_data),
3362 .pull_calc_reg = rv1126_calc_pull_reg_and_bit,
3363 .drv_calc_reg = rv1126_calc_drv_reg_and_bit,
3364 .schmitt_calc_reg = rv1126_calc_schmitt_reg_and_bit,
3365 };
3366
3367 static struct rockchip_pin_bank rk1808_pin_banks[] = {
3368 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0",
3369 IOMUX_SOURCE_PMU,
3370 IOMUX_SOURCE_PMU,
3371 IOMUX_SOURCE_PMU,
3372 IOMUX_SOURCE_PMU),
3373 PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1",
3374 IOMUX_WIDTH_4BIT,
3375 IOMUX_WIDTH_4BIT,
3376 IOMUX_WIDTH_4BIT,
3377 IOMUX_WIDTH_4BIT),
3378 PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2",
3379 IOMUX_WIDTH_4BIT,
3380 IOMUX_WIDTH_4BIT,
3381 IOMUX_WIDTH_4BIT,
3382 IOMUX_WIDTH_4BIT),
3383 PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3",
3384 IOMUX_WIDTH_4BIT,
3385 IOMUX_WIDTH_4BIT,
3386 IOMUX_WIDTH_4BIT,
3387 IOMUX_WIDTH_4BIT),
3388 PIN_BANK_IOMUX_FLAGS(4, 32, "gpio4",
3389 IOMUX_WIDTH_4BIT,
3390 IOMUX_WIDTH_4BIT,
3391 IOMUX_WIDTH_4BIT,
3392 IOMUX_WIDTH_4BIT),
3393 };
3394
3395 static const struct rockchip_pin_ctrl rk1808_pin_ctrl = {
3396 .pin_banks = rk1808_pin_banks,
3397 .nr_banks = ARRAY_SIZE(rk1808_pin_banks),
3398 .nr_pins = 160,
3399 .label = "RK1808-GPIO",
3400 .type = RK1808,
3401 .iomux_routes = rk1808_mux_route_data,
3402 .niomux_routes = ARRAY_SIZE(rk1808_mux_route_data),
3403 .grf_mux_offset = 0x0,
3404 .pmu_mux_offset = 0x0,
3405 .pull_calc_reg = rk1808_calc_pull_reg_and_bit,
3406 .drv_calc_reg = rk1808_calc_drv_reg_and_bit,
3407 .schmitt_calc_reg = rk1808_calc_schmitt_reg_and_bit,
3408 };
3409
3410 static struct rockchip_pin_bank rk2928_pin_banks[] = {
3411 PIN_BANK(0, 32, "gpio0"),
3412 PIN_BANK(1, 32, "gpio1"),
3413 PIN_BANK(2, 32, "gpio2"),
3414 PIN_BANK(3, 32, "gpio3"),
3415 };
3416
3417 static const struct rockchip_pin_ctrl rk2928_pin_ctrl = {
3418 .pin_banks = rk2928_pin_banks,
3419 .nr_banks = ARRAY_SIZE(rk2928_pin_banks),
3420 .nr_pins = 128,
3421 .label = "RK2928-GPIO",
3422 .type = RK2928,
3423 .grf_mux_offset = 0xa8,
3424 .pull_calc_reg = rk2928_calc_pull_reg_and_bit,
3425 };
3426
3427 static struct rockchip_pin_bank rk3036_pin_banks[] = {
3428 PIN_BANK(0, 32, "gpio0"),
3429 PIN_BANK(1, 32, "gpio1"),
3430 PIN_BANK(2, 32, "gpio2"),
3431 };
3432
3433 static const struct rockchip_pin_ctrl rk3036_pin_ctrl = {
3434 .pin_banks = rk3036_pin_banks,
3435 .nr_banks = ARRAY_SIZE(rk3036_pin_banks),
3436 .nr_pins = 96,
3437 .label = "RK3036-GPIO",
3438 .type = RK2928,
3439 .grf_mux_offset = 0xa8,
3440 .pull_calc_reg = rk2928_calc_pull_reg_and_bit,
3441 };
3442
3443 static struct rockchip_pin_bank rk3066a_pin_banks[] = {
3444 PIN_BANK(0, 32, "gpio0"),
3445 PIN_BANK(1, 32, "gpio1"),
3446 PIN_BANK(2, 32, "gpio2"),
3447 PIN_BANK(3, 32, "gpio3"),
3448 PIN_BANK(4, 32, "gpio4"),
3449 PIN_BANK(6, 16, "gpio6"),
3450 };
3451
3452 static const struct rockchip_pin_ctrl rk3066a_pin_ctrl = {
3453 .pin_banks = rk3066a_pin_banks,
3454 .nr_banks = ARRAY_SIZE(rk3066a_pin_banks),
3455 .nr_pins = 176,
3456 .label = "RK3066a-GPIO",
3457 .type = RK2928,
3458 .grf_mux_offset = 0xa8,
3459 .pull_calc_reg = rk2928_calc_pull_reg_and_bit,
3460 };
3461
3462 static struct rockchip_pin_bank rk3066b_pin_banks[] = {
3463 PIN_BANK(0, 32, "gpio0"),
3464 PIN_BANK(1, 32, "gpio1"),
3465 PIN_BANK(2, 32, "gpio2"),
3466 PIN_BANK(3, 32, "gpio3"),
3467 };
3468
3469 static const struct rockchip_pin_ctrl rk3066b_pin_ctrl = {
3470 .pin_banks = rk3066b_pin_banks,
3471 .nr_banks = ARRAY_SIZE(rk3066b_pin_banks),
3472 .nr_pins = 128,
3473 .label = "RK3066b-GPIO",
3474 .type = RK3066B,
3475 .grf_mux_offset = 0x60,
3476 };
3477
3478 static struct rockchip_pin_bank rk3128_pin_banks[] = {
3479 PIN_BANK(0, 32, "gpio0"),
3480 PIN_BANK(1, 32, "gpio1"),
3481 PIN_BANK(2, 32, "gpio2"),
3482 PIN_BANK(3, 32, "gpio3"),
3483 };
3484
3485 static const struct rockchip_pin_ctrl rk3128_pin_ctrl = {
3486 .pin_banks = rk3128_pin_banks,
3487 .nr_banks = ARRAY_SIZE(rk3128_pin_banks),
3488 .nr_pins = 128,
3489 .label = "RK3128-GPIO",
3490 .type = RK3128,
3491 .grf_mux_offset = 0xa8,
3492 .iomux_recalced = rk3128_mux_recalced_data,
3493 .niomux_recalced = ARRAY_SIZE(rk3128_mux_recalced_data),
3494 .iomux_routes = rk3128_mux_route_data,
3495 .niomux_routes = ARRAY_SIZE(rk3128_mux_route_data),
3496 .pull_calc_reg = rk3128_calc_pull_reg_and_bit,
3497 };
3498
3499 static struct rockchip_pin_bank rk3188_pin_banks[] = {
3500 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_GPIO_ONLY, 0, 0, 0),
3501 PIN_BANK(1, 32, "gpio1"),
3502 PIN_BANK(2, 32, "gpio2"),
3503 PIN_BANK(3, 32, "gpio3"),
3504 };
3505
3506 static const struct rockchip_pin_ctrl rk3188_pin_ctrl = {
3507 .pin_banks = rk3188_pin_banks,
3508 .nr_banks = ARRAY_SIZE(rk3188_pin_banks),
3509 .nr_pins = 128,
3510 .label = "RK3188-GPIO",
3511 .type = RK3188,
3512 .grf_mux_offset = 0x60,
3513 .pull_calc_reg = rk3188_calc_pull_reg_and_bit,
3514 };
3515
3516 static struct rockchip_pin_bank rk3228_pin_banks[] = {
3517 PIN_BANK(0, 32, "gpio0"),
3518 PIN_BANK(1, 32, "gpio1"),
3519 PIN_BANK(2, 32, "gpio2"),
3520 PIN_BANK(3, 32, "gpio3"),
3521 };
3522
3523 static const struct rockchip_pin_ctrl rk3228_pin_ctrl = {
3524 .pin_banks = rk3228_pin_banks,
3525 .nr_banks = ARRAY_SIZE(rk3228_pin_banks),
3526 .nr_pins = 128,
3527 .label = "RK3228-GPIO",
3528 .type = RK3288,
3529 .grf_mux_offset = 0x0,
3530 .iomux_routes = rk3228_mux_route_data,
3531 .niomux_routes = ARRAY_SIZE(rk3228_mux_route_data),
3532 .pull_calc_reg = rk3228_calc_pull_reg_and_bit,
3533 .drv_calc_reg = rk3228_calc_drv_reg_and_bit,
3534 };
3535
3536 static struct rockchip_pin_bank rk3288_pin_banks[] = {
3537 PIN_BANK_IOMUX_DRV_PULL_FLAGS(0, 24, "gpio0",
3538 IOMUX_SOURCE_PMU | IOMUX_WRITABLE_32BIT,
3539 IOMUX_SOURCE_PMU | IOMUX_WRITABLE_32BIT,
3540 IOMUX_SOURCE_PMU | IOMUX_WRITABLE_32BIT,
3541 IOMUX_UNROUTED,
3542 DRV_TYPE_WRITABLE_32BIT,
3543 DRV_TYPE_WRITABLE_32BIT,
3544 DRV_TYPE_WRITABLE_32BIT,
3545 0,
3546 PULL_TYPE_WRITABLE_32BIT,
3547 PULL_TYPE_WRITABLE_32BIT,
3548 PULL_TYPE_WRITABLE_32BIT,
3549 0
3550 ),
3551 PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", IOMUX_UNROUTED,
3552 IOMUX_UNROUTED,
3553 IOMUX_UNROUTED,
3554 0
3555 ),
3556 PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", 0, 0, 0, IOMUX_UNROUTED),
3557 PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", 0, 0, 0, IOMUX_WIDTH_4BIT),
3558 PIN_BANK_IOMUX_FLAGS(4, 32, "gpio4", IOMUX_WIDTH_4BIT,
3559 IOMUX_WIDTH_4BIT,
3560 0,
3561 0
3562 ),
3563 PIN_BANK_IOMUX_FLAGS(5, 32, "gpio5", IOMUX_UNROUTED,
3564 0,
3565 0,
3566 IOMUX_UNROUTED
3567 ),
3568 PIN_BANK_IOMUX_FLAGS(6, 32, "gpio6", 0, 0, 0, IOMUX_UNROUTED),
3569 PIN_BANK_IOMUX_FLAGS(7, 32, "gpio7", 0,
3570 0,
3571 IOMUX_WIDTH_4BIT,
3572 IOMUX_UNROUTED
3573 ),
3574 PIN_BANK(8, 16, "gpio8"),
3575 };
3576
3577 static const struct rockchip_pin_ctrl rk3288_pin_ctrl = {
3578 .pin_banks = rk3288_pin_banks,
3579 .nr_banks = ARRAY_SIZE(rk3288_pin_banks),
3580 .nr_pins = 264,
3581 .label = "RK3288-GPIO",
3582 .type = RK3288,
3583 .grf_mux_offset = 0x0,
3584 .pmu_mux_offset = 0x84,
3585 .iomux_routes = rk3288_mux_route_data,
3586 .niomux_routes = ARRAY_SIZE(rk3288_mux_route_data),
3587 .pull_calc_reg = rk3288_calc_pull_reg_and_bit,
3588 .drv_calc_reg = rk3288_calc_drv_reg_and_bit,
3589 };
3590
3591 static struct rockchip_pin_bank rk3308_pin_banks[] = {
3592 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_8WIDTH_2BIT,
3593 IOMUX_8WIDTH_2BIT,
3594 IOMUX_8WIDTH_2BIT,
3595 IOMUX_8WIDTH_2BIT),
3596 PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", IOMUX_8WIDTH_2BIT,
3597 IOMUX_8WIDTH_2BIT,
3598 IOMUX_8WIDTH_2BIT,
3599 IOMUX_8WIDTH_2BIT),
3600 PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", IOMUX_8WIDTH_2BIT,
3601 IOMUX_8WIDTH_2BIT,
3602 IOMUX_8WIDTH_2BIT,
3603 IOMUX_8WIDTH_2BIT),
3604 PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", IOMUX_8WIDTH_2BIT,
3605 IOMUX_8WIDTH_2BIT,
3606 IOMUX_8WIDTH_2BIT,
3607 IOMUX_8WIDTH_2BIT),
3608 PIN_BANK_IOMUX_FLAGS(4, 32, "gpio4", IOMUX_8WIDTH_2BIT,
3609 IOMUX_8WIDTH_2BIT,
3610 IOMUX_8WIDTH_2BIT,
3611 IOMUX_8WIDTH_2BIT),
3612 };
3613
3614 static struct rockchip_pin_ctrl rk3308_pin_ctrl = {
3615 .pin_banks = rk3308_pin_banks,
3616 .nr_banks = ARRAY_SIZE(rk3308_pin_banks),
3617 .nr_pins = 160,
3618 .label = "RK3308-GPIO",
3619 .type = RK3308,
3620 .grf_mux_offset = 0x0,
3621 .iomux_recalced = rk3308_mux_recalced_data,
3622 .niomux_recalced = ARRAY_SIZE(rk3308_mux_recalced_data),
3623 .iomux_routes = rk3308_mux_route_data,
3624 .niomux_routes = ARRAY_SIZE(rk3308_mux_route_data),
3625 .pull_calc_reg = rk3308_calc_pull_reg_and_bit,
3626 .drv_calc_reg = rk3308_calc_drv_reg_and_bit,
3627 .schmitt_calc_reg = rk3308_calc_schmitt_reg_and_bit,
3628 };
3629
3630 static const struct rockchip_pin_ctrl rk3308b_pin_ctrl = {
3631 .pin_banks = rk3308_pin_banks,
3632 .nr_banks = ARRAY_SIZE(rk3308_pin_banks),
3633 .nr_pins = 160,
3634 .label = "RK3308-GPIO",
3635 .type = RK3308,
3636 .grf_mux_offset = 0x0,
3637 .iomux_recalced = rk3308b_mux_recalced_data,
3638 .niomux_recalced = ARRAY_SIZE(rk3308b_mux_recalced_data),
3639 .iomux_routes = rk3308b_mux_route_data,
3640 .niomux_routes = ARRAY_SIZE(rk3308b_mux_route_data),
3641 .soc_data_init = rk3308b_soc_data_init,
3642 .pull_calc_reg = rk3308_calc_pull_reg_and_bit,
3643 .drv_calc_reg = rk3308_calc_drv_reg_and_bit,
3644 .schmitt_calc_reg = rk3308_calc_schmitt_reg_and_bit,
3645 };
3646
3647 static struct rockchip_pin_bank rk3328_pin_banks[] = {
3648 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", 0, 0, 0, 0),
3649 PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", 0, 0, 0, 0),
3650 PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", 0,
3651 IOMUX_WIDTH_3BIT,
3652 IOMUX_WIDTH_3BIT,
3653 0),
3654 PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3",
3655 IOMUX_WIDTH_3BIT,
3656 IOMUX_WIDTH_3BIT,
3657 0,
3658 0),
3659 };
3660
3661 static const struct rockchip_pin_ctrl rk3328_pin_ctrl = {
3662 .pin_banks = rk3328_pin_banks,
3663 .nr_banks = ARRAY_SIZE(rk3328_pin_banks),
3664 .nr_pins = 128,
3665 .label = "RK3328-GPIO",
3666 .type = RK3288,
3667 .grf_mux_offset = 0x0,
3668 .iomux_recalced = rk3328_mux_recalced_data,
3669 .niomux_recalced = ARRAY_SIZE(rk3328_mux_recalced_data),
3670 .iomux_routes = rk3328_mux_route_data,
3671 .niomux_routes = ARRAY_SIZE(rk3328_mux_route_data),
3672 .pull_calc_reg = rk3228_calc_pull_reg_and_bit,
3673 .drv_calc_reg = rk3228_calc_drv_reg_and_bit,
3674 .schmitt_calc_reg = rk3328_calc_schmitt_reg_and_bit,
3675 };
3676
3677 static struct rockchip_pin_bank rk3368_pin_banks[] = {
3678 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_SOURCE_PMU,
3679 IOMUX_SOURCE_PMU,
3680 IOMUX_SOURCE_PMU,
3681 IOMUX_SOURCE_PMU
3682 ),
3683 PIN_BANK(1, 32, "gpio1"),
3684 PIN_BANK(2, 32, "gpio2"),
3685 PIN_BANK(3, 32, "gpio3"),
3686 };
3687
3688 static const struct rockchip_pin_ctrl rk3368_pin_ctrl = {
3689 .pin_banks = rk3368_pin_banks,
3690 .nr_banks = ARRAY_SIZE(rk3368_pin_banks),
3691 .nr_pins = 128,
3692 .label = "RK3368-GPIO",
3693 .type = RK3368,
3694 .grf_mux_offset = 0x0,
3695 .pmu_mux_offset = 0x0,
3696 .pull_calc_reg = rk3368_calc_pull_reg_and_bit,
3697 .drv_calc_reg = rk3368_calc_drv_reg_and_bit,
3698 };
3699
3700 static struct rockchip_pin_bank rk3399_pin_banks[] = {
3701 PIN_BANK_IOMUX_FLAGS_DRV_FLAGS_OFFSET_PULL_FLAGS(0, 32, "gpio0",
3702 IOMUX_SOURCE_PMU,
3703 IOMUX_SOURCE_PMU,
3704 IOMUX_SOURCE_PMU,
3705 IOMUX_SOURCE_PMU,
3706 DRV_TYPE_IO_1V8_ONLY,
3707 DRV_TYPE_IO_1V8_ONLY,
3708 DRV_TYPE_IO_DEFAULT,
3709 DRV_TYPE_IO_DEFAULT,
3710 0x80,
3711 0x88,
3712 -1,
3713 -1,
3714 PULL_TYPE_IO_1V8_ONLY,
3715 PULL_TYPE_IO_1V8_ONLY,
3716 PULL_TYPE_IO_DEFAULT,
3717 PULL_TYPE_IO_DEFAULT
3718 ),
3719 PIN_BANK_IOMUX_DRV_FLAGS_OFFSET(1, 32, "gpio1", IOMUX_SOURCE_PMU,
3720 IOMUX_SOURCE_PMU,
3721 IOMUX_SOURCE_PMU,
3722 IOMUX_SOURCE_PMU,
3723 DRV_TYPE_IO_1V8_OR_3V0,
3724 DRV_TYPE_IO_1V8_OR_3V0,
3725 DRV_TYPE_IO_1V8_OR_3V0,
3726 DRV_TYPE_IO_1V8_OR_3V0,
3727 0xa0,
3728 0xa8,
3729 0xb0,
3730 0xb8
3731 ),
3732 PIN_BANK_DRV_FLAGS_PULL_FLAGS(2, 32, "gpio2", DRV_TYPE_IO_1V8_OR_3V0,
3733 DRV_TYPE_IO_1V8_OR_3V0,
3734 DRV_TYPE_IO_1V8_ONLY,
3735 DRV_TYPE_IO_1V8_ONLY,
3736 PULL_TYPE_IO_DEFAULT,
3737 PULL_TYPE_IO_DEFAULT,
3738 PULL_TYPE_IO_1V8_ONLY,
3739 PULL_TYPE_IO_1V8_ONLY
3740 ),
3741 PIN_BANK_DRV_FLAGS(3, 32, "gpio3", DRV_TYPE_IO_3V3_ONLY,
3742 DRV_TYPE_IO_3V3_ONLY,
3743 DRV_TYPE_IO_3V3_ONLY,
3744 DRV_TYPE_IO_1V8_OR_3V0
3745 ),
3746 PIN_BANK_DRV_FLAGS(4, 32, "gpio4", DRV_TYPE_IO_1V8_OR_3V0,
3747 DRV_TYPE_IO_1V8_3V0_AUTO,
3748 DRV_TYPE_IO_1V8_OR_3V0,
3749 DRV_TYPE_IO_1V8_OR_3V0
3750 ),
3751 };
3752
3753 static const struct rockchip_pin_ctrl rk3399_pin_ctrl = {
3754 .pin_banks = rk3399_pin_banks,
3755 .nr_banks = ARRAY_SIZE(rk3399_pin_banks),
3756 .nr_pins = 160,
3757 .label = "RK3399-GPIO",
3758 .type = RK3399,
3759 .grf_mux_offset = 0xe000,
3760 .pmu_mux_offset = 0x0,
3761 .grf_drv_offset = 0xe100,
3762 .pmu_drv_offset = 0x80,
3763 .iomux_routes = rk3399_mux_route_data,
3764 .niomux_routes = ARRAY_SIZE(rk3399_mux_route_data),
3765 .pull_calc_reg = rk3399_calc_pull_reg_and_bit,
3766 .drv_calc_reg = rk3399_calc_drv_reg_and_bit,
3767 };
3768
3769 static const struct udevice_id rockchip_pinctrl_dt_match[] = {
3770 { .compatible = "rockchip,px30-pinctrl",
3771 .data = (ulong)&px30_pin_ctrl },
3772 { .compatible = "rockchip,rv1108-pinctrl",
3773 .data = (ulong)&rv1108_pin_ctrl },
3774 { .compatible = "rockchip,rv1126-pinctrl-legency",
3775 .data = (ulong)&rv1126_pin_ctrl },
3776 { .compatible = "rockchip,rk1808-pinctrl",
3777 .data = (ulong)&rk1808_pin_ctrl },
3778 { .compatible = "rockchip,rk2928-pinctrl",
3779 .data = (ulong)&rk2928_pin_ctrl },
3780 { .compatible = "rockchip,rk3036-pinctrl",
3781 .data = (ulong)&rk3036_pin_ctrl },
3782 { .compatible = "rockchip,rk3066a-pinctrl",
3783 .data = (ulong)&rk3066a_pin_ctrl },
3784 { .compatible = "rockchip,rk3066b-pinctrl",
3785 .data = (ulong)&rk3066b_pin_ctrl },
3786 { .compatible = "rockchip,rk3128-pinctrl",
3787 .data = (ulong)&rk3128_pin_ctrl },
3788 { .compatible = "rockchip,rk3188-pinctrl",
3789 .data = (ulong)&rk3188_pin_ctrl },
3790 { .compatible = "rockchip,rk3228-pinctrl",
3791 .data = (ulong)&rk3228_pin_ctrl },
3792 { .compatible = "rockchip,rk3288-pinctrl",
3793 .data = (ulong)&rk3288_pin_ctrl },
3794 { .compatible = "rockchip,rk3308-pinctrl",
3795 .data = (ulong)&rk3308_pin_ctrl },
3796 { .compatible = "rockchip,rk3328-pinctrl",
3797 .data = (ulong)&rk3328_pin_ctrl },
3798 { .compatible = "rockchip,rk3368-pinctrl",
3799 .data = (ulong)&rk3368_pin_ctrl },
3800 { .compatible = "rockchip,rk3399-pinctrl",
3801 .data = (ulong)&rk3399_pin_ctrl },
3802 {},
3803 };
3804
3805 U_BOOT_DRIVER(pinctrl_rockchip) = {
3806 .name = "rockchip_pinctrl",
3807 .id = UCLASS_PINCTRL,
3808 .of_match = rockchip_pinctrl_dt_match,
3809 .priv_auto_alloc_size = sizeof(struct rockchip_pinctrl_priv),
3810 .ops = &rockchip_pinctrl_ops,
3811 #if !CONFIG_IS_ENABLED(OF_PLATDATA)
3812 .bind = dm_scan_fdt_dev,
3813 #endif
3814 .probe = rockchip_pinctrl_probe,
3815 };
3816