1 /*
2 * Copyright (c) 2016, NVIDIA CORPORATION.
3 *
4 * SPDX-License-Identifier: GPL-2.0
5 *
6 * Portions based on U-Boot's rtl8169.c.
7 */
8
9 /*
10 * This driver supports the Synopsys Designware Ethernet QOS (Quality Of
11 * Service) IP block. The IP supports multiple options for bus type, clocking/
12 * reset structure, and feature list.
13 *
14 * The driver is written such that generic core logic is kept separate from
15 * configuration-specific logic. Code that interacts with configuration-
16 * specific resources is split out into separate functions to avoid polluting
17 * common code. If/when this driver is enhanced to support multiple
18 * configurations, the core code should be adapted to call all configuration-
19 * specific functions through function pointers, with the definition of those
20 * function pointers being supplied by struct udevice_id eqos_ids[]'s .data
21 * field.
22 *
23 * The following configurations are currently supported:
24 * tegra186:
25 * NVIDIA's Tegra186 chip. This configuration uses an AXI master/DMA bus, an
26 * AHB slave/register bus, contains the DMA, MTL, and MAC sub-blocks, and
27 * supports a single RGMII PHY. This configuration also has SW control over
28 * all clock and reset signals to the HW block.
29 */
30 #include <common.h>
31 #include <clk.h>
32 #include <dm.h>
33 #include <errno.h>
34 #include <memalign.h>
35 #include <miiphy.h>
36 #include <net.h>
37 #include <netdev.h>
38 #include <phy.h>
39 #include <reset.h>
40 #include <wait_bit.h>
41 #include <asm/io.h>
42 #include <eth_phy.h>
43 #ifdef CONFIG_ARCH_IMX8M
44 #include <asm/arch/clock.h>
45 #include <asm/mach-imx/sys_proto.h>
46 #endif
47 #include "dwc_eth_qos.h"
48
49 /* Core registers */
50
51 #define EQOS_MAC_REGS_BASE 0x000
52 struct eqos_mac_regs {
53 uint32_t configuration; /* 0x000 */
54 uint32_t unused_004[(0x070 - 0x004) / 4]; /* 0x004 */
55 uint32_t q0_tx_flow_ctrl; /* 0x070 */
56 uint32_t unused_070[(0x090 - 0x074) / 4]; /* 0x074 */
57 uint32_t rx_flow_ctrl; /* 0x090 */
58 uint32_t unused_094; /* 0x094 */
59 uint32_t txq_prty_map0; /* 0x098 */
60 uint32_t unused_09c; /* 0x09c */
61 uint32_t rxq_ctrl0; /* 0x0a0 */
62 uint32_t unused_0a4; /* 0x0a4 */
63 uint32_t rxq_ctrl2; /* 0x0a8 */
64 uint32_t unused_0ac[(0x0dc - 0x0ac) / 4]; /* 0x0ac */
65 uint32_t us_tic_counter; /* 0x0dc */
66 uint32_t unused_0e0[(0x11c - 0x0e0) / 4]; /* 0x0e0 */
67 uint32_t hw_feature0; /* 0x11c */
68 uint32_t hw_feature1; /* 0x120 */
69 uint32_t hw_feature2; /* 0x124 */
70 uint32_t unused_128[(0x200 - 0x128) / 4]; /* 0x128 */
71 uint32_t mdio_address; /* 0x200 */
72 uint32_t mdio_data; /* 0x204 */
73 uint32_t unused_208[(0x300 - 0x208) / 4]; /* 0x208 */
74 uint32_t address0_high; /* 0x300 */
75 uint32_t address0_low; /* 0x304 */
76 };
77
78 #define EQOS_MAC_CONFIGURATION_GPSLCE BIT(23)
79 #define EQOS_MAC_CONFIGURATION_CST BIT(21)
80 #define EQOS_MAC_CONFIGURATION_ACS BIT(20)
81 #define EQOS_MAC_CONFIGURATION_WD BIT(19)
82 #define EQOS_MAC_CONFIGURATION_JD BIT(17)
83 #define EQOS_MAC_CONFIGURATION_JE BIT(16)
84 #define EQOS_MAC_CONFIGURATION_PS BIT(15)
85 #define EQOS_MAC_CONFIGURATION_FES BIT(14)
86 #define EQOS_MAC_CONFIGURATION_DM BIT(13)
87 #define EQOS_MAC_CONFIGURATION_LM BIT(12)
88 #define EQOS_MAC_CONFIGURATION_TE BIT(1)
89 #define EQOS_MAC_CONFIGURATION_RE BIT(0)
90
91 #define EQOS_MAC_Q0_TX_FLOW_CTRL_PT_SHIFT 16
92 #define EQOS_MAC_Q0_TX_FLOW_CTRL_PT_MASK 0xffff
93 #define EQOS_MAC_Q0_TX_FLOW_CTRL_TFE BIT(1)
94
95 #define EQOS_MAC_RX_FLOW_CTRL_RFE BIT(0)
96
97 #define EQOS_MAC_TXQ_PRTY_MAP0_PSTQ0_SHIFT 0
98 #define EQOS_MAC_TXQ_PRTY_MAP0_PSTQ0_MASK 0xff
99
100 #define EQOS_MAC_RXQ_CTRL0_RXQ0EN_SHIFT 0
101 #define EQOS_MAC_RXQ_CTRL0_RXQ0EN_MASK 3
102
103 #define EQOS_MAC_RXQ_CTRL2_PSRQ0_SHIFT 0
104 #define EQOS_MAC_RXQ_CTRL2_PSRQ0_MASK 0xff
105
106 #define EQOS_MAC_HW_FEATURE0_MMCSEL_SHIFT 8
107 #define EQOS_MAC_HW_FEATURE0_HDSEL_SHIFT 2
108 #define EQOS_MAC_HW_FEATURE0_GMIISEL_SHIFT 1
109 #define EQOS_MAC_HW_FEATURE0_MIISEL_SHIFT 0
110
111 #define EQOS_MAC_HW_FEATURE1_TXFIFOSIZE_SHIFT 6
112 #define EQOS_MAC_HW_FEATURE1_TXFIFOSIZE_MASK 0x1f
113 #define EQOS_MAC_HW_FEATURE1_RXFIFOSIZE_SHIFT 0
114 #define EQOS_MAC_HW_FEATURE1_RXFIFOSIZE_MASK 0x1f
115
116 #define EQOS_MAC_HW_FEATURE3_ASP_SHIFT 28
117 #define EQOS_MAC_HW_FEATURE3_ASP_MASK 0x3
118
119 #define EQOS_MAC_MDIO_ADDRESS_PA_SHIFT 21
120 #define EQOS_MAC_MDIO_ADDRESS_RDA_SHIFT 16
121 #define EQOS_MAC_MDIO_ADDRESS_CR_SHIFT 8
122 #define EQOS_MAC_MDIO_ADDRESS_SKAP BIT(4)
123 #define EQOS_MAC_MDIO_ADDRESS_GOC_SHIFT 2
124 #define EQOS_MAC_MDIO_ADDRESS_GOC_READ 3
125 #define EQOS_MAC_MDIO_ADDRESS_GOC_WRITE 1
126 #define EQOS_MAC_MDIO_ADDRESS_C45E BIT(1)
127 #define EQOS_MAC_MDIO_ADDRESS_GB BIT(0)
128
129 #define EQOS_MAC_MDIO_DATA_GD_MASK 0xffff
130
131 #define EQOS_MTL_REGS_BASE 0xd00
132 struct eqos_mtl_regs {
133 uint32_t txq0_operation_mode; /* 0xd00 */
134 uint32_t unused_d04; /* 0xd04 */
135 uint32_t txq0_debug; /* 0xd08 */
136 uint32_t unused_d0c[(0xd18 - 0xd0c) / 4]; /* 0xd0c */
137 uint32_t txq0_quantum_weight; /* 0xd18 */
138 uint32_t unused_d1c[(0xd30 - 0xd1c) / 4]; /* 0xd1c */
139 uint32_t rxq0_operation_mode; /* 0xd30 */
140 uint32_t unused_d34; /* 0xd34 */
141 uint32_t rxq0_debug; /* 0xd38 */
142 };
143
144 #define EQOS_MTL_TXQ0_OPERATION_MODE_TQS_SHIFT 16
145 #define EQOS_MTL_TXQ0_OPERATION_MODE_TQS_MASK 0x1ff
146 #define EQOS_MTL_TXQ0_OPERATION_MODE_TXQEN_SHIFT 2
147 #define EQOS_MTL_TXQ0_OPERATION_MODE_TXQEN_MASK 3
148 #define EQOS_MTL_TXQ0_OPERATION_MODE_TXQEN_ENABLED 2
149 #define EQOS_MTL_TXQ0_OPERATION_MODE_TSF BIT(1)
150 #define EQOS_MTL_TXQ0_OPERATION_MODE_FTQ BIT(0)
151
152 #define EQOS_MTL_TXQ0_DEBUG_TXQSTS BIT(4)
153 #define EQOS_MTL_TXQ0_DEBUG_TRCSTS_SHIFT 1
154 #define EQOS_MTL_TXQ0_DEBUG_TRCSTS_MASK 3
155
156 #define EQOS_MTL_RXQ0_OPERATION_MODE_RQS_SHIFT 20
157 #define EQOS_MTL_RXQ0_OPERATION_MODE_RQS_MASK 0x3ff
158 #define EQOS_MTL_RXQ0_OPERATION_MODE_RFD_SHIFT 14
159 #define EQOS_MTL_RXQ0_OPERATION_MODE_RFD_MASK 0x3f
160 #define EQOS_MTL_RXQ0_OPERATION_MODE_RFA_SHIFT 8
161 #define EQOS_MTL_RXQ0_OPERATION_MODE_RFA_MASK 0x3f
162 #define EQOS_MTL_RXQ0_OPERATION_MODE_EHFC BIT(7)
163 #define EQOS_MTL_RXQ0_OPERATION_MODE_RSF BIT(5)
164 #define EQOS_MTL_RXQ0_OPERATION_MODE_FEP BIT(4)
165 #define EQOS_MTL_RXQ0_OPERATION_MODE_FUP BIT(3)
166
167 #define EQOS_MTL_RXQ0_DEBUG_PRXQ_SHIFT 16
168 #define EQOS_MTL_RXQ0_DEBUG_PRXQ_MASK 0x7fff
169 #define EQOS_MTL_RXQ0_DEBUG_RXQSTS_SHIFT 4
170 #define EQOS_MTL_RXQ0_DEBUG_RXQSTS_MASK 3
171
172 #define EQOS_DMA_REGS_BASE 0x1000
173 struct eqos_dma_regs {
174 uint32_t mode; /* 0x1000 */
175 uint32_t sysbus_mode; /* 0x1004 */
176 uint32_t unused_1008[(0x1100 - 0x1008) / 4]; /* 0x1008 */
177 uint32_t ch0_control; /* 0x1100 */
178 uint32_t ch0_tx_control; /* 0x1104 */
179 uint32_t ch0_rx_control; /* 0x1108 */
180 uint32_t unused_110c; /* 0x110c */
181 uint32_t ch0_txdesc_list_haddress; /* 0x1110 */
182 uint32_t ch0_txdesc_list_address; /* 0x1114 */
183 uint32_t ch0_rxdesc_list_haddress; /* 0x1118 */
184 uint32_t ch0_rxdesc_list_address; /* 0x111c */
185 uint32_t ch0_txdesc_tail_pointer; /* 0x1120 */
186 uint32_t unused_1124; /* 0x1124 */
187 uint32_t ch0_rxdesc_tail_pointer; /* 0x1128 */
188 uint32_t ch0_txdesc_ring_length; /* 0x112c */
189 uint32_t ch0_rxdesc_ring_length; /* 0x1130 */
190 };
191
192 #define EQOS_DMA_MODE_SWR BIT(0)
193
194 #define EQOS_DMA_SYSBUS_MODE_RD_OSR_LMT_SHIFT 16
195 #define EQOS_DMA_SYSBUS_MODE_RD_OSR_LMT_MASK 0xf
196 #define EQOS_DMA_SYSBUS_MODE_EAME BIT(11)
197 #define EQOS_DMA_SYSBUS_MODE_BLEN16 BIT(3)
198 #define EQOS_DMA_SYSBUS_MODE_BLEN8 BIT(2)
199 #define EQOS_DMA_SYSBUS_MODE_BLEN4 BIT(1)
200
201 #define EQOS_DMA_CH0_CONTROL_PBLX8 BIT(16)
202
203 #define EQOS_DMA_CH0_TX_CONTROL_TXPBL_SHIFT 16
204 #define EQOS_DMA_CH0_TX_CONTROL_TXPBL_MASK 0x3f
205 #define EQOS_DMA_CH0_TX_CONTROL_OSP BIT(4)
206 #define EQOS_DMA_CH0_TX_CONTROL_ST BIT(0)
207
208 #define EQOS_DMA_CH0_RX_CONTROL_RXPBL_SHIFT 16
209 #define EQOS_DMA_CH0_RX_CONTROL_RXPBL_MASK 0x3f
210 #define EQOS_DMA_CH0_RX_CONTROL_RBSZ_SHIFT 1
211 #define EQOS_DMA_CH0_RX_CONTROL_RBSZ_MASK 0x3fff
212 #define EQOS_DMA_CH0_RX_CONTROL_SR BIT(0)
213
214 /* These registers are Tegra186-specific */
215 #define EQOS_TEGRA186_REGS_BASE 0x8800
216 struct eqos_tegra186_regs {
217 uint32_t sdmemcomppadctrl; /* 0x8800 */
218 uint32_t auto_cal_config; /* 0x8804 */
219 uint32_t unused_8808; /* 0x8808 */
220 uint32_t auto_cal_status; /* 0x880c */
221 };
222
223 #define EQOS_SDMEMCOMPPADCTRL_PAD_E_INPUT_OR_E_PWRD BIT(31)
224
225 #define EQOS_AUTO_CAL_CONFIG_START BIT(31)
226 #define EQOS_AUTO_CAL_CONFIG_ENABLE BIT(29)
227
228 #define EQOS_AUTO_CAL_STATUS_ACTIVE BIT(31)
229
230 /* Descriptors */
231
232 #define EQOS_DESCRIPTOR_WORDS 4
233 #define EQOS_DESCRIPTOR_SIZE (EQOS_DESCRIPTOR_WORDS * 4)
234 /* We assume ARCH_DMA_MINALIGN >= 16; 16 is the EQOS HW minimum */
235 #define EQOS_DESCRIPTOR_ALIGN ARCH_DMA_MINALIGN
236 #define EQOS_DESCRIPTORS_TX 4
237 #define EQOS_DESCRIPTORS_RX 4
238 #define EQOS_DESCRIPTORS_NUM (EQOS_DESCRIPTORS_TX + EQOS_DESCRIPTORS_RX)
239 #define EQOS_DESCRIPTORS_SIZE ALIGN(EQOS_DESCRIPTORS_NUM * \
240 EQOS_DESCRIPTOR_SIZE, ARCH_DMA_MINALIGN)
241 #define EQOS_BUFFER_ALIGN ARCH_DMA_MINALIGN
242 #define EQOS_MAX_PACKET_SIZE ALIGN(1568, ARCH_DMA_MINALIGN)
243 #define EQOS_RX_BUFFER_SIZE (EQOS_DESCRIPTORS_RX * EQOS_MAX_PACKET_SIZE)
244
245 /*
246 * Warn if the cache-line size is larger than the descriptor size. In such
247 * cases the driver will likely fail because the CPU needs to flush the cache
248 * when requeuing RX buffers, therefore descriptors written by the hardware
249 * may be discarded. Architectures with full IO coherence, such as x86, do not
250 * experience this issue, and hence are excluded from this condition.
251 *
252 * This can be fixed by defining CONFIG_SYS_NONCACHED_MEMORY which will cause
253 * the driver to allocate descriptors from a pool of non-cached memory.
254 */
255 #if EQOS_DESCRIPTOR_SIZE < ARCH_DMA_MINALIGN
256 #if !defined(CONFIG_SYS_NONCACHED_MEMORY) && \
257 !defined(CONFIG_SYS_DCACHE_OFF) && !defined(CONFIG_X86)
258 #warning Cache line size is larger than descriptor size
259 #endif
260 #endif
261
262 struct eqos_desc {
263 u32 des0;
264 u32 des1;
265 u32 des2;
266 u32 des3;
267 };
268
269 #define EQOS_DESC3_OWN BIT(31)
270 #define EQOS_DESC3_FD BIT(29)
271 #define EQOS_DESC3_LD BIT(28)
272 #define EQOS_DESC3_BUF1V BIT(24)
273
274 /*
275 * TX and RX descriptors are 16 bytes. This causes problems with the cache
276 * maintenance on CPUs where the cache-line size exceeds the size of these
277 * descriptors. What will happen is that when the driver receives a packet
278 * it will be immediately requeued for the hardware to reuse. The CPU will
279 * therefore need to flush the cache-line containing the descriptor, which
280 * will cause all other descriptors in the same cache-line to be flushed
281 * along with it. If one of those descriptors had been written to by the
282 * device those changes (and the associated packet) will be lost.
283 *
284 * To work around this, we make use of non-cached memory if available. If
285 * descriptors are mapped uncached there's no need to manually flush them
286 * or invalidate them.
287 *
288 * Note that this only applies to descriptors. The packet data buffers do
289 * not have the same constraints since they are 1536 bytes large, so they
290 * are unlikely to share cache-lines.
291 */
eqos_alloc_descs(unsigned int num)292 static void *eqos_alloc_descs(unsigned int num)
293 {
294 #ifdef CONFIG_SYS_NONCACHED_MEMORY
295 return (void *)noncached_alloc(EQOS_DESCRIPTORS_SIZE,
296 EQOS_DESCRIPTOR_ALIGN);
297 #else
298 return memalign(EQOS_DESCRIPTOR_ALIGN, EQOS_DESCRIPTORS_SIZE);
299 #endif
300 }
301
eqos_free_descs(void * descs)302 static void eqos_free_descs(void *descs)
303 {
304 #ifdef CONFIG_SYS_NONCACHED_MEMORY
305 /* FIXME: noncached_alloc() has no opposite */
306 #else
307 free(descs);
308 #endif
309 }
310
311 #ifdef CONFIG_QOS_FULL
eqos_inval_desc_tegra186(void * desc)312 static void eqos_inval_desc_tegra186(void *desc)
313 {
314 #ifndef CONFIG_SYS_NONCACHED_MEMORY
315 unsigned long start = (unsigned long)desc & ~(ARCH_DMA_MINALIGN - 1);
316 unsigned long end = ALIGN(start + EQOS_DESCRIPTOR_SIZE,
317 ARCH_DMA_MINALIGN);
318
319 invalidate_dcache_range(start, end);
320 #endif
321 }
322 #endif
323
eqos_inval_desc_generic(void * desc)324 static void eqos_inval_desc_generic(void *desc)
325 {
326 #ifndef CONFIG_SYS_NONCACHED_MEMORY
327 unsigned long start = rounddown((unsigned long)desc, ARCH_DMA_MINALIGN);
328 unsigned long end = roundup((unsigned long)desc + EQOS_DESCRIPTOR_SIZE,
329 ARCH_DMA_MINALIGN);
330
331 invalidate_dcache_range(start, end);
332 #endif
333 }
334
335 #ifdef CONFIG_QOS_FULL
eqos_flush_desc_tegra186(void * desc)336 static void eqos_flush_desc_tegra186(void *desc)
337 {
338 #ifndef CONFIG_SYS_NONCACHED_MEMORY
339 flush_cache((unsigned long)desc, EQOS_DESCRIPTOR_SIZE);
340 #endif
341 }
342 #endif
343
eqos_flush_desc_generic(void * desc)344 static void eqos_flush_desc_generic(void *desc)
345 {
346 #ifndef CONFIG_SYS_NONCACHED_MEMORY
347 unsigned long start = rounddown((unsigned long)desc, ARCH_DMA_MINALIGN);
348 unsigned long end = roundup((unsigned long)desc + EQOS_DESCRIPTOR_SIZE,
349 ARCH_DMA_MINALIGN);
350
351 flush_dcache_range(start, end);
352 #endif
353 }
354
355 #ifdef CONFIG_QOS_FULL
eqos_inval_buffer_tegra186(void * buf,size_t size)356 static void eqos_inval_buffer_tegra186(void *buf, size_t size)
357 {
358 unsigned long start = (unsigned long)buf & ~(ARCH_DMA_MINALIGN - 1);
359 unsigned long end = ALIGN(start + size, ARCH_DMA_MINALIGN);
360
361 invalidate_dcache_range(start, end);
362 }
363 #endif
364
eqos_inval_buffer_generic(void * buf,size_t size)365 static void eqos_inval_buffer_generic(void *buf, size_t size)
366 {
367 unsigned long start = rounddown((unsigned long)buf, ARCH_DMA_MINALIGN);
368 unsigned long end = roundup((unsigned long)buf + size,
369 ARCH_DMA_MINALIGN);
370
371 invalidate_dcache_range(start, end);
372 }
373
374 #ifdef CONFIG_QOS_FULL
eqos_flush_buffer_tegra186(void * buf,size_t size)375 static void eqos_flush_buffer_tegra186(void *buf, size_t size)
376 {
377 flush_cache((unsigned long)buf, size);
378 }
379 #endif
380
eqos_flush_buffer_generic(void * buf,size_t size)381 static void eqos_flush_buffer_generic(void *buf, size_t size)
382 {
383 unsigned long start = rounddown((unsigned long)buf, ARCH_DMA_MINALIGN);
384 unsigned long end = roundup((unsigned long)buf + size,
385 ARCH_DMA_MINALIGN);
386
387 flush_dcache_range(start, end);
388 }
389
eqos_mdio_wait_idle(struct eqos_priv * eqos)390 static int eqos_mdio_wait_idle(struct eqos_priv *eqos)
391 {
392 return wait_for_bit_le32(&eqos->mac_regs->mdio_address,
393 EQOS_MAC_MDIO_ADDRESS_GB, false,
394 1000000, true);
395 }
396
eqos_mdio_read(struct mii_dev * bus,int mdio_addr,int mdio_devad,int mdio_reg)397 static int eqos_mdio_read(struct mii_dev *bus, int mdio_addr, int mdio_devad,
398 int mdio_reg)
399 {
400 struct eqos_priv *eqos = bus->priv;
401 u32 val;
402 int ret;
403
404 debug("%s(dev=%p, addr=%x, reg=%d):\n", __func__, eqos->dev, mdio_addr,
405 mdio_reg);
406
407 ret = eqos_mdio_wait_idle(eqos);
408 if (ret) {
409 pr_err("MDIO not idle at entry");
410 return ret;
411 }
412
413 val = readl(&eqos->mac_regs->mdio_address);
414 val &= EQOS_MAC_MDIO_ADDRESS_SKAP |
415 EQOS_MAC_MDIO_ADDRESS_C45E;
416 val |= (mdio_addr << EQOS_MAC_MDIO_ADDRESS_PA_SHIFT) |
417 (mdio_reg << EQOS_MAC_MDIO_ADDRESS_RDA_SHIFT) |
418 (eqos->config->config_mac_mdio <<
419 EQOS_MAC_MDIO_ADDRESS_CR_SHIFT) |
420 (EQOS_MAC_MDIO_ADDRESS_GOC_READ <<
421 EQOS_MAC_MDIO_ADDRESS_GOC_SHIFT) |
422 EQOS_MAC_MDIO_ADDRESS_GB;
423 writel(val, &eqos->mac_regs->mdio_address);
424
425 udelay(eqos->config->mdio_wait);
426
427 ret = eqos_mdio_wait_idle(eqos);
428 if (ret) {
429 pr_err("MDIO read didn't complete");
430 return ret;
431 }
432
433 val = readl(&eqos->mac_regs->mdio_data);
434 val &= EQOS_MAC_MDIO_DATA_GD_MASK;
435
436 debug("%s: val=%x\n", __func__, val);
437
438 return val;
439 }
440
eqos_mdio_write(struct mii_dev * bus,int mdio_addr,int mdio_devad,int mdio_reg,u16 mdio_val)441 static int eqos_mdio_write(struct mii_dev *bus, int mdio_addr, int mdio_devad,
442 int mdio_reg, u16 mdio_val)
443 {
444 struct eqos_priv *eqos = bus->priv;
445 u32 val;
446 int ret;
447
448 debug("%s(dev=%p, addr=%x, reg=%d, val=%x):\n", __func__, eqos->dev,
449 mdio_addr, mdio_reg, mdio_val);
450
451 ret = eqos_mdio_wait_idle(eqos);
452 if (ret) {
453 pr_err("MDIO not idle at entry");
454 return ret;
455 }
456
457 writel(mdio_val, &eqos->mac_regs->mdio_data);
458
459 val = readl(&eqos->mac_regs->mdio_address);
460 val &= EQOS_MAC_MDIO_ADDRESS_SKAP |
461 EQOS_MAC_MDIO_ADDRESS_C45E;
462 val |= (mdio_addr << EQOS_MAC_MDIO_ADDRESS_PA_SHIFT) |
463 (mdio_reg << EQOS_MAC_MDIO_ADDRESS_RDA_SHIFT) |
464 (eqos->config->config_mac_mdio <<
465 EQOS_MAC_MDIO_ADDRESS_CR_SHIFT) |
466 (EQOS_MAC_MDIO_ADDRESS_GOC_WRITE <<
467 EQOS_MAC_MDIO_ADDRESS_GOC_SHIFT) |
468 EQOS_MAC_MDIO_ADDRESS_GB;
469 writel(val, &eqos->mac_regs->mdio_address);
470
471 udelay(eqos->config->mdio_wait);
472
473 ret = eqos_mdio_wait_idle(eqos);
474 if (ret) {
475 pr_err("MDIO read didn't complete");
476 return ret;
477 }
478
479 return 0;
480 }
481
482 #ifdef CONFIG_QOS_FULL
eqos_start_clks_tegra186(struct udevice * dev)483 static int eqos_start_clks_tegra186(struct udevice *dev)
484 {
485 #ifdef CONFIG_CLK
486 struct eqos_priv *eqos = dev_get_priv(dev);
487 int ret;
488
489 debug("%s(dev=%p):\n", __func__, dev);
490
491 ret = clk_enable(&eqos->clk_slave_bus);
492 if (ret < 0) {
493 pr_err("clk_enable(clk_slave_bus) failed: %d", ret);
494 goto err;
495 }
496
497 ret = clk_enable(&eqos->clk_master_bus);
498 if (ret < 0) {
499 pr_err("clk_enable(clk_master_bus) failed: %d", ret);
500 goto err_disable_clk_slave_bus;
501 }
502
503 ret = clk_enable(&eqos->clk_rx);
504 if (ret < 0) {
505 pr_err("clk_enable(clk_rx) failed: %d", ret);
506 goto err_disable_clk_master_bus;
507 }
508
509 ret = clk_enable(&eqos->clk_ptp_ref);
510 if (ret < 0) {
511 pr_err("clk_enable(clk_ptp_ref) failed: %d", ret);
512 goto err_disable_clk_rx;
513 }
514
515 ret = clk_set_rate(&eqos->clk_ptp_ref, 125 * 1000 * 1000);
516 if (ret < 0) {
517 pr_err("clk_set_rate(clk_ptp_ref) failed: %d", ret);
518 goto err_disable_clk_ptp_ref;
519 }
520
521 ret = clk_enable(&eqos->clk_tx);
522 if (ret < 0) {
523 pr_err("clk_enable(clk_tx) failed: %d", ret);
524 goto err_disable_clk_ptp_ref;
525 }
526 #endif
527
528 debug("%s: OK\n", __func__);
529 return 0;
530
531 #ifdef CONFIG_CLK
532 err_disable_clk_ptp_ref:
533 clk_disable(&eqos->clk_ptp_ref);
534 err_disable_clk_rx:
535 clk_disable(&eqos->clk_rx);
536 err_disable_clk_master_bus:
537 clk_disable(&eqos->clk_master_bus);
538 err_disable_clk_slave_bus:
539 clk_disable(&eqos->clk_slave_bus);
540 err:
541 debug("%s: FAILED: %d\n", __func__, ret);
542 return ret;
543 #endif
544 }
545
eqos_start_clks_stm32(struct udevice * dev)546 static int eqos_start_clks_stm32(struct udevice *dev)
547 {
548 #ifdef CONFIG_CLK
549 struct eqos_priv *eqos = dev_get_priv(dev);
550 int ret;
551
552 debug("%s(dev=%p):\n", __func__, dev);
553
554 ret = clk_enable(&eqos->clk_master_bus);
555 if (ret < 0) {
556 pr_err("clk_enable(clk_master_bus) failed: %d", ret);
557 goto err;
558 }
559
560 if (clk_valid(&eqos->clk_rx)) {
561 ret = clk_enable(&eqos->clk_rx);
562 if (ret < 0) {
563 pr_err("clk_enable(clk_rx) failed: %d", ret);
564 goto err_disable_clk_master_bus;
565 }
566 }
567
568 if (clk_valid(&eqos->clk_tx)) {
569 ret = clk_enable(&eqos->clk_tx);
570 if (ret < 0) {
571 pr_err("clk_enable(clk_tx) failed: %d", ret);
572 goto err_disable_clk_rx;
573 }
574 }
575
576 if (clk_valid(&eqos->clk_ck)) {
577 ret = clk_enable(&eqos->clk_ck);
578 if (ret < 0) {
579 pr_err("clk_enable(clk_ck) failed: %d", ret);
580 goto err_disable_clk_tx;
581 }
582 }
583 #endif
584
585 debug("%s: OK\n", __func__);
586 return 0;
587
588 #ifdef CONFIG_CLK
589 err_disable_clk_tx:
590 if (clk_valid(&eqos->clk_tx))
591 clk_disable(&eqos->clk_tx);
592 err_disable_clk_rx:
593 if (clk_valid(&eqos->clk_rx))
594 clk_disable(&eqos->clk_rx);
595 err_disable_clk_master_bus:
596 clk_disable(&eqos->clk_master_bus);
597 err:
598 debug("%s: FAILED: %d\n", __func__, ret);
599 return ret;
600 #endif
601 }
602
eqos_start_clks_imx(struct udevice * dev)603 static int eqos_start_clks_imx(struct udevice *dev)
604 {
605 return 0;
606 }
607
eqos_stop_clks_tegra186(struct udevice * dev)608 static void eqos_stop_clks_tegra186(struct udevice *dev)
609 {
610 #ifdef CONFIG_CLK
611 struct eqos_priv *eqos = dev_get_priv(dev);
612
613 debug("%s(dev=%p):\n", __func__, dev);
614
615 clk_disable(&eqos->clk_tx);
616 clk_disable(&eqos->clk_ptp_ref);
617 clk_disable(&eqos->clk_rx);
618 clk_disable(&eqos->clk_master_bus);
619 clk_disable(&eqos->clk_slave_bus);
620 #endif
621
622 debug("%s: OK\n", __func__);
623 }
624
eqos_stop_clks_stm32(struct udevice * dev)625 static void eqos_stop_clks_stm32(struct udevice *dev)
626 {
627 #ifdef CONFIG_CLK
628 struct eqos_priv *eqos = dev_get_priv(dev);
629
630 debug("%s(dev=%p):\n", __func__, dev);
631
632 if (clk_valid(&eqos->clk_tx))
633 clk_disable(&eqos->clk_tx);
634 if (clk_valid(&eqos->clk_rx))
635 clk_disable(&eqos->clk_rx);
636 clk_disable(&eqos->clk_master_bus);
637 if (clk_valid(&eqos->clk_ck))
638 clk_disable(&eqos->clk_ck);
639 #endif
640
641 debug("%s: OK\n", __func__);
642 }
643
eqos_stop_clks_imx(struct udevice * dev)644 static void eqos_stop_clks_imx(struct udevice *dev)
645 {
646 /* empty */
647 }
648
eqos_start_resets_tegra186(struct udevice * dev)649 static int eqos_start_resets_tegra186(struct udevice *dev)
650 {
651 struct eqos_priv *eqos = dev_get_priv(dev);
652 int ret;
653
654 debug("%s(dev=%p):\n", __func__, dev);
655
656 ret = dm_gpio_set_value(&eqos->phy_reset_gpio, 1);
657 if (ret < 0) {
658 pr_err("dm_gpio_set_value(phy_reset, assert) failed: %d", ret);
659 return ret;
660 }
661
662 udelay(2);
663
664 ret = dm_gpio_set_value(&eqos->phy_reset_gpio, 0);
665 if (ret < 0) {
666 pr_err("dm_gpio_set_value(phy_reset, deassert) failed: %d", ret);
667 return ret;
668 }
669
670 ret = reset_assert(&eqos->reset_ctl);
671 if (ret < 0) {
672 pr_err("reset_assert() failed: %d", ret);
673 return ret;
674 }
675
676 udelay(2);
677
678 ret = reset_deassert(&eqos->reset_ctl);
679 if (ret < 0) {
680 pr_err("reset_deassert() failed: %d", ret);
681 return ret;
682 }
683
684 debug("%s: OK\n", __func__);
685 return 0;
686 }
687 #endif
688
eqos_start_resets_stm32(struct udevice * dev)689 static int eqos_start_resets_stm32(struct udevice *dev)
690 {
691 struct eqos_priv *eqos = dev_get_priv(dev);
692 int ret;
693
694 debug("%s(dev=%p):\n", __func__, dev);
695 if (dm_gpio_is_valid(&eqos->phy_reset_gpio)) {
696 ret = dm_gpio_set_value(&eqos->phy_reset_gpio, 0);
697 if (ret < 0) {
698 pr_err("dm_gpio_set_value(phy_reset, deassert) failed: %d",
699 ret);
700 return ret;
701 }
702
703 udelay(eqos->reset_delays[0]);
704
705 ret = dm_gpio_set_value(&eqos->phy_reset_gpio, 1);
706 if (ret < 0) {
707 pr_err("dm_gpio_set_value(phy_reset, assert) failed: %d",
708 ret);
709 return ret;
710 }
711
712 udelay(eqos->reset_delays[1]);
713
714 ret = dm_gpio_set_value(&eqos->phy_reset_gpio, 0);
715 if (ret < 0) {
716 pr_err("dm_gpio_set_value(phy_reset, deassert) failed: %d",
717 ret);
718 return ret;
719 }
720
721 udelay(eqos->reset_delays[2]);
722 }
723 debug("%s: OK\n", __func__);
724
725 return 0;
726 }
727
728 #ifdef CONFIG_QOS_FULL
eqos_start_resets_imx(struct udevice * dev)729 static int eqos_start_resets_imx(struct udevice *dev)
730 {
731 return 0;
732 }
733
eqos_stop_resets_tegra186(struct udevice * dev)734 static int eqos_stop_resets_tegra186(struct udevice *dev)
735 {
736 struct eqos_priv *eqos = dev_get_priv(dev);
737
738 reset_assert(&eqos->reset_ctl);
739 dm_gpio_set_value(&eqos->phy_reset_gpio, 1);
740
741 return 0;
742 }
743 #endif
744
eqos_stop_resets_stm32(struct udevice * dev)745 static int eqos_stop_resets_stm32(struct udevice *dev)
746 {
747 struct eqos_priv *eqos = dev_get_priv(dev);
748 int ret;
749
750 if (dm_gpio_is_valid(&eqos->phy_reset_gpio)) {
751 ret = dm_gpio_set_value(&eqos->phy_reset_gpio, 1);
752 if (ret < 0) {
753 pr_err("dm_gpio_set_value(phy_reset, assert) failed: %d",
754 ret);
755 return ret;
756 }
757 }
758
759 return 0;
760 }
761
762 #ifdef CONFIG_QOS_FULL
eqos_stop_resets_imx(struct udevice * dev)763 static int eqos_stop_resets_imx(struct udevice *dev)
764 {
765 return 0;
766 }
767
eqos_calibrate_pads_tegra186(struct udevice * dev)768 static int eqos_calibrate_pads_tegra186(struct udevice *dev)
769 {
770 struct eqos_priv *eqos = dev_get_priv(dev);
771 int ret;
772
773 debug("%s(dev=%p):\n", __func__, dev);
774
775 setbits_le32(&eqos->tegra186_regs->sdmemcomppadctrl,
776 EQOS_SDMEMCOMPPADCTRL_PAD_E_INPUT_OR_E_PWRD);
777
778 udelay(1);
779
780 setbits_le32(&eqos->tegra186_regs->auto_cal_config,
781 EQOS_AUTO_CAL_CONFIG_START | EQOS_AUTO_CAL_CONFIG_ENABLE);
782
783 ret = wait_for_bit_le32(&eqos->tegra186_regs->auto_cal_status,
784 EQOS_AUTO_CAL_STATUS_ACTIVE, true, 10, false);
785 if (ret) {
786 pr_err("calibrate didn't start");
787 goto failed;
788 }
789
790 ret = wait_for_bit_le32(&eqos->tegra186_regs->auto_cal_status,
791 EQOS_AUTO_CAL_STATUS_ACTIVE, false, 10, false);
792 if (ret) {
793 pr_err("calibrate didn't finish");
794 goto failed;
795 }
796
797 ret = 0;
798
799 failed:
800 clrbits_le32(&eqos->tegra186_regs->sdmemcomppadctrl,
801 EQOS_SDMEMCOMPPADCTRL_PAD_E_INPUT_OR_E_PWRD);
802
803 debug("%s: returns %d\n", __func__, ret);
804
805 return ret;
806 }
807
eqos_disable_calibration_tegra186(struct udevice * dev)808 static int eqos_disable_calibration_tegra186(struct udevice *dev)
809 {
810 struct eqos_priv *eqos = dev_get_priv(dev);
811
812 debug("%s(dev=%p):\n", __func__, dev);
813
814 clrbits_le32(&eqos->tegra186_regs->auto_cal_config,
815 EQOS_AUTO_CAL_CONFIG_ENABLE);
816
817 return 0;
818 }
819
eqos_get_tick_clk_rate_tegra186(struct udevice * dev)820 static ulong eqos_get_tick_clk_rate_tegra186(struct udevice *dev)
821 {
822 #ifdef CONFIG_CLK
823 struct eqos_priv *eqos = dev_get_priv(dev);
824
825 return clk_get_rate(&eqos->clk_slave_bus);
826 #else
827 return 0;
828 #endif
829 }
830 #endif
831
eqos_get_tick_clk_rate_stm32(struct udevice * dev)832 static ulong eqos_get_tick_clk_rate_stm32(struct udevice *dev)
833 {
834 #ifdef CONFIG_CLK
835 struct eqos_priv *eqos = dev_get_priv(dev);
836
837 return clk_get_rate(&eqos->clk_master_bus);
838 #else
839 return 0;
840 #endif
841 }
842
843 #ifdef CONFIG_QOS_FULL
imx_get_eqos_csr_clk(void)844 __weak u32 imx_get_eqos_csr_clk(void)
845 {
846 return 100 * 1000000;
847 }
imx_eqos_txclk_set_rate(unsigned long rate)848 __weak int imx_eqos_txclk_set_rate(unsigned long rate)
849 {
850 return 0;
851 }
852
eqos_get_tick_clk_rate_imx(struct udevice * dev)853 static ulong eqos_get_tick_clk_rate_imx(struct udevice *dev)
854 {
855 return imx_get_eqos_csr_clk();
856 }
857 #endif
858
eqos_calibrate_pads_stm32(struct udevice * dev)859 static int eqos_calibrate_pads_stm32(struct udevice *dev)
860 {
861 return 0;
862 }
863
864 #ifdef CONFIG_QOS_FULL
eqos_calibrate_pads_imx(struct udevice * dev)865 static int eqos_calibrate_pads_imx(struct udevice *dev)
866 {
867 return 0;
868 }
869 #endif
870
eqos_disable_calibration_stm32(struct udevice * dev)871 static int eqos_disable_calibration_stm32(struct udevice *dev)
872 {
873 return 0;
874 }
875
876 #ifdef CONFIG_QOS_FULL
eqos_disable_calibration_imx(struct udevice * dev)877 static int eqos_disable_calibration_imx(struct udevice *dev)
878 {
879 return 0;
880 }
881 #endif
882
eqos_set_full_duplex(struct udevice * dev)883 static int eqos_set_full_duplex(struct udevice *dev)
884 {
885 struct eqos_priv *eqos = dev_get_priv(dev);
886
887 debug("%s(dev=%p):\n", __func__, dev);
888
889 setbits_le32(&eqos->mac_regs->configuration, EQOS_MAC_CONFIGURATION_DM);
890
891 return 0;
892 }
893
eqos_set_half_duplex(struct udevice * dev)894 static int eqos_set_half_duplex(struct udevice *dev)
895 {
896 struct eqos_priv *eqos = dev_get_priv(dev);
897
898 debug("%s(dev=%p):\n", __func__, dev);
899
900 clrbits_le32(&eqos->mac_regs->configuration, EQOS_MAC_CONFIGURATION_DM);
901
902 /* WAR: Flush TX queue when switching to half-duplex */
903 setbits_le32(&eqos->mtl_regs->txq0_operation_mode,
904 EQOS_MTL_TXQ0_OPERATION_MODE_FTQ);
905
906 return 0;
907 }
908
eqos_set_gmii_speed(struct udevice * dev)909 static int eqos_set_gmii_speed(struct udevice *dev)
910 {
911 struct eqos_priv *eqos = dev_get_priv(dev);
912
913 debug("%s(dev=%p):\n", __func__, dev);
914
915 clrbits_le32(&eqos->mac_regs->configuration,
916 EQOS_MAC_CONFIGURATION_PS | EQOS_MAC_CONFIGURATION_FES);
917
918 return 0;
919 }
920
eqos_set_mii_speed_100(struct udevice * dev)921 static int eqos_set_mii_speed_100(struct udevice *dev)
922 {
923 struct eqos_priv *eqos = dev_get_priv(dev);
924
925 debug("%s(dev=%p):\n", __func__, dev);
926
927 setbits_le32(&eqos->mac_regs->configuration,
928 EQOS_MAC_CONFIGURATION_PS | EQOS_MAC_CONFIGURATION_FES);
929
930 return 0;
931 }
932
eqos_set_mii_speed_10(struct udevice * dev)933 static int eqos_set_mii_speed_10(struct udevice *dev)
934 {
935 struct eqos_priv *eqos = dev_get_priv(dev);
936
937 debug("%s(dev=%p):\n", __func__, dev);
938
939 clrsetbits_le32(&eqos->mac_regs->configuration,
940 EQOS_MAC_CONFIGURATION_FES, EQOS_MAC_CONFIGURATION_PS);
941
942 return 0;
943 }
944
945 #ifdef CONFIG_QOS_FULL
eqos_set_tx_clk_speed_tegra186(struct udevice * dev)946 static int eqos_set_tx_clk_speed_tegra186(struct udevice *dev)
947 {
948 #ifdef CONFIG_CLK
949 struct eqos_priv *eqos = dev_get_priv(dev);
950 ulong rate;
951 int ret;
952
953 debug("%s(dev=%p):\n", __func__, dev);
954
955 switch (eqos->phy->speed) {
956 case SPEED_1000:
957 rate = 125 * 1000 * 1000;
958 break;
959 case SPEED_100:
960 rate = 25 * 1000 * 1000;
961 break;
962 case SPEED_10:
963 rate = 2.5 * 1000 * 1000;
964 break;
965 default:
966 pr_err("invalid speed %d", eqos->phy->speed);
967 return -EINVAL;
968 }
969
970 ret = clk_set_rate(&eqos->clk_tx, rate);
971 if (ret < 0) {
972 pr_err("clk_set_rate(tx_clk, %lu) failed: %d", rate, ret);
973 return ret;
974 }
975 #endif
976
977 return 0;
978 }
979 #endif
980
eqos_set_tx_clk_speed_stm32(struct udevice * dev)981 static int eqos_set_tx_clk_speed_stm32(struct udevice *dev)
982 {
983 return 0;
984 }
985
986 #ifdef CONFIG_QOS_FULL
eqos_set_tx_clk_speed_imx(struct udevice * dev)987 static int eqos_set_tx_clk_speed_imx(struct udevice *dev)
988 {
989 struct eqos_priv *eqos = dev_get_priv(dev);
990 ulong rate;
991 int ret;
992
993 debug("%s(dev=%p):\n", __func__, dev);
994
995 switch (eqos->phy->speed) {
996 case SPEED_1000:
997 rate = 125 * 1000 * 1000;
998 break;
999 case SPEED_100:
1000 rate = 25 * 1000 * 1000;
1001 break;
1002 case SPEED_10:
1003 rate = 2.5 * 1000 * 1000;
1004 break;
1005 default:
1006 pr_err("invalid speed %d", eqos->phy->speed);
1007 return -EINVAL;
1008 }
1009
1010 ret = imx_eqos_txclk_set_rate(rate);
1011 if (ret < 0) {
1012 pr_err("imx (tx_clk, %lu) failed: %d", rate, ret);
1013 return ret;
1014 }
1015
1016 return 0;
1017 }
1018 #endif
1019
eqos_adjust_link(struct udevice * dev)1020 static int eqos_adjust_link(struct udevice *dev)
1021 {
1022 struct eqos_priv *eqos = dev_get_priv(dev);
1023 int ret;
1024 bool en_calibration;
1025
1026 debug("%s(dev=%p):\n", __func__, dev);
1027
1028 if (eqos->phy->duplex)
1029 ret = eqos_set_full_duplex(dev);
1030 else
1031 ret = eqos_set_half_duplex(dev);
1032 if (ret < 0) {
1033 pr_err("eqos_set_*_duplex() failed: %d", ret);
1034 return ret;
1035 }
1036
1037 switch (eqos->phy->speed) {
1038 case SPEED_1000:
1039 en_calibration = true;
1040 ret = eqos_set_gmii_speed(dev);
1041 break;
1042 case SPEED_100:
1043 en_calibration = true;
1044 ret = eqos_set_mii_speed_100(dev);
1045 break;
1046 case SPEED_10:
1047 en_calibration = false;
1048 ret = eqos_set_mii_speed_10(dev);
1049 break;
1050 default:
1051 pr_err("invalid speed %d", eqos->phy->speed);
1052 return -EINVAL;
1053 }
1054 if (ret < 0) {
1055 pr_err("eqos_set_*mii_speed*() failed: %d", ret);
1056 return ret;
1057 }
1058
1059 if (en_calibration) {
1060 ret = eqos->config->ops->eqos_calibrate_pads(dev);
1061 if (ret < 0) {
1062 pr_err("eqos_calibrate_pads() failed: %d",
1063 ret);
1064 return ret;
1065 }
1066 } else {
1067 ret = eqos->config->ops->eqos_disable_calibration(dev);
1068 if (ret < 0) {
1069 pr_err("eqos_disable_calibration() failed: %d",
1070 ret);
1071 return ret;
1072 }
1073 }
1074 ret = eqos->config->ops->eqos_set_tx_clk_speed(dev);
1075 if (ret < 0) {
1076 pr_err("eqos_set_tx_clk_speed() failed: %d", ret);
1077 return ret;
1078 }
1079
1080 return 0;
1081 }
1082
eqos_write_hwaddr(struct udevice * dev)1083 int eqos_write_hwaddr(struct udevice *dev)
1084 {
1085 struct eth_pdata *plat = dev_get_platdata(dev);
1086 struct eqos_priv *eqos = dev_get_priv(dev);
1087 uint32_t val;
1088
1089 /*
1090 * This function may be called before start() or after stop(). At that
1091 * time, on at least some configurations of the EQoS HW, all clocks to
1092 * the EQoS HW block will be stopped, and a reset signal applied. If
1093 * any register access is attempted in this state, bus timeouts or CPU
1094 * hangs may occur. This check prevents that.
1095 *
1096 * A simple solution to this problem would be to not implement
1097 * write_hwaddr(), since start() always writes the MAC address into HW
1098 * anyway. However, it is desirable to implement write_hwaddr() to
1099 * support the case of SW that runs subsequent to U-Boot which expects
1100 * the MAC address to already be programmed into the EQoS registers,
1101 * which must happen irrespective of whether the U-Boot user (or
1102 * scripts) actually made use of the EQoS device, and hence
1103 * irrespective of whether start() was ever called.
1104 *
1105 * Note that this requirement by subsequent SW is not valid for
1106 * Tegra186, and is likely not valid for any non-PCI instantiation of
1107 * the EQoS HW block. This function is implemented solely as
1108 * future-proofing with the expectation the driver will eventually be
1109 * ported to some system where the expectation above is true.
1110 */
1111 if (!eqos->config->reg_access_always_ok && !eqos->reg_access_ok)
1112 return 0;
1113
1114 /* Update the MAC address */
1115 val = (plat->enetaddr[5] << 8) |
1116 (plat->enetaddr[4]);
1117 writel(val, &eqos->mac_regs->address0_high);
1118 val = (plat->enetaddr[3] << 24) |
1119 (plat->enetaddr[2] << 16) |
1120 (plat->enetaddr[1] << 8) |
1121 (plat->enetaddr[0]);
1122 writel(val, &eqos->mac_regs->address0_low);
1123
1124 return 0;
1125 }
1126
1127 #ifdef CONFIG_QOS_FULL
eqos_read_rom_hwaddr(struct udevice * dev)1128 static int eqos_read_rom_hwaddr(struct udevice *dev)
1129 {
1130 struct eth_pdata *pdata = dev_get_platdata(dev);
1131
1132 #ifdef CONFIG_ARCH_IMX8M
1133 imx_get_mac_from_fuse(dev->req_seq, pdata->enetaddr);
1134 #endif
1135 return !is_valid_ethaddr(pdata->enetaddr);
1136 }
1137 #endif
1138
eqos_init(struct udevice * dev)1139 int eqos_init(struct udevice *dev)
1140 {
1141 struct eqos_priv *eqos = dev_get_priv(dev);
1142 int ret = 0, limit = 10;
1143 ulong rate;
1144 u32 val;
1145
1146 debug("%s(dev=%p):\n", __func__, dev);
1147
1148 if (eqos->config->ops->eqos_start_clks) {
1149 ret = eqos->config->ops->eqos_start_clks(dev);
1150 if (ret < 0) {
1151 pr_err("eqos_start_clks() failed: %d", ret);
1152 goto err;
1153 }
1154 }
1155
1156 if (!eqos->mii_reseted) {
1157 ret = eqos->config->ops->eqos_start_resets(dev);
1158 if (ret < 0) {
1159 pr_err("eqos_start_resets() failed: %d", ret);
1160 goto err_stop_clks;
1161 }
1162
1163 eqos->mii_reseted = true;
1164 udelay(10);
1165 }
1166
1167 eqos->reg_access_ok = true;
1168
1169 /* DMA SW reset */
1170 val = readl(&eqos->dma_regs->mode);
1171 val |= EQOS_DMA_MODE_SWR;
1172 writel(val, &eqos->dma_regs->mode);
1173 while (limit--) {
1174 if (!(readl(&eqos->dma_regs->mode) & EQOS_DMA_MODE_SWR))
1175 break;
1176 mdelay(10);
1177 }
1178
1179 if (limit < 0) {
1180 pr_err("EQOS_DMA_MODE_SWR stuck");
1181 ret = -EAGAIN;
1182 goto err_stop_resets;
1183 }
1184
1185 ret = eqos->config->ops->eqos_calibrate_pads(dev);
1186 if (ret < 0) {
1187 pr_err("eqos_calibrate_pads() failed: %d", ret);
1188 goto err_stop_resets;
1189 }
1190 rate = eqos->config->ops->eqos_get_tick_clk_rate(dev);
1191
1192 val = (rate / 1000000) - 1;
1193 writel(val, &eqos->mac_regs->us_tic_counter);
1194
1195 /*
1196 * if PHY was already connected and configured,
1197 * don't need to reconnect/reconfigure again
1198 */
1199 if (!eqos->phy) {
1200 int addr = -1;
1201 #ifdef CONFIG_DM_ETH_PHY
1202 addr = eth_phy_get_addr(dev);
1203 #endif
1204 #ifdef DWC_NET_PHYADDR
1205 addr = DWC_NET_PHYADDR;
1206 #endif
1207 eqos->phy = phy_connect(eqos->mii, addr, dev,
1208 eqos->config->ops->eqos_get_interface(dev));
1209 if (!eqos->phy) {
1210 pr_err("phy_connect() failed");
1211 ret = -ENODEV;
1212 goto err_stop_resets;
1213 }
1214
1215 if (eqos->max_speed) {
1216 ret = phy_set_supported(eqos->phy, eqos->max_speed);
1217 if (ret) {
1218 pr_err("phy_set_supported() failed: %d", ret);
1219 goto err_shutdown_phy;
1220 }
1221 }
1222
1223 ret = phy_config(eqos->phy);
1224 if (ret < 0) {
1225 pr_err("phy_config() failed: %d", ret);
1226 goto err_shutdown_phy;
1227 }
1228 }
1229
1230 ret = phy_startup(eqos->phy);
1231 if (ret < 0) {
1232 pr_err("phy_startup() failed: %d", ret);
1233 goto err_shutdown_phy;
1234 }
1235
1236 if (!eqos->phy->link) {
1237 pr_err("No link");
1238 ret = -EINVAL;
1239 goto err_shutdown_phy;
1240 }
1241
1242 ret = eqos_adjust_link(dev);
1243 if (ret < 0) {
1244 pr_err("eqos_adjust_link() failed: %d", ret);
1245 goto err_shutdown_phy;
1246 }
1247
1248 debug("%s: OK\n", __func__);
1249 return 0;
1250
1251 err_shutdown_phy:
1252 phy_shutdown(eqos->phy);
1253 err_stop_resets:
1254 eqos->config->ops->eqos_stop_resets(dev);
1255 eqos->mii_reseted = false;
1256 err_stop_clks:
1257 if (eqos->config->ops->eqos_stop_clks)
1258 eqos->config->ops->eqos_stop_clks(dev);
1259 err:
1260 pr_err("FAILED: %d", ret);
1261 return ret;
1262 }
1263
eqos_enable(struct udevice * dev)1264 void eqos_enable(struct udevice *dev)
1265 {
1266 struct eqos_priv *eqos = dev_get_priv(dev);
1267 u32 val, tx_fifo_sz, rx_fifo_sz, tqs, rqs, pbl;
1268 ulong last_rx_desc;
1269 int i;
1270
1271 eqos->tx_desc_idx = 0;
1272 eqos->rx_desc_idx = 0;
1273
1274 /* Configure MTL */
1275 writel(0x60, &eqos->mtl_regs->txq0_quantum_weight - 0x100);
1276
1277 /* Enable Store and Forward mode for TX */
1278 /* Program Tx operating mode */
1279 setbits_le32(&eqos->mtl_regs->txq0_operation_mode,
1280 EQOS_MTL_TXQ0_OPERATION_MODE_TSF |
1281 (EQOS_MTL_TXQ0_OPERATION_MODE_TXQEN_ENABLED <<
1282 EQOS_MTL_TXQ0_OPERATION_MODE_TXQEN_SHIFT));
1283
1284 /* Transmit Queue weight */
1285 writel(0x10, &eqos->mtl_regs->txq0_quantum_weight);
1286
1287 /* Enable Store and Forward mode for RX, since no jumbo frame */
1288 setbits_le32(&eqos->mtl_regs->rxq0_operation_mode,
1289 EQOS_MTL_RXQ0_OPERATION_MODE_RSF |
1290 EQOS_MTL_RXQ0_OPERATION_MODE_FEP |
1291 EQOS_MTL_RXQ0_OPERATION_MODE_FUP);
1292
1293 /* Transmit/Receive queue fifo size; use all RAM for 1 queue */
1294 val = readl(&eqos->mac_regs->hw_feature1);
1295 tx_fifo_sz = (val >> EQOS_MAC_HW_FEATURE1_TXFIFOSIZE_SHIFT) &
1296 EQOS_MAC_HW_FEATURE1_TXFIFOSIZE_MASK;
1297 rx_fifo_sz = (val >> EQOS_MAC_HW_FEATURE1_RXFIFOSIZE_SHIFT) &
1298 EQOS_MAC_HW_FEATURE1_RXFIFOSIZE_MASK;
1299
1300 /*
1301 * r/tx_fifo_sz is encoded as log2(n / 128). Undo that by shifting.
1302 * r/tqs is encoded as (n / 256) - 1.
1303 */
1304 tqs = (128 << tx_fifo_sz) / 256 - 1;
1305 rqs = (128 << rx_fifo_sz) / 256 - 1;
1306
1307 clrsetbits_le32(&eqos->mtl_regs->txq0_operation_mode,
1308 EQOS_MTL_TXQ0_OPERATION_MODE_TQS_MASK <<
1309 EQOS_MTL_TXQ0_OPERATION_MODE_TQS_SHIFT,
1310 tqs << EQOS_MTL_TXQ0_OPERATION_MODE_TQS_SHIFT);
1311 clrsetbits_le32(&eqos->mtl_regs->rxq0_operation_mode,
1312 EQOS_MTL_RXQ0_OPERATION_MODE_RQS_MASK <<
1313 EQOS_MTL_RXQ0_OPERATION_MODE_RQS_SHIFT,
1314 rqs << EQOS_MTL_RXQ0_OPERATION_MODE_RQS_SHIFT);
1315
1316 /* Flow control used only if each channel gets 4KB or more FIFO */
1317 if (rqs >= ((4096 / 256) - 1)) {
1318 u32 rfd, rfa;
1319
1320 setbits_le32(&eqos->mtl_regs->rxq0_operation_mode,
1321 EQOS_MTL_RXQ0_OPERATION_MODE_EHFC);
1322
1323 /*
1324 * Set Threshold for Activating Flow Contol space for min 2
1325 * frames ie, (1500 * 1) = 1500 bytes.
1326 *
1327 * Set Threshold for Deactivating Flow Contol for space of
1328 * min 1 frame (frame size 1500bytes) in receive fifo
1329 */
1330 if (rqs == ((4096 / 256) - 1)) {
1331 /*
1332 * This violates the above formula because of FIFO size
1333 * limit therefore overflow may occur inspite of this.
1334 */
1335 rfd = 0x3; /* Full-3K */
1336 rfa = 0x1; /* Full-1.5K */
1337 } else if (rqs == ((8192 / 256) - 1)) {
1338 rfd = 0x6; /* Full-4K */
1339 rfa = 0xa; /* Full-6K */
1340 } else if (rqs == ((16384 / 256) - 1)) {
1341 rfd = 0x6; /* Full-4K */
1342 rfa = 0x12; /* Full-10K */
1343 } else {
1344 rfd = 0x6; /* Full-4K */
1345 rfa = 0x1E; /* Full-16K */
1346 }
1347
1348 clrsetbits_le32(&eqos->mtl_regs->rxq0_operation_mode,
1349 (EQOS_MTL_RXQ0_OPERATION_MODE_RFD_MASK <<
1350 EQOS_MTL_RXQ0_OPERATION_MODE_RFD_SHIFT) |
1351 (EQOS_MTL_RXQ0_OPERATION_MODE_RFA_MASK <<
1352 EQOS_MTL_RXQ0_OPERATION_MODE_RFA_SHIFT),
1353 (rfd <<
1354 EQOS_MTL_RXQ0_OPERATION_MODE_RFD_SHIFT) |
1355 (rfa <<
1356 EQOS_MTL_RXQ0_OPERATION_MODE_RFA_SHIFT));
1357 }
1358
1359 /* Configure MAC */
1360
1361 clrsetbits_le32(&eqos->mac_regs->rxq_ctrl0,
1362 EQOS_MAC_RXQ_CTRL0_RXQ0EN_MASK <<
1363 EQOS_MAC_RXQ_CTRL0_RXQ0EN_SHIFT,
1364 eqos->config->config_mac <<
1365 EQOS_MAC_RXQ_CTRL0_RXQ0EN_SHIFT);
1366
1367 clrsetbits_le32(&eqos->mac_regs->rxq_ctrl0,
1368 EQOS_MAC_RXQ_CTRL0_RXQ0EN_MASK <<
1369 EQOS_MAC_RXQ_CTRL0_RXQ0EN_SHIFT,
1370 0x2 <<
1371 EQOS_MAC_RXQ_CTRL0_RXQ0EN_SHIFT);
1372
1373 /* Multicast and Broadcast Queue Enable */
1374 setbits_le32(&eqos->mac_regs->unused_0a4,
1375 0x00100000);
1376 /* enable promise mode */
1377 setbits_le32(&eqos->mac_regs->unused_004[1],
1378 0x1);
1379
1380 /* Set TX flow control parameters */
1381 /* Set Pause Time */
1382 setbits_le32(&eqos->mac_regs->q0_tx_flow_ctrl,
1383 0xffff << EQOS_MAC_Q0_TX_FLOW_CTRL_PT_SHIFT);
1384 /* Assign priority for TX flow control */
1385 clrbits_le32(&eqos->mac_regs->txq_prty_map0,
1386 EQOS_MAC_TXQ_PRTY_MAP0_PSTQ0_MASK <<
1387 EQOS_MAC_TXQ_PRTY_MAP0_PSTQ0_SHIFT);
1388 /* Assign priority for RX flow control */
1389 clrbits_le32(&eqos->mac_regs->rxq_ctrl2,
1390 EQOS_MAC_RXQ_CTRL2_PSRQ0_MASK <<
1391 EQOS_MAC_RXQ_CTRL2_PSRQ0_SHIFT);
1392 /* Enable flow control */
1393 setbits_le32(&eqos->mac_regs->q0_tx_flow_ctrl,
1394 EQOS_MAC_Q0_TX_FLOW_CTRL_TFE);
1395 setbits_le32(&eqos->mac_regs->rx_flow_ctrl,
1396 EQOS_MAC_RX_FLOW_CTRL_RFE);
1397
1398 clrsetbits_le32(&eqos->mac_regs->configuration,
1399 EQOS_MAC_CONFIGURATION_GPSLCE |
1400 EQOS_MAC_CONFIGURATION_WD |
1401 EQOS_MAC_CONFIGURATION_JD |
1402 EQOS_MAC_CONFIGURATION_JE,
1403 EQOS_MAC_CONFIGURATION_CST |
1404 EQOS_MAC_CONFIGURATION_ACS);
1405
1406 eqos_write_hwaddr(dev);
1407
1408 /* Configure DMA */
1409
1410 /* Enable OSP mode */
1411 setbits_le32(&eqos->dma_regs->ch0_tx_control,
1412 EQOS_DMA_CH0_TX_CONTROL_OSP);
1413
1414 /* RX buffer size. Must be a multiple of bus width */
1415 clrsetbits_le32(&eqos->dma_regs->ch0_rx_control,
1416 EQOS_DMA_CH0_RX_CONTROL_RBSZ_MASK <<
1417 EQOS_DMA_CH0_RX_CONTROL_RBSZ_SHIFT,
1418 EQOS_MAX_PACKET_SIZE <<
1419 EQOS_DMA_CH0_RX_CONTROL_RBSZ_SHIFT);
1420
1421 setbits_le32(&eqos->dma_regs->ch0_control,
1422 EQOS_DMA_CH0_CONTROL_PBLX8);
1423
1424 /*
1425 * Burst length must be < 1/2 FIFO size.
1426 * FIFO size in tqs is encoded as (n / 256) - 1.
1427 * Each burst is n * 8 (PBLX8) * 16 (AXI width) == 128 bytes.
1428 * Half of n * 256 is n * 128, so pbl == tqs, modulo the -1.
1429 */
1430 pbl = tqs + 1;
1431 if (pbl > 32)
1432 pbl = 32;
1433 clrsetbits_le32(&eqos->dma_regs->ch0_tx_control,
1434 EQOS_DMA_CH0_TX_CONTROL_TXPBL_MASK <<
1435 EQOS_DMA_CH0_TX_CONTROL_TXPBL_SHIFT,
1436 pbl << EQOS_DMA_CH0_TX_CONTROL_TXPBL_SHIFT);
1437
1438 clrsetbits_le32(&eqos->dma_regs->ch0_rx_control,
1439 EQOS_DMA_CH0_RX_CONTROL_RXPBL_MASK <<
1440 EQOS_DMA_CH0_RX_CONTROL_RXPBL_SHIFT,
1441 8 << EQOS_DMA_CH0_RX_CONTROL_RXPBL_SHIFT);
1442
1443 /* DMA performance configuration */
1444 val = (2 << EQOS_DMA_SYSBUS_MODE_RD_OSR_LMT_SHIFT) |
1445 EQOS_DMA_SYSBUS_MODE_EAME | EQOS_DMA_SYSBUS_MODE_BLEN16 |
1446 EQOS_DMA_SYSBUS_MODE_BLEN8 | EQOS_DMA_SYSBUS_MODE_BLEN4;
1447 writel(val, &eqos->dma_regs->sysbus_mode);
1448
1449 /* Set up descriptors */
1450
1451 memset(eqos->descs, 0, EQOS_DESCRIPTORS_SIZE);
1452 for (i = 0; i < EQOS_DESCRIPTORS_RX; i++) {
1453 struct eqos_desc *rx_desc = &(eqos->rx_descs[i]);
1454 rx_desc->des0 = (u32)(ulong)(eqos->rx_dma_buf +
1455 (i * EQOS_MAX_PACKET_SIZE));
1456 rx_desc->des3 = EQOS_DESC3_OWN | EQOS_DESC3_BUF1V;
1457 mb();
1458 eqos->config->ops->eqos_flush_desc(rx_desc);
1459 eqos->config->ops->eqos_inval_buffer(eqos->rx_dma_buf +
1460 (i * EQOS_MAX_PACKET_SIZE),
1461 EQOS_MAX_PACKET_SIZE);
1462 }
1463
1464 writel(0, &eqos->dma_regs->ch0_txdesc_list_haddress);
1465 writel((ulong)eqos->tx_descs, &eqos->dma_regs->ch0_txdesc_list_address);
1466 writel(EQOS_DESCRIPTORS_TX - 1,
1467 &eqos->dma_regs->ch0_txdesc_ring_length);
1468
1469 writel(0, &eqos->dma_regs->ch0_rxdesc_list_haddress);
1470 writel((ulong)eqos->rx_descs, &eqos->dma_regs->ch0_rxdesc_list_address);
1471 writel(EQOS_DESCRIPTORS_RX - 1,
1472 &eqos->dma_regs->ch0_rxdesc_ring_length);
1473
1474 /* Enable everything */
1475 setbits_le32(&eqos->dma_regs->ch0_tx_control,
1476 EQOS_DMA_CH0_TX_CONTROL_ST);
1477 setbits_le32(&eqos->dma_regs->ch0_rx_control,
1478 EQOS_DMA_CH0_RX_CONTROL_SR);
1479 setbits_le32(&eqos->mac_regs->configuration,
1480 EQOS_MAC_CONFIGURATION_TE | EQOS_MAC_CONFIGURATION_RE);
1481
1482 /* TX tail pointer not written until we need to TX a packet */
1483 /*
1484 * Point RX tail pointer at last descriptor. Ideally, we'd point at the
1485 * first descriptor, implying all descriptors were available. However,
1486 * that's not distinguishable from none of the descriptors being
1487 * available.
1488 */
1489 last_rx_desc = (ulong)&(eqos->rx_descs[(EQOS_DESCRIPTORS_RX - 1)]);
1490 writel(last_rx_desc, &eqos->dma_regs->ch0_rxdesc_tail_pointer);
1491
1492 eqos->started = true;
1493 }
1494
eqos_start(struct udevice * dev)1495 static int __maybe_unused eqos_start(struct udevice *dev)
1496 {
1497 int ret;
1498
1499 ret = eqos_init(dev);
1500 if (ret)
1501 return ret;
1502
1503 eqos_enable(dev);
1504
1505 return 0;
1506 }
1507
eqos_stop(struct udevice * dev)1508 void eqos_stop(struct udevice *dev)
1509 {
1510 struct eqos_priv *eqos = dev_get_priv(dev);
1511 int i;
1512
1513 debug("%s(dev=%p):\n", __func__, dev);
1514
1515 if (!eqos->started)
1516 return;
1517 eqos->started = false;
1518 eqos->reg_access_ok = false;
1519
1520 /* Disable TX DMA */
1521 clrbits_le32(&eqos->dma_regs->ch0_tx_control,
1522 EQOS_DMA_CH0_TX_CONTROL_ST);
1523
1524 /* Wait for TX all packets to drain out of MTL */
1525 for (i = 0; i < 1000000; i++) {
1526 u32 val = readl(&eqos->mtl_regs->txq0_debug);
1527 u32 trcsts = (val >> EQOS_MTL_TXQ0_DEBUG_TRCSTS_SHIFT) &
1528 EQOS_MTL_TXQ0_DEBUG_TRCSTS_MASK;
1529 u32 txqsts = val & EQOS_MTL_TXQ0_DEBUG_TXQSTS;
1530 if ((trcsts != 1) && (!txqsts))
1531 break;
1532 }
1533
1534 /* Turn off MAC TX and RX */
1535 clrbits_le32(&eqos->mac_regs->configuration,
1536 EQOS_MAC_CONFIGURATION_TE | EQOS_MAC_CONFIGURATION_RE);
1537
1538 /* Wait for all RX packets to drain out of MTL */
1539 for (i = 0; i < 1000000; i++) {
1540 u32 val = readl(&eqos->mtl_regs->rxq0_debug);
1541 u32 prxq = (val >> EQOS_MTL_RXQ0_DEBUG_PRXQ_SHIFT) &
1542 EQOS_MTL_RXQ0_DEBUG_PRXQ_MASK;
1543 u32 rxqsts = (val >> EQOS_MTL_RXQ0_DEBUG_RXQSTS_SHIFT) &
1544 EQOS_MTL_RXQ0_DEBUG_RXQSTS_MASK;
1545 if ((!prxq) && (!rxqsts))
1546 break;
1547 }
1548
1549 /* Turn off RX DMA */
1550 clrbits_le32(&eqos->dma_regs->ch0_rx_control,
1551 EQOS_DMA_CH0_RX_CONTROL_SR);
1552
1553 if (eqos->phy) {
1554 phy_shutdown(eqos->phy);
1555 }
1556 if (eqos->config->ops->eqos_stop_clks)
1557 eqos->config->ops->eqos_stop_clks(dev);
1558
1559 debug("%s: OK\n", __func__);
1560 }
1561
eqos_send(struct udevice * dev,void * packet,int length)1562 int eqos_send(struct udevice *dev, void *packet, int length)
1563 {
1564 struct eqos_priv *eqos = dev_get_priv(dev);
1565 struct eqos_desc *tx_desc;
1566 int i;
1567
1568 debug("%s(dev=%p, packet=%p, length=%d):\n", __func__, dev, packet,
1569 length);
1570
1571 memcpy(eqos->tx_dma_buf, packet, length);
1572 eqos->config->ops->eqos_flush_buffer(eqos->tx_dma_buf, length);
1573
1574 tx_desc = &(eqos->tx_descs[eqos->tx_desc_idx]);
1575 eqos->tx_desc_idx++;
1576 eqos->tx_desc_idx %= EQOS_DESCRIPTORS_TX;
1577
1578 tx_desc->des0 = (ulong)eqos->tx_dma_buf;
1579 tx_desc->des1 = 0;
1580 tx_desc->des2 = length;
1581 /*
1582 * Make sure that if HW sees the _OWN write below, it will see all the
1583 * writes to the rest of the descriptor too.
1584 */
1585 mb();
1586 tx_desc->des3 = EQOS_DESC3_OWN | EQOS_DESC3_FD | EQOS_DESC3_LD | length;
1587 eqos->config->ops->eqos_flush_desc(tx_desc);
1588
1589 writel((ulong)(&(eqos->tx_descs[eqos->tx_desc_idx])),
1590 &eqos->dma_regs->ch0_txdesc_tail_pointer);
1591
1592 for (i = 0; i < 1000000; i++) {
1593 eqos->config->ops->eqos_inval_desc(tx_desc);
1594 if (!(readl(&tx_desc->des3) & EQOS_DESC3_OWN))
1595 return 0;
1596 udelay(1);
1597 }
1598
1599 debug("%s: TX timeout\n", __func__);
1600
1601 return -ETIMEDOUT;
1602 }
1603
eqos_recv(struct udevice * dev,int flags,uchar ** packetp)1604 int eqos_recv(struct udevice *dev, int flags, uchar **packetp)
1605 {
1606 struct eqos_priv *eqos = dev_get_priv(dev);
1607 struct eqos_desc *rx_desc;
1608 int length;
1609
1610 debug("%s(dev=%p, flags=%x):\n", __func__, dev, flags);
1611
1612 rx_desc = &(eqos->rx_descs[eqos->rx_desc_idx]);
1613 eqos->config->ops->eqos_inval_desc(rx_desc);
1614 if (rx_desc->des3 & EQOS_DESC3_OWN) {
1615 debug("%s: RX packet not available\n", __func__);
1616 return -EAGAIN;
1617 }
1618
1619 *packetp = eqos->rx_dma_buf +
1620 (eqos->rx_desc_idx * EQOS_MAX_PACKET_SIZE);
1621 length = rx_desc->des3 & 0x7fff;
1622 debug("%s: *packetp=%p, length=%d\n", __func__, *packetp, length);
1623
1624 eqos->config->ops->eqos_inval_buffer(*packetp, length);
1625
1626 return length;
1627 }
1628
eqos_free_pkt(struct udevice * dev,uchar * packet,int length)1629 int eqos_free_pkt(struct udevice *dev, uchar *packet, int length)
1630 {
1631 struct eqos_priv *eqos = dev_get_priv(dev);
1632 uchar *packet_expected;
1633 struct eqos_desc *rx_desc;
1634
1635 debug("%s(packet=%p, length=%d)\n", __func__, packet, length);
1636
1637 packet_expected = eqos->rx_dma_buf +
1638 (eqos->rx_desc_idx * EQOS_MAX_PACKET_SIZE);
1639 if (packet != packet_expected) {
1640 debug("%s: Unexpected packet (expected %p)\n", __func__,
1641 packet_expected);
1642 return -EINVAL;
1643 }
1644
1645 eqos->config->ops->eqos_inval_buffer(packet, length);
1646
1647 rx_desc = &(eqos->rx_descs[eqos->rx_desc_idx]);
1648
1649 rx_desc->des0 = 0;
1650 mb();
1651 eqos->config->ops->eqos_flush_desc(rx_desc);
1652 eqos->config->ops->eqos_inval_buffer(packet, length);
1653 rx_desc->des0 = (u32)(ulong)packet;
1654 rx_desc->des1 = 0;
1655 rx_desc->des2 = 0;
1656 /*
1657 * Make sure that if HW sees the _OWN write below, it will see all the
1658 * writes to the rest of the descriptor too.
1659 */
1660 mb();
1661 rx_desc->des3 = EQOS_DESC3_OWN | EQOS_DESC3_BUF1V;
1662 eqos->config->ops->eqos_flush_desc(rx_desc);
1663
1664 writel((ulong)rx_desc, &eqos->dma_regs->ch0_rxdesc_tail_pointer);
1665
1666 eqos->rx_desc_idx++;
1667 eqos->rx_desc_idx %= EQOS_DESCRIPTORS_RX;
1668
1669 return 0;
1670 }
1671
eqos_probe_resources_core(struct udevice * dev)1672 static int eqos_probe_resources_core(struct udevice *dev)
1673 {
1674 struct eqos_priv *eqos = dev_get_priv(dev);
1675 int ret;
1676
1677 debug("%s(dev=%p):\n", __func__, dev);
1678
1679 eqos->descs = eqos_alloc_descs(EQOS_DESCRIPTORS_TX +
1680 EQOS_DESCRIPTORS_RX);
1681 if (!eqos->descs) {
1682 debug("%s: eqos_alloc_descs() failed\n", __func__);
1683 ret = -ENOMEM;
1684 goto err;
1685 }
1686 eqos->tx_descs = (struct eqos_desc *)eqos->descs;
1687 eqos->rx_descs = (eqos->tx_descs + EQOS_DESCRIPTORS_TX);
1688 debug("%s: tx_descs=%p, rx_descs=%p\n", __func__, eqos->tx_descs,
1689 eqos->rx_descs);
1690
1691 eqos->tx_dma_buf = memalign(EQOS_BUFFER_ALIGN, EQOS_MAX_PACKET_SIZE);
1692 if (!eqos->tx_dma_buf) {
1693 debug("%s: memalign(tx_dma_buf) failed\n", __func__);
1694 ret = -ENOMEM;
1695 goto err_free_descs;
1696 }
1697 debug("%s: tx_dma_buf=%p\n", __func__, eqos->tx_dma_buf);
1698
1699 eqos->rx_dma_buf = memalign(EQOS_BUFFER_ALIGN, EQOS_RX_BUFFER_SIZE);
1700 if (!eqos->rx_dma_buf) {
1701 debug("%s: memalign(rx_dma_buf) failed\n", __func__);
1702 ret = -ENOMEM;
1703 goto err_free_tx_dma_buf;
1704 }
1705 debug("%s: rx_dma_buf=%p\n", __func__, eqos->rx_dma_buf);
1706
1707 eqos->rx_pkt = malloc(EQOS_MAX_PACKET_SIZE);
1708 if (!eqos->rx_pkt) {
1709 debug("%s: malloc(rx_pkt) failed\n", __func__);
1710 ret = -ENOMEM;
1711 goto err_free_rx_dma_buf;
1712 }
1713 debug("%s: rx_pkt=%p\n", __func__, eqos->rx_pkt);
1714
1715 eqos->config->ops->eqos_inval_buffer(eqos->rx_dma_buf,
1716 EQOS_MAX_PACKET_SIZE * EQOS_DESCRIPTORS_RX);
1717
1718 debug("%s: OK\n", __func__);
1719 return 0;
1720
1721 err_free_rx_dma_buf:
1722 free(eqos->rx_dma_buf);
1723 err_free_tx_dma_buf:
1724 free(eqos->tx_dma_buf);
1725 err_free_descs:
1726 eqos_free_descs(eqos->descs);
1727 err:
1728
1729 debug("%s: returns %d\n", __func__, ret);
1730 return ret;
1731 }
1732
eqos_remove_resources_core(struct udevice * dev)1733 static int eqos_remove_resources_core(struct udevice *dev)
1734 {
1735 struct eqos_priv *eqos = dev_get_priv(dev);
1736
1737 debug("%s(dev=%p):\n", __func__, dev);
1738
1739 free(eqos->rx_pkt);
1740 free(eqos->rx_dma_buf);
1741 free(eqos->tx_dma_buf);
1742 eqos_free_descs(eqos->descs);
1743
1744 debug("%s: OK\n", __func__);
1745 return 0;
1746 }
1747
1748 #ifdef CONFIG_QOS_FULL
eqos_probe_resources_tegra186(struct udevice * dev)1749 static int eqos_probe_resources_tegra186(struct udevice *dev)
1750 {
1751 struct eqos_priv *eqos = dev_get_priv(dev);
1752 int ret;
1753
1754 debug("%s(dev=%p):\n", __func__, dev);
1755
1756 ret = reset_get_by_name(dev, "eqos", &eqos->reset_ctl);
1757 if (ret) {
1758 pr_err("reset_get_by_name(rst) failed: %d", ret);
1759 return ret;
1760 }
1761
1762 ret = gpio_request_by_name(dev, "phy-reset-gpios", 0,
1763 &eqos->phy_reset_gpio,
1764 GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE);
1765 if (ret) {
1766 pr_err("gpio_request_by_name(phy reset) failed: %d", ret);
1767 goto err_free_reset_eqos;
1768 }
1769
1770 ret = clk_get_by_name(dev, "slave_bus", &eqos->clk_slave_bus);
1771 if (ret) {
1772 pr_err("clk_get_by_name(slave_bus) failed: %d", ret);
1773 goto err_free_gpio_phy_reset;
1774 }
1775
1776 ret = clk_get_by_name(dev, "master_bus", &eqos->clk_master_bus);
1777 if (ret) {
1778 pr_err("clk_get_by_name(master_bus) failed: %d", ret);
1779 goto err_free_clk_slave_bus;
1780 }
1781
1782 ret = clk_get_by_name(dev, "rx", &eqos->clk_rx);
1783 if (ret) {
1784 pr_err("clk_get_by_name(rx) failed: %d", ret);
1785 goto err_free_clk_master_bus;
1786 }
1787
1788 ret = clk_get_by_name(dev, "ptp_ref", &eqos->clk_ptp_ref);
1789 if (ret) {
1790 pr_err("clk_get_by_name(ptp_ref) failed: %d", ret);
1791 goto err_free_clk_rx;
1792 return ret;
1793 }
1794
1795 ret = clk_get_by_name(dev, "tx", &eqos->clk_tx);
1796 if (ret) {
1797 pr_err("clk_get_by_name(tx) failed: %d", ret);
1798 goto err_free_clk_ptp_ref;
1799 }
1800
1801 debug("%s: OK\n", __func__);
1802 return 0;
1803
1804 err_free_clk_ptp_ref:
1805 clk_free(&eqos->clk_ptp_ref);
1806 err_free_clk_rx:
1807 clk_free(&eqos->clk_rx);
1808 err_free_clk_master_bus:
1809 clk_free(&eqos->clk_master_bus);
1810 err_free_clk_slave_bus:
1811 clk_free(&eqos->clk_slave_bus);
1812 err_free_gpio_phy_reset:
1813 dm_gpio_free(dev, &eqos->phy_reset_gpio);
1814 err_free_reset_eqos:
1815 reset_free(&eqos->reset_ctl);
1816
1817 debug("%s: returns %d\n", __func__, ret);
1818 return ret;
1819 }
1820 #endif
1821
1822 /* board-specific Ethernet Interface initializations. */
board_interface_eth_init(struct udevice * dev,phy_interface_t interface_type)1823 __weak int board_interface_eth_init(struct udevice *dev,
1824 phy_interface_t interface_type)
1825 {
1826 return 0;
1827 }
1828
eqos_probe_resources_stm32(struct udevice * dev)1829 static int eqos_probe_resources_stm32(struct udevice *dev)
1830 {
1831 struct eqos_priv *eqos = dev_get_priv(dev);
1832 int ret;
1833 phy_interface_t interface;
1834 struct ofnode_phandle_args phandle_args;
1835
1836 debug("%s(dev=%p):\n", __func__, dev);
1837
1838 interface = eqos->config->ops->eqos_get_interface(dev);
1839
1840 if (interface == PHY_INTERFACE_MODE_NONE) {
1841 pr_err("Invalid PHY interface\n");
1842 return -EINVAL;
1843 }
1844
1845 ret = board_interface_eth_init(dev, interface);
1846 if (ret)
1847 return -EINVAL;
1848
1849 eqos->max_speed = dev_read_u32_default(dev, "max-speed", 0);
1850
1851 ret = clk_get_by_name(dev, "stmmaceth", &eqos->clk_master_bus);
1852 if (ret) {
1853 pr_err("clk_get_by_name(master_bus) failed: %d", ret);
1854 return ret;
1855 }
1856
1857 ret = clk_get_by_name(dev, "mac-clk-rx", &eqos->clk_rx);
1858 if (ret)
1859 pr_warn("clk_get_by_name(rx) failed: %d", ret);
1860
1861 ret = clk_get_by_name(dev, "mac-clk-tx", &eqos->clk_tx);
1862 if (ret)
1863 pr_warn("clk_get_by_name(tx) failed: %d", ret);
1864
1865 /* Get ETH_CLK clocks (optional) */
1866 ret = clk_get_by_name(dev, "eth-ck", &eqos->clk_ck);
1867 if (ret)
1868 pr_warn("No phy clock provided %d", ret);
1869
1870 eqos->phyaddr = -1;
1871 ret = dev_read_phandle_with_args(dev, "phy-handle", NULL, 0, 0,
1872 &phandle_args);
1873 if (!ret) {
1874 /* search "reset-gpios" in phy node */
1875 ret = gpio_request_by_name_nodev(phandle_args.node,
1876 "reset-gpios", 0,
1877 &eqos->phy_reset_gpio,
1878 GPIOD_IS_OUT |
1879 GPIOD_IS_OUT_ACTIVE);
1880 if (ret)
1881 pr_warn("gpio_request_by_name(phy reset) not provided %d",
1882 ret);
1883 else
1884 eqos->reset_delays[1] = 2;
1885
1886 eqos->phyaddr = ofnode_read_u32_default(phandle_args.node,
1887 "reg", -1);
1888 }
1889
1890 if (!dm_gpio_is_valid(&eqos->phy_reset_gpio)) {
1891 int reset_flags = GPIOD_IS_OUT;
1892
1893 if (dev_read_bool(dev, "snps,reset-active-low"))
1894 reset_flags |= GPIOD_ACTIVE_LOW;
1895
1896 ret = gpio_request_by_name(dev, "snps,reset-gpio", 0,
1897 &eqos->phy_reset_gpio, reset_flags);
1898 if (ret == 0)
1899 ret = dev_read_u32_array(dev, "snps,reset-delays-us",
1900 eqos->reset_delays, 3);
1901 else
1902 pr_warn("gpio_request_by_name(snps,reset-gpio) failed: %d",
1903 ret);
1904 }
1905
1906 debug("%s: OK\n", __func__);
1907 return 0;
1908 }
1909
eqos_get_interface_stm32(struct udevice * dev)1910 static phy_interface_t eqos_get_interface_stm32(struct udevice *dev)
1911 {
1912 const char *phy_mode;
1913 phy_interface_t interface = PHY_INTERFACE_MODE_NONE;
1914
1915 debug("%s(dev=%p):\n", __func__, dev);
1916
1917 phy_mode = dev_read_string(dev, "phy-mode");
1918 if (phy_mode)
1919 interface = phy_get_interface_by_name(phy_mode);
1920
1921 return interface;
1922 }
1923
1924 #ifdef CONFIG_QOS_FULL
eqos_get_interface_tegra186(struct udevice * dev)1925 static phy_interface_t eqos_get_interface_tegra186(struct udevice *dev)
1926 {
1927 return PHY_INTERFACE_MODE_MII;
1928 }
1929
eqos_probe_resources_imx(struct udevice * dev)1930 static int eqos_probe_resources_imx(struct udevice *dev)
1931 {
1932 struct eqos_priv *eqos = dev_get_priv(dev);
1933 phy_interface_t interface;
1934
1935 debug("%s(dev=%p):\n", __func__, dev);
1936
1937 interface = eqos->config->ops->eqos_get_interface(dev);
1938
1939 if (interface == PHY_INTERFACE_MODE_NONE) {
1940 pr_err("Invalid PHY interface\n");
1941 return -EINVAL;
1942 }
1943
1944 debug("%s: OK\n", __func__);
1945 return 0;
1946 }
1947
eqos_get_interface_imx(struct udevice * dev)1948 static phy_interface_t eqos_get_interface_imx(struct udevice *dev)
1949 {
1950 const char *phy_mode;
1951 phy_interface_t interface = PHY_INTERFACE_MODE_NONE;
1952
1953 debug("%s(dev=%p):\n", __func__, dev);
1954
1955 phy_mode = fdt_getprop(gd->fdt_blob, dev_of_offset(dev), "phy-mode",
1956 NULL);
1957 if (phy_mode)
1958 interface = phy_get_interface_by_name(phy_mode);
1959
1960 return interface;
1961 }
1962
eqos_remove_resources_tegra186(struct udevice * dev)1963 static int eqos_remove_resources_tegra186(struct udevice *dev)
1964 {
1965 struct eqos_priv *eqos = dev_get_priv(dev);
1966
1967 debug("%s(dev=%p):\n", __func__, dev);
1968
1969 #ifdef CONFIG_CLK
1970 clk_free(&eqos->clk_tx);
1971 clk_free(&eqos->clk_ptp_ref);
1972 clk_free(&eqos->clk_rx);
1973 clk_free(&eqos->clk_slave_bus);
1974 clk_free(&eqos->clk_master_bus);
1975 #endif
1976 dm_gpio_free(dev, &eqos->phy_reset_gpio);
1977 reset_free(&eqos->reset_ctl);
1978
1979 debug("%s: OK\n", __func__);
1980 return 0;
1981 }
1982 #endif
1983
eqos_remove_resources_stm32(struct udevice * dev)1984 static int eqos_remove_resources_stm32(struct udevice *dev)
1985 {
1986 #ifdef CONFIG_CLK
1987 struct eqos_priv *eqos = dev_get_priv(dev);
1988
1989 debug("%s(dev=%p):\n", __func__, dev);
1990
1991 if (clk_valid(&eqos->clk_tx))
1992 clk_free(&eqos->clk_tx);
1993 if (clk_valid(&eqos->clk_rx))
1994 clk_free(&eqos->clk_rx);
1995 clk_free(&eqos->clk_master_bus);
1996 if (clk_valid(&eqos->clk_ck))
1997 clk_free(&eqos->clk_ck);
1998 #endif
1999
2000 if (dm_gpio_is_valid(&eqos->phy_reset_gpio))
2001 dm_gpio_free(dev, &eqos->phy_reset_gpio);
2002
2003 debug("%s: OK\n", __func__);
2004 return 0;
2005 }
2006
2007 #ifdef CONFIG_QOS_FULL
eqos_remove_resources_imx(struct udevice * dev)2008 static int eqos_remove_resources_imx(struct udevice *dev)
2009 {
2010 return 0;
2011 }
2012 #endif
2013
eqos_probe(struct udevice * dev)2014 int eqos_probe(struct udevice *dev)
2015 {
2016 struct eqos_priv *eqos = dev_get_priv(dev);
2017 int ret;
2018
2019 debug("%s(dev=%p):\n", __func__, dev);
2020
2021 eqos->dev = dev;
2022 eqos->config = (void *)dev_get_driver_data(dev);
2023
2024 eqos->regs = dev_read_addr(dev);
2025 if (eqos->regs == FDT_ADDR_T_NONE) {
2026 pr_err("dev_read_addr() failed");
2027 return -ENODEV;
2028 }
2029 eqos->mac_regs = (void *)(eqos->regs + EQOS_MAC_REGS_BASE);
2030 eqos->mtl_regs = (void *)(eqos->regs + EQOS_MTL_REGS_BASE);
2031 eqos->dma_regs = (void *)(eqos->regs + EQOS_DMA_REGS_BASE);
2032 eqos->tegra186_regs = (void *)(eqos->regs + EQOS_TEGRA186_REGS_BASE);
2033
2034 ret = eqos_probe_resources_core(dev);
2035 if (ret < 0) {
2036 pr_err("eqos_probe_resources_core() failed: %d", ret);
2037 return ret;
2038 }
2039
2040 ret = eqos->config->ops->eqos_probe_resources(dev);
2041 if (ret < 0) {
2042 pr_err("eqos_probe_resources() failed: %d", ret);
2043 goto err_remove_resources_core;
2044 }
2045
2046 #ifdef CONFIG_DM_ETH_PHY
2047 eqos->mii = eth_phy_get_mdio_bus(dev);
2048 #endif
2049 if (!eqos->mii) {
2050 eqos->mii = mdio_alloc();
2051 if (!eqos->mii) {
2052 pr_err("mdio_alloc() failed");
2053 ret = -ENOMEM;
2054 goto err_remove_resources_tegra;
2055 }
2056 eqos->mii->read = eqos_mdio_read;
2057 eqos->mii->write = eqos_mdio_write;
2058 eqos->mii->priv = eqos;
2059 strcpy(eqos->mii->name, dev->name);
2060
2061 ret = mdio_register(eqos->mii);
2062 if (ret < 0) {
2063 pr_err("mdio_register() failed: %d", ret);
2064 goto err_free_mdio;
2065 }
2066 }
2067
2068 #ifdef CONFIG_DM_ETH_PHY
2069 eth_phy_set_mdio_bus(dev, eqos->mii);
2070 #endif
2071
2072 debug("%s: OK\n", __func__);
2073 return 0;
2074
2075 err_free_mdio:
2076 mdio_free(eqos->mii);
2077 err_remove_resources_tegra:
2078 eqos->config->ops->eqos_remove_resources(dev);
2079 err_remove_resources_core:
2080 eqos_remove_resources_core(dev);
2081
2082 debug("%s: returns %d\n", __func__, ret);
2083 return ret;
2084 }
2085
eqos_remove(struct udevice * dev)2086 static int __maybe_unused eqos_remove(struct udevice *dev)
2087 {
2088 struct eqos_priv *eqos = dev_get_priv(dev);
2089
2090 debug("%s(dev=%p):\n", __func__, dev);
2091
2092 mdio_unregister(eqos->mii);
2093 mdio_free(eqos->mii);
2094 eqos->config->ops->eqos_remove_resources(dev);
2095
2096 eqos_probe_resources_core(dev);
2097
2098 debug("%s: OK\n", __func__);
2099 return 0;
2100 }
2101
2102 #ifdef CONFIG_QOS_FULL
2103 static const struct eth_ops eqos_ops = {
2104 .start = eqos_start,
2105 .stop = eqos_stop,
2106 .send = eqos_send,
2107 .recv = eqos_recv,
2108 .free_pkt = eqos_free_pkt,
2109 .write_hwaddr = eqos_write_hwaddr,
2110 .read_rom_hwaddr = eqos_read_rom_hwaddr,
2111 };
2112
2113 static struct eqos_ops eqos_tegra186_ops = {
2114 .eqos_inval_desc = eqos_inval_desc_tegra186,
2115 .eqos_flush_desc = eqos_flush_desc_tegra186,
2116 .eqos_inval_buffer = eqos_inval_buffer_tegra186,
2117 .eqos_flush_buffer = eqos_flush_buffer_tegra186,
2118 .eqos_probe_resources = eqos_probe_resources_tegra186,
2119 .eqos_remove_resources = eqos_remove_resources_tegra186,
2120 .eqos_stop_resets = eqos_stop_resets_tegra186,
2121 .eqos_start_resets = eqos_start_resets_tegra186,
2122 .eqos_stop_clks = eqos_stop_clks_tegra186,
2123 .eqos_start_clks = eqos_start_clks_tegra186,
2124 .eqos_calibrate_pads = eqos_calibrate_pads_tegra186,
2125 .eqos_disable_calibration = eqos_disable_calibration_tegra186,
2126 .eqos_set_tx_clk_speed = eqos_set_tx_clk_speed_tegra186,
2127 .eqos_get_tick_clk_rate = eqos_get_tick_clk_rate_tegra186,
2128 .eqos_get_interface = eqos_get_interface_tegra186
2129 };
2130
2131 static const struct eqos_config eqos_tegra186_config = {
2132 .reg_access_always_ok = false,
2133 .mdio_wait = 10,
2134 .swr_wait = 10,
2135 .config_mac = EQOS_MAC_RXQ_CTRL0_RXQ0EN_ENABLED_DCB,
2136 .config_mac_mdio = EQOS_MAC_MDIO_ADDRESS_CR_20_35,
2137 .ops = &eqos_tegra186_ops
2138 };
2139
2140 static struct eqos_ops eqos_stm32_ops = {
2141 .eqos_inval_desc = eqos_inval_desc_generic,
2142 .eqos_flush_desc = eqos_flush_desc_generic,
2143 .eqos_inval_buffer = eqos_inval_buffer_generic,
2144 .eqos_flush_buffer = eqos_flush_buffer_generic,
2145 .eqos_probe_resources = eqos_probe_resources_stm32,
2146 .eqos_remove_resources = eqos_remove_resources_stm32,
2147 .eqos_stop_resets = eqos_stop_resets_stm32,
2148 .eqos_start_resets = eqos_start_resets_stm32,
2149 .eqos_stop_clks = eqos_stop_clks_stm32,
2150 .eqos_start_clks = eqos_start_clks_stm32,
2151 .eqos_calibrate_pads = eqos_calibrate_pads_stm32,
2152 .eqos_disable_calibration = eqos_disable_calibration_stm32,
2153 .eqos_set_tx_clk_speed = eqos_set_tx_clk_speed_stm32,
2154 .eqos_get_tick_clk_rate = eqos_get_tick_clk_rate_stm32,
2155 .eqos_get_interface = eqos_get_interface_stm32
2156 };
2157
2158 static const struct eqos_config eqos_stm32_config = {
2159 .reg_access_always_ok = false,
2160 .mdio_wait = 10000,
2161 .swr_wait = 50,
2162 .config_mac = EQOS_MAC_RXQ_CTRL0_RXQ0EN_ENABLED_AV,
2163 .config_mac_mdio = EQOS_MAC_MDIO_ADDRESS_CR_250_300,
2164 .ops = &eqos_stm32_ops
2165 };
2166
2167 static struct eqos_ops eqos_imx_ops = {
2168 .eqos_inval_desc = eqos_inval_desc_generic,
2169 .eqos_flush_desc = eqos_flush_desc_generic,
2170 .eqos_inval_buffer = eqos_inval_buffer_generic,
2171 .eqos_flush_buffer = eqos_flush_buffer_generic,
2172 .eqos_probe_resources = eqos_probe_resources_imx,
2173 .eqos_remove_resources = eqos_remove_resources_imx,
2174 .eqos_stop_resets = eqos_stop_resets_imx,
2175 .eqos_start_resets = eqos_start_resets_imx,
2176 .eqos_stop_clks = eqos_stop_clks_imx,
2177 .eqos_start_clks = eqos_start_clks_imx,
2178 .eqos_calibrate_pads = eqos_calibrate_pads_imx,
2179 .eqos_disable_calibration = eqos_disable_calibration_imx,
2180 .eqos_set_tx_clk_speed = eqos_set_tx_clk_speed_imx,
2181 .eqos_get_tick_clk_rate = eqos_get_tick_clk_rate_imx,
2182 .eqos_get_interface = eqos_get_interface_imx
2183 };
2184
2185 struct eqos_config eqos_imx_config = {
2186 .reg_access_always_ok = false,
2187 .mdio_wait = 10000,
2188 .swr_wait = 50,
2189 .config_mac = EQOS_MAC_RXQ_CTRL0_RXQ0EN_ENABLED_DCB,
2190 .config_mac_mdio = EQOS_MAC_MDIO_ADDRESS_CR_250_300,
2191 .ops = &eqos_imx_ops
2192 };
2193 #endif
2194
2195 struct eqos_ops eqos_rockchip_ops = {
2196 .eqos_inval_desc = eqos_inval_desc_generic,
2197 .eqos_flush_desc = eqos_flush_desc_generic,
2198 .eqos_inval_buffer = eqos_inval_buffer_generic,
2199 .eqos_flush_buffer = eqos_flush_buffer_generic,
2200 .eqos_probe_resources = eqos_probe_resources_stm32,
2201 .eqos_remove_resources = eqos_remove_resources_stm32,
2202 .eqos_stop_resets = eqos_stop_resets_stm32,
2203 .eqos_start_resets = eqos_start_resets_stm32,
2204 .eqos_calibrate_pads = eqos_calibrate_pads_stm32,
2205 .eqos_disable_calibration = eqos_disable_calibration_stm32,
2206 .eqos_set_tx_clk_speed = eqos_set_tx_clk_speed_stm32,
2207 .eqos_get_tick_clk_rate = eqos_get_tick_clk_rate_stm32,
2208 .eqos_get_interface = eqos_get_interface_stm32
2209 };
2210
2211 #ifdef CONFIG_QOS_FULL
2212 static const struct udevice_id eqos_ids[] = {
2213 {
2214 .compatible = "nvidia,tegra186-eqos",
2215 .data = (ulong)&eqos_tegra186_config
2216 },
2217 {
2218 .compatible = "snps,dwmac-4.20a",
2219 .data = (ulong)&eqos_stm32_config
2220 },
2221 {
2222 .compatible = "fsl,imx-eqos",
2223 .data = (ulong)&eqos_imx_config
2224 },
2225
2226 { }
2227 };
2228
2229 U_BOOT_DRIVER(eth_eqos) = {
2230 .name = "eth_eqos",
2231 .id = UCLASS_ETH,
2232 .of_match = of_match_ptr(eqos_ids),
2233 .probe = eqos_probe,
2234 .remove = eqos_remove,
2235 .ops = &eqos_ops,
2236 .priv_auto_alloc_size = sizeof(struct eqos_priv),
2237 .platdata_auto_alloc_size = sizeof(struct eth_pdata),
2238 };
2239 #endif
2240