1 /* 2 * (C) Copyright 2011 NVIDIA Corporation <www.nvidia.com> 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 /* register offset */ 8 #define COMMAND_0 0x00 9 #define CMD_GO (1 << 31) 10 #define CMD_CLE (1 << 30) 11 #define CMD_ALE (1 << 29) 12 #define CMD_PIO (1 << 28) 13 #define CMD_TX (1 << 27) 14 #define CMD_RX (1 << 26) 15 #define CMD_SEC_CMD (1 << 25) 16 #define CMD_AFT_DAT_MASK (1 << 24) 17 #define CMD_AFT_DAT_DISABLE 0 18 #define CMD_AFT_DAT_ENABLE (1 << 24) 19 #define CMD_TRANS_SIZE_SHIFT 20 20 #define CMD_TRANS_SIZE_PAGE 8 21 #define CMD_A_VALID (1 << 19) 22 #define CMD_B_VALID (1 << 18) 23 #define CMD_RD_STATUS_CHK (1 << 17) 24 #define CMD_R_BSY_CHK (1 << 16) 25 #define CMD_CE7 (1 << 15) 26 #define CMD_CE6 (1 << 14) 27 #define CMD_CE5 (1 << 13) 28 #define CMD_CE4 (1 << 12) 29 #define CMD_CE3 (1 << 11) 30 #define CMD_CE2 (1 << 10) 31 #define CMD_CE1 (1 << 9) 32 #define CMD_CE0 (1 << 8) 33 #define CMD_CLE_BYTE_SIZE_SHIFT 4 34 enum { 35 CMD_CLE_BYTES1 = 0, 36 CMD_CLE_BYTES2, 37 CMD_CLE_BYTES3, 38 CMD_CLE_BYTES4, 39 }; 40 #define CMD_ALE_BYTE_SIZE_SHIFT 0 41 enum { 42 CMD_ALE_BYTES1 = 0, 43 CMD_ALE_BYTES2, 44 CMD_ALE_BYTES3, 45 CMD_ALE_BYTES4, 46 CMD_ALE_BYTES5, 47 CMD_ALE_BYTES6, 48 CMD_ALE_BYTES7, 49 CMD_ALE_BYTES8 50 }; 51 52 #define STATUS_0 0x04 53 #define STATUS_RBSY0 (1 << 8) 54 55 #define ISR_0 0x08 56 #define ISR_IS_CMD_DONE (1 << 5) 57 #define ISR_IS_ECC_ERR (1 << 4) 58 59 #define IER_0 0x0C 60 61 #define CFG_0 0x10 62 #define CFG_HW_ECC_MASK (1 << 31) 63 #define CFG_HW_ECC_DISABLE 0 64 #define CFG_HW_ECC_ENABLE (1 << 31) 65 #define CFG_HW_ECC_SEL_MASK (1 << 30) 66 #define CFG_HW_ECC_SEL_HAMMING 0 67 #define CFG_HW_ECC_SEL_RS (1 << 30) 68 #define CFG_HW_ECC_CORRECTION_MASK (1 << 29) 69 #define CFG_HW_ECC_CORRECTION_DISABLE 0 70 #define CFG_HW_ECC_CORRECTION_ENABLE (1 << 29) 71 #define CFG_PIPELINE_EN_MASK (1 << 28) 72 #define CFG_PIPELINE_EN_DISABLE 0 73 #define CFG_PIPELINE_EN_ENABLE (1 << 28) 74 #define CFG_ECC_EN_TAG_MASK (1 << 27) 75 #define CFG_ECC_EN_TAG_DISABLE 0 76 #define CFG_ECC_EN_TAG_ENABLE (1 << 27) 77 #define CFG_TVALUE_MASK (3 << 24) 78 enum { 79 CFG_TVAL4 = 0 << 24, 80 CFG_TVAL6 = 1 << 24, 81 CFG_TVAL8 = 2 << 24 82 }; 83 #define CFG_SKIP_SPARE_MASK (1 << 23) 84 #define CFG_SKIP_SPARE_DISABLE 0 85 #define CFG_SKIP_SPARE_ENABLE (1 << 23) 86 #define CFG_COM_BSY_MASK (1 << 22) 87 #define CFG_COM_BSY_DISABLE 0 88 #define CFG_COM_BSY_ENABLE (1 << 22) 89 #define CFG_BUS_WIDTH_MASK (1 << 21) 90 #define CFG_BUS_WIDTH_8BIT 0 91 #define CFG_BUS_WIDTH_16BIT (1 << 21) 92 #define CFG_LPDDR1_MODE_MASK (1 << 20) 93 #define CFG_LPDDR1_MODE_DISABLE 0 94 #define CFG_LPDDR1_MODE_ENABLE (1 << 20) 95 #define CFG_EDO_MODE_MASK (1 << 19) 96 #define CFG_EDO_MODE_DISABLE 0 97 #define CFG_EDO_MODE_ENABLE (1 << 19) 98 #define CFG_PAGE_SIZE_SEL_MASK (7 << 16) 99 enum { 100 CFG_PAGE_SIZE_256 = 0 << 16, 101 CFG_PAGE_SIZE_512 = 1 << 16, 102 CFG_PAGE_SIZE_1024 = 2 << 16, 103 CFG_PAGE_SIZE_2048 = 3 << 16, 104 CFG_PAGE_SIZE_4096 = 4 << 16 105 }; 106 #define CFG_SKIP_SPARE_SEL_MASK (3 << 14) 107 enum { 108 CFG_SKIP_SPARE_SEL_4 = 0 << 14, 109 CFG_SKIP_SPARE_SEL_8 = 1 << 14, 110 CFG_SKIP_SPARE_SEL_12 = 2 << 14, 111 CFG_SKIP_SPARE_SEL_16 = 3 << 14 112 }; 113 #define CFG_TAG_BYTE_SIZE_MASK 0x1FF 114 115 #define TIMING_0 0x14 116 #define TIMING_TRP_RESP_CNT_SHIFT 28 117 #define TIMING_TRP_RESP_CNT_MASK (0xf << TIMING_TRP_RESP_CNT_SHIFT) 118 #define TIMING_TWB_CNT_SHIFT 24 119 #define TIMING_TWB_CNT_MASK (0xf << TIMING_TWB_CNT_SHIFT) 120 #define TIMING_TCR_TAR_TRR_CNT_SHIFT 20 121 #define TIMING_TCR_TAR_TRR_CNT_MASK (0xf << TIMING_TCR_TAR_TRR_CNT_SHIFT) 122 #define TIMING_TWHR_CNT_SHIFT 16 123 #define TIMING_TWHR_CNT_MASK (0xf << TIMING_TWHR_CNT_SHIFT) 124 #define TIMING_TCS_CNT_SHIFT 14 125 #define TIMING_TCS_CNT_MASK (3 << TIMING_TCS_CNT_SHIFT) 126 #define TIMING_TWH_CNT_SHIFT 12 127 #define TIMING_TWH_CNT_MASK (3 << TIMING_TWH_CNT_SHIFT) 128 #define TIMING_TWP_CNT_SHIFT 8 129 #define TIMING_TWP_CNT_MASK (0xf << TIMING_TWP_CNT_SHIFT) 130 #define TIMING_TRH_CNT_SHIFT 4 131 #define TIMING_TRH_CNT_MASK (3 << TIMING_TRH_CNT_SHIFT) 132 #define TIMING_TRP_CNT_SHIFT 0 133 #define TIMING_TRP_CNT_MASK (0xf << TIMING_TRP_CNT_SHIFT) 134 135 #define RESP_0 0x18 136 137 #define TIMING2_0 0x1C 138 #define TIMING2_TADL_CNT_SHIFT 0 139 #define TIMING2_TADL_CNT_MASK (0xf << TIMING2_TADL_CNT_SHIFT) 140 141 #define CMD_REG1_0 0x20 142 #define CMD_REG2_0 0x24 143 #define ADDR_REG1_0 0x28 144 #define ADDR_REG2_0 0x2C 145 146 #define DMA_MST_CTRL_0 0x30 147 #define DMA_MST_CTRL_GO_MASK (1 << 31) 148 #define DMA_MST_CTRL_GO_DISABLE 0 149 #define DMA_MST_CTRL_GO_ENABLE (1 << 31) 150 #define DMA_MST_CTRL_DIR_MASK (1 << 30) 151 #define DMA_MST_CTRL_DIR_READ 0 152 #define DMA_MST_CTRL_DIR_WRITE (1 << 30) 153 #define DMA_MST_CTRL_PERF_EN_MASK (1 << 29) 154 #define DMA_MST_CTRL_PERF_EN_DISABLE 0 155 #define DMA_MST_CTRL_PERF_EN_ENABLE (1 << 29) 156 #define DMA_MST_CTRL_REUSE_BUFFER_MASK (1 << 27) 157 #define DMA_MST_CTRL_REUSE_BUFFER_DISABLE 0 158 #define DMA_MST_CTRL_REUSE_BUFFER_ENABLE (1 << 27) 159 #define DMA_MST_CTRL_BURST_SIZE_SHIFT 24 160 #define DMA_MST_CTRL_BURST_SIZE_MASK (7 << DMA_MST_CTRL_BURST_SIZE_SHIFT) 161 enum { 162 DMA_MST_CTRL_BURST_1WORDS = 2 << DMA_MST_CTRL_BURST_SIZE_SHIFT, 163 DMA_MST_CTRL_BURST_4WORDS = 3 << DMA_MST_CTRL_BURST_SIZE_SHIFT, 164 DMA_MST_CTRL_BURST_8WORDS = 4 << DMA_MST_CTRL_BURST_SIZE_SHIFT, 165 DMA_MST_CTRL_BURST_16WORDS = 5 << DMA_MST_CTRL_BURST_SIZE_SHIFT 166 }; 167 #define DMA_MST_CTRL_IS_DMA_DONE (1 << 20) 168 #define DMA_MST_CTRL_EN_A_MASK (1 << 2) 169 #define DMA_MST_CTRL_EN_A_DISABLE 0 170 #define DMA_MST_CTRL_EN_A_ENABLE (1 << 2) 171 #define DMA_MST_CTRL_EN_B_MASK (1 << 1) 172 #define DMA_MST_CTRL_EN_B_DISABLE 0 173 #define DMA_MST_CTRL_EN_B_ENABLE (1 << 1) 174 175 #define DMA_CFG_A_0 0x34 176 #define DMA_CFG_B_0 0x38 177 #define FIFO_CTRL_0 0x3C 178 #define DATA_BLOCK_PTR_0 0x40 179 #define TAG_PTR_0 0x44 180 #define ECC_PTR_0 0x48 181 182 #define DEC_STATUS_0 0x4C 183 #define DEC_STATUS_A_ECC_FAIL (1 << 1) 184 #define DEC_STATUS_B_ECC_FAIL (1 << 0) 185 186 #define BCH_CONFIG_0 0xCC 187 #define BCH_CONFIG_BCH_TVALUE_SHIFT 4 188 #define BCH_CONFIG_BCH_TVALUE_MASK (3 << BCH_CONFIG_BCH_TVALUE_SHIFT) 189 enum { 190 BCH_CONFIG_BCH_TVAL4 = 0 << BCH_CONFIG_BCH_TVALUE_SHIFT, 191 BCH_CONFIG_BCH_TVAL8 = 1 << BCH_CONFIG_BCH_TVALUE_SHIFT, 192 BCH_CONFIG_BCH_TVAL14 = 2 << BCH_CONFIG_BCH_TVALUE_SHIFT, 193 BCH_CONFIG_BCH_TVAL16 = 3 << BCH_CONFIG_BCH_TVALUE_SHIFT 194 }; 195 #define BCH_CONFIG_BCH_ECC_MASK (1 << 0) 196 #define BCH_CONFIG_BCH_ECC_DISABLE 0 197 #define BCH_CONFIG_BCH_ECC_ENABLE (1 << 0) 198 199 #define BCH_DEC_RESULT_0 0xD0 200 #define BCH_DEC_RESULT_CORRFAIL_ERR_MASK (1 << 8) 201 #define BCH_DEC_RESULT_PAGE_COUNT_MASK 0xFF 202 203 #define BCH_DEC_STATUS_BUF_0 0xD4 204 #define BCH_DEC_STATUS_FAIL_SEC_FLAG_MASK 0xFF000000 205 #define BCH_DEC_STATUS_CORR_SEC_FLAG_MASK 0x00FF0000 206 #define BCH_DEC_STATUS_FAIL_TAG_MASK (1 << 14) 207 #define BCH_DEC_STATUS_CORR_TAG_MASK (1 << 13) 208 #define BCH_DEC_STATUS_MAX_CORR_CNT_MASK (0x1f << 8) 209 #define BCH_DEC_STATUS_PAGE_NUMBER_MASK 0xFF 210 211 #define LP_OPTIONS 0 212 213 struct nand_ctlr { 214 u32 command; /* offset 00h */ 215 u32 status; /* offset 04h */ 216 u32 isr; /* offset 08h */ 217 u32 ier; /* offset 0Ch */ 218 u32 config; /* offset 10h */ 219 u32 timing; /* offset 14h */ 220 u32 resp; /* offset 18h */ 221 u32 timing2; /* offset 1Ch */ 222 u32 cmd_reg1; /* offset 20h */ 223 u32 cmd_reg2; /* offset 24h */ 224 u32 addr_reg1; /* offset 28h */ 225 u32 addr_reg2; /* offset 2Ch */ 226 u32 dma_mst_ctrl; /* offset 30h */ 227 u32 dma_cfg_a; /* offset 34h */ 228 u32 dma_cfg_b; /* offset 38h */ 229 u32 fifo_ctrl; /* offset 3Ch */ 230 u32 data_block_ptr; /* offset 40h */ 231 u32 tag_ptr; /* offset 44h */ 232 u32 resv1; /* offset 48h */ 233 u32 dec_status; /* offset 4Ch */ 234 u32 hwstatus_cmd; /* offset 50h */ 235 u32 hwstatus_mask; /* offset 54h */ 236 u32 resv2[29]; 237 u32 bch_config; /* offset CCh */ 238 u32 bch_dec_result; /* offset D0h */ 239 u32 bch_dec_status_buf; 240 /* offset D4h */ 241 }; 242