1 /*
2 * Copyright (c) 2017 Yifeng Zhao <yifeng.zhao@rock-chips.com>
3 *
4 * SPDX-License-Identifier: GPL-2.0+
5 */
6
7 #include <common.h>
8 #include <dm.h>
9 #include <fdtdec.h>
10 #include <fdt_support.h>
11 #include <inttypes.h>
12 #include <nand.h>
13 #include <linux/kernel.h>
14 #include <linux/mtd/mtd.h>
15 #include <linux/mtd/nand.h>
16 #include <linux/mtd/partitions.h>
17 #include <linux/io.h>
18
19 DECLARE_GLOBAL_DATA_PTR;
20
21 #define NANDC_V6_BOOTROM_ECC 24
22 #define NANDC_V6_NUM_BANKS 4
23 #define NANDC_V6_DEF_TIMEOUT 20000
24 #define NANDC_V6_READ 0
25 #define NANDC_V6_WRITE 1
26
27 #define NANDC_REG_V6_FMCTL 0x00
28 #define NANDC_REG_V6_FMWAIT 0x04
29 #define NANDC_REG_V6_FLCTL 0x08
30 #define NANDC_REG_V6_BCHCTL 0x0c
31 #define NANDC_REG_V6_DMA_CFG 0x10
32 #define NANDC_REG_V6_DMA_BUF0 0x14
33 #define NANDC_REG_V6_DMA_BUF1 0x18
34 #define NANDC_REG_V6_DMA_ST 0x1C
35 #define NANDC_REG_V6_BCHST 0x20
36 #define NANDC_REG_V6_RANDMZ 0x150
37 #define NANDC_REG_V6_VER 0x160
38 #define NANDC_REG_V6_INTEN 0x16C
39 #define NANDC_REG_V6_INTCLR 0x170
40 #define NANDC_REG_V6_INTST 0x174
41 #define NANDC_REG_V6_SPARE0 0x200
42 #define NANDC_REG_V6_SPARE1 0x230
43 #define NANDC_REG_V6_BANK0 0x800
44 #define NANDC_REG_V6_SRAM0 0x1000
45 #define NANDC_REG_V6_SRAM_SIZE 0x400
46
47 #define NANDC_REG_V6_DATA 0x00
48 #define NANDC_REG_V6_ADDR 0x04
49 #define NANDC_REG_V6_CMD 0x08
50
51 /* FMCTL */
52 #define NANDC_V6_FM_WP BIT(8)
53 #define NANDC_V6_FM_CE_SEL_M 0xFF
54 #define NANDC_V6_FM_CE_SEL(x) (1 << (x))
55 #define NANDC_V6_FM_FREADY BIT(9)
56
57 /* FLCTL */
58 #define NANDC_V6_FL_RST BIT(0)
59 #define NANDC_V6_FL_DIR_S 0x1
60 #define NANDC_V6_FL_XFER_START BIT(2)
61 #define NANDC_V6_FL_XFER_EN BIT(3)
62 #define NANDC_V6_FL_ST_BUF_S 0x4
63 #define NANDC_V6_FL_XFER_COUNT BIT(5)
64 #define NANDC_V6_FL_ACORRECT BIT(10)
65 #define NANDC_V6_FL_XFER_READY BIT(20)
66
67 /* BCHCTL */
68 #define NAND_V6_BCH_REGION_S 0x5
69 #define NAND_V6_BCH_REGION_M 0x7
70
71 /* BCHST */
72 #define NANDC_V6_BCH0_ST_ERR BIT(2)
73 #define NANDC_V6_BCH1_ST_ERR BIT(15)
74 #define NANDC_V6_ECC_ERR_CNT0(x) ((((x & (0x1F << 3)) >> 3) \
75 | ((x & (1 << 27)) >> 22)) & 0x3F)
76 #define NANDC_V6_ECC_ERR_CNT1(x) ((((x & (0x1F << 16)) >> 16) \
77 | ((x & (1 << 29)) >> 24)) & 0x3F)
78
79 struct rk_nand {
80 void __iomem *regs;
81 u8 chipnr;
82 u8 id[5];
83 u8 *databuf;
84 struct udevice *dev;
85 struct mtd_info *mtd;
86 };
87
88 static struct rk_nand *g_rk_nand;
89 static u32 nand_page_size;
90 static u32 nand_page_num;
91 static u32 nand_block_num;
92
nandc_init(struct rk_nand * rknand)93 static void nandc_init(struct rk_nand *rknand)
94 {
95 writel(0x1081, rknand->regs + NANDC_REG_V6_FMWAIT);
96 }
97
rockchip_nand_wait_dev_ready(void __iomem * regs)98 static void rockchip_nand_wait_dev_ready(void __iomem *regs)
99 {
100 u32 reg;
101 u32 timeout = NANDC_V6_DEF_TIMEOUT;
102
103 while (timeout--) {
104 udelay(1);
105 reg = readl(regs + NANDC_REG_V6_FMCTL);
106
107 if ((reg & NANDC_V6_FM_FREADY))
108 break;
109 }
110 }
111
rockchip_nand_select_chip(void __iomem * regs,int chipnr)112 static void rockchip_nand_select_chip(void __iomem *regs, int chipnr)
113 {
114 u32 reg;
115
116 reg = readl(regs + NANDC_REG_V6_FMCTL);
117 reg &= ~NANDC_V6_FM_CE_SEL_M;
118 if (chipnr != -1)
119 reg |= 1 << chipnr;
120 writel(reg, regs + NANDC_REG_V6_FMCTL);
121 }
122
rockchip_nand_read_page(void __iomem * regs,int page,int col)123 static void rockchip_nand_read_page(void __iomem *regs,
124 int page, int col)
125 {
126 void __iomem *bank_base = regs + NANDC_REG_V6_BANK0;
127
128 writeb(0x00, bank_base + NANDC_REG_V6_CMD);
129 writeb(col, bank_base + NANDC_REG_V6_ADDR);
130 writeb(col >> 8, bank_base + NANDC_REG_V6_ADDR);
131 writeb(page, bank_base + NANDC_REG_V6_ADDR);
132 writeb(page >> 8, bank_base + NANDC_REG_V6_ADDR);
133 writeb(page >> 16, bank_base + NANDC_REG_V6_ADDR);
134 writeb(0x30, bank_base + NANDC_REG_V6_CMD);
135 }
136
rockchip_nand_pio_xfer_start(struct rk_nand * rknand,u8 dir,u8 st_buf)137 static void rockchip_nand_pio_xfer_start(struct rk_nand *rknand,
138 u8 dir,
139 u8 st_buf)
140 {
141 u32 reg;
142
143 reg = readl(rknand->regs + NANDC_REG_V6_BCHCTL);
144 reg = (reg & (~(NAND_V6_BCH_REGION_M << NAND_V6_BCH_REGION_S)));
145 writel(reg, rknand->regs + NANDC_REG_V6_BCHCTL);
146
147 reg = (dir << NANDC_V6_FL_DIR_S) | (st_buf << NANDC_V6_FL_ST_BUF_S) |
148 NANDC_V6_FL_XFER_EN | NANDC_V6_FL_XFER_COUNT |
149 NANDC_V6_FL_ACORRECT;
150 writel(reg, rknand->regs + NANDC_REG_V6_FLCTL);
151
152 reg |= NANDC_V6_FL_XFER_START;
153 writel(reg, rknand->regs + NANDC_REG_V6_FLCTL);
154 }
155
rockchip_nand_wait_pio_xfer_done(struct rk_nand * rknand)156 static int rockchip_nand_wait_pio_xfer_done(struct rk_nand *rknand)
157 {
158 int timeout = NANDC_V6_DEF_TIMEOUT;
159 int reg;
160
161 while (timeout--) {
162 reg = readl(rknand->regs + NANDC_REG_V6_FLCTL);
163
164 if ((reg & NANDC_V6_FL_XFER_READY) != 0)
165 break;
166
167 udelay(1);
168 }
169
170 if (timeout == 0)
171 return -1;
172
173 return 0;
174 }
175
nandc_read_page(unsigned int page,uint8_t * buf)176 static int nandc_read_page(unsigned int page, uint8_t *buf)
177 {
178 void __iomem *sram_base = g_rk_nand->regs + NANDC_REG_V6_SRAM0;
179 unsigned int max_bitflips = 0;
180 int ret, step, bch_st, ecc_step;
181
182 ecc_step = nand_page_size / 1024;
183 rockchip_nand_select_chip(g_rk_nand->regs, 0);
184 rockchip_nand_read_page(g_rk_nand->regs, page, 0);
185 rockchip_nand_wait_dev_ready(g_rk_nand->regs);
186 rockchip_nand_pio_xfer_start(g_rk_nand, NANDC_V6_READ, 0);
187
188 for (step = 0; step < ecc_step; step++) {
189 int data_off = step * 1024;
190 u8 *data = buf + data_off;
191
192 ret = rockchip_nand_wait_pio_xfer_done(g_rk_nand);
193 if (ret)
194 return ret;
195
196 bch_st = readl(g_rk_nand->regs + NANDC_REG_V6_BCHST);
197
198 if (bch_st & NANDC_V6_BCH0_ST_ERR) {
199 max_bitflips = -1;
200 } else {
201 ret = NANDC_V6_ECC_ERR_CNT0(bch_st);
202 max_bitflips = max_t(unsigned int, max_bitflips, ret);
203 }
204
205 if ((step + 1) < ecc_step)
206 rockchip_nand_pio_xfer_start(g_rk_nand, NANDC_V6_READ,
207 (step + 1) & 0x1);
208
209 memcpy_fromio(data, sram_base + NANDC_REG_V6_SRAM_SIZE *
210 (step & 1), 1024);
211 }
212 rockchip_nand_select_chip(g_rk_nand->regs, -1);
213
214 return max_bitflips;
215 }
216
is_badblock(unsigned int page)217 static int is_badblock(unsigned int page)
218 {
219 int res = 0, i;
220 u16 bad = 0xff;
221 void __iomem *regs = g_rk_nand->regs;
222 void __iomem *bank_base = regs + NANDC_REG_V6_BANK0;
223
224 if (nandc_read_page(page, g_rk_nand->databuf) == -1) {
225 rockchip_nand_select_chip(regs, 0);
226 rockchip_nand_read_page(regs, page, nand_page_size);
227 rockchip_nand_wait_dev_ready(regs);
228 for (i = 0; i < 8; i++) {
229 bad = readb(bank_base);
230 if (bad)
231 break;
232 }
233 if (i >= 8)
234 res = 1;
235 rockchip_nand_select_chip(regs, 0);
236 }
237 if (res)
238 printf("%s 0x%x %x %x\n", __func__, page, res, bad);
239 return res;
240 }
241
read_flash_id(struct rk_nand * rknand,uint8_t * id)242 static void read_flash_id(struct rk_nand *rknand, uint8_t *id)
243 {
244 void __iomem *bank_base = rknand->regs + NANDC_REG_V6_BANK0;
245
246 rockchip_nand_wait_dev_ready(g_rk_nand->regs);
247 writeb(0x90, bank_base + NANDC_REG_V6_CMD);
248 writeb(0x00, bank_base + NANDC_REG_V6_ADDR);
249 udelay(1);
250 id[0] = readb(bank_base);
251 id[1] = readb(bank_base);
252 id[2] = readb(bank_base);
253 id[3] = readb(bank_base);
254 id[4] = readb(bank_base);
255 rockchip_nand_select_chip(rknand->regs, -1);
256 if (id[0] != 0xFF && id[0] != 0x00)
257 printf("NAND:%x %x\n", id[0], id[1]);
258 }
259
260 #ifdef CONFIG_NAND_ROCKCHIP_DT
261 static const struct udevice_id rockchip_nandc_ids[] = {
262 { .compatible = "rockchip,rk-nandc" },
263 { }
264 };
265
spl_nand_block_isbad(struct mtd_info * mtd,loff_t ofs)266 static int spl_nand_block_isbad(struct mtd_info *mtd, loff_t ofs)
267 {
268 return is_badblock((u32)ofs / nand_page_size);
269 }
270
spl_nand_read_page(struct mtd_info * mtd,loff_t from,size_t len,size_t * retlen,u_char * buf)271 static int spl_nand_read_page(struct mtd_info *mtd, loff_t from, size_t len,
272 size_t *retlen, u_char *buf)
273 {
274 int read_size, offset, read_len;
275 unsigned int page;
276 unsigned int max_pages = nand_page_num * nand_block_num;
277
278 /* Convert to page number */
279 page = (u32)from / nand_page_size;
280 offset = from & (nand_page_size - 1);
281 read_len = len;
282 *retlen = 0;
283
284 while (read_len) {
285 read_size = nand_page_size - offset;
286 if (read_size > read_len)
287 read_size = read_len;
288 if (offset || read_size < nand_page_size) {
289 if (nandc_read_page(page, g_rk_nand->databuf) < 0)
290 return -EIO;
291 memcpy(buf, g_rk_nand->databuf + offset, read_size);
292 offset = 0;
293 } else {
294 if (nandc_read_page(page, buf) < 0)
295 return -EIO;
296 }
297 page++;
298 read_len -= read_size;
299 buf += read_size;
300 if (page >= max_pages)
301 return -EIO;
302 }
303
304 *retlen = len;
305
306 return 0;
307 }
308
rockchip_nandc_probe(struct udevice * dev)309 static int rockchip_nandc_probe(struct udevice *dev)
310 {
311 const void *blob = gd->fdt_blob;
312 struct rk_nand *rknand = dev_get_priv(dev);
313 struct mtd_info *mtd = dev_get_uclass_priv(dev);
314 fdt_addr_t regs;
315 int ret = -ENODEV;
316 int node;
317 u8 *id;
318
319 g_rk_nand = rknand;
320 rknand->dev = dev;
321
322 node = fdtdec_next_compatible(blob, 0, COMPAT_ROCKCHIP_NANDC);
323
324 if (node < 0) {
325 printf("Nand node not found\n");
326 return -ENODEV;
327 }
328
329 if (!fdtdec_get_is_enabled(blob, node)) {
330 debug("Nand disabled in device tree\n");
331 return -ENODEV;
332 }
333
334 regs = fdt_get_base_address(blob, node);
335 if (!regs) {
336 debug("Nand address not found\n");
337 return -ENODEV;
338 }
339
340 rknand->regs = (void *)regs;
341
342 nandc_init(g_rk_nand);
343 read_flash_id(g_rk_nand, g_rk_nand->id);
344
345 id = g_rk_nand->id;
346 if (id[0] == id[1])
347 return -ENODEV;
348
349 if (id[1] == 0xA1 || id[1] == 0xF1 ||
350 id[1] == 0xD1 || id[1] == 0xAA ||
351 id[1] == 0xDA || id[1] == 0xAC ||
352 id[1] == 0xDC || id[1] == 0xA3 ||
353 id[1] == 0xD3 || id[1] == 0x95 ||
354 id[1] == 0x48) {
355 nand_page_size = 2048;
356 nand_page_num = 64;
357 nand_block_num = 1024;
358 if (id[1] == 0xDC) {
359 if ((id[0] == 0x2C && id[3] == 0xA6) ||
360 (id[0] == 0xC2 && id[3] == 0xA2)) {
361 nand_page_size = 4096;
362 nand_block_num = 2048;
363 } else if (id[0] == 0x98 && id[3] == 0x26) {
364 nand_page_size = 4096;
365 nand_block_num = 2048;
366 } else {
367 nand_block_num = 4096;
368 }
369 } else if (id[1] == 0xDA) {
370 nand_block_num = 2048;
371 } else if (id[1] == 0x48) {
372 nand_page_size = 4096;
373 nand_page_num = 128;
374 nand_block_num = 4096;
375 } else if (id[1] == 0xD3) {
376 if ((id[2] == 0xD1 && id[4] == 0x5a) || /* S34ML08G2 */
377 (id[3] == 0x05 && id[4] == 0x04)) { /* S34ML08G3 */
378 nand_block_num = 8192;
379 } else {
380 nand_page_size = 4096;
381 nand_block_num = 4096;
382 }
383 }
384
385 g_rk_nand->chipnr = 1;
386 g_rk_nand->databuf = kzalloc(nand_page_size, GFP_KERNEL);
387 if (!g_rk_nand)
388 return -ENOMEM;
389 mtd->_block_isbad = spl_nand_block_isbad;
390 mtd->_read = spl_nand_read_page;
391 mtd->size = (size_t)nand_page_size * nand_page_num *
392 nand_block_num;
393 mtd->writesize = nand_page_size;
394 mtd->erasesize = nand_page_size * nand_page_num;
395 mtd->erasesize_shift = ffs(mtd->erasesize) - 1;
396 mtd->erasesize_mask = (1 << mtd->erasesize_shift) - 1;
397 mtd->type = MTD_NANDFLASH;
398 mtd->dev = rknand->dev;
399 mtd->priv = rknand;
400 add_mtd_device(mtd);
401 rknand->mtd = mtd;
402 ret = 0;
403 }
404
405 return ret;
406 }
407
rockchip_nandc_bind(struct udevice * udev)408 static int rockchip_nandc_bind(struct udevice *udev)
409 {
410 int ret = 0;
411
412 #ifdef CONFIG_MTD_BLK
413 struct udevice *bdev;
414
415 ret = blk_create_devicef(udev, "mtd_blk", "blk", IF_TYPE_MTD,
416 BLK_MTD_NAND, 512, 0, &bdev);
417 if (ret)
418 printf("Cannot create block device\n");
419 #endif
420 return ret;
421 }
422
423 U_BOOT_DRIVER(rk_nandc_v6) = {
424 .name = "rk_nandc_v6",
425 .id = UCLASS_MTD,
426 .of_match = rockchip_nandc_ids,
427 .bind = rockchip_nandc_bind,
428 .probe = rockchip_nandc_probe,
429 .priv_auto_alloc_size = sizeof(struct rk_nand),
430 };
431
board_nand_init(void)432 void board_nand_init(void)
433 {
434 struct udevice *dev;
435 int ret;
436
437 ret = uclass_get_device_by_driver(UCLASS_MTD,
438 DM_GET_DRIVER(rk_nandc_v6),
439 &dev);
440 if (ret && ret != -ENODEV)
441 pr_err("Failed to initialize NAND controller. (error %d)\n",
442 ret);
443 }
444
nand_spl_load_image(u32 offs,u32 size,void * buf)445 int nand_spl_load_image(u32 offs, u32 size, void *buf)
446 {
447 return -EIO;
448 }
449
nand_init(void)450 void nand_init(void){};
451
rk_nand_init(void)452 int rk_nand_init(void)
453 {
454 return -ENODEV;
455 }
456
457 #else
board_nand_init(void)458 void board_nand_init(void)
459 {
460 const void *blob = gd->fdt_blob;
461 static int initialized;
462 fdt_addr_t regs;
463 int node;
464
465 if (initialized)
466 return;
467
468 initialized = 1;
469 nand_page_size = CONFIG_SYS_NAND_PAGE_SIZE;
470 nand_page_num = CONFIG_SYS_NAND_PAGE_COUNT;
471
472 if (g_rk_nand)
473 return;
474
475 node = fdtdec_next_compatible(blob, 0, COMPAT_ROCKCHIP_NANDC);
476
477 if (node < 0) {
478 printf("Nand node not found\n");
479 return;
480 }
481
482 if (!fdtdec_get_is_enabled(blob, node)) {
483 debug("Nand disabled in device tree\n");
484 return;
485 }
486
487 regs = fdt_get_base_address(blob, node);
488 if (!regs) {
489 debug("Nand address not found\n");
490 return;
491 }
492
493 g_rk_nand = kzalloc(sizeof(*g_rk_nand), GFP_KERNEL);
494 g_rk_nand->regs = (void *)regs;
495 g_rk_nand->databuf = kzalloc(nand_page_size, GFP_KERNEL);
496 nandc_init(g_rk_nand);
497 read_flash_id(g_rk_nand, g_rk_nand->id);
498
499 if (g_rk_nand->id[0] == g_rk_nand->id[1])
500 goto err;
501
502 if (g_rk_nand->id[1] == 0xA1 || g_rk_nand->id[1] == 0xF1 ||
503 g_rk_nand->id[1] == 0xD1 || g_rk_nand->id[1] == 0xAA ||
504 g_rk_nand->id[1] == 0xDA || g_rk_nand->id[1] == 0xAC ||
505 g_rk_nand->id[1] == 0xDC || g_rk_nand->id[1] == 0xA3 ||
506 g_rk_nand->id[1] == 0xD3 || g_rk_nand->id[1] == 0x95 ||
507 g_rk_nand->id[1] == 0x48) {
508 g_rk_nand->chipnr = 1;
509 return;
510 }
511
512 err:
513 kfree(g_rk_nand->databuf);
514 kfree(g_rk_nand);
515 g_rk_nand = NULL;
516 }
517
nand_spl_load_image(u32 offs,u32 size,void * buf)518 int nand_spl_load_image(u32 offs, u32 size, void *buf)
519 {
520 int i;
521 unsigned int page;
522 int force_bad_block_check = 1;
523 unsigned int maxpages = CONFIG_SYS_NAND_SIZE /
524 nand_page_size;
525
526 /* Convert to page number */
527 page = offs / nand_page_size;
528 i = 0;
529
530 size = roundup(size, nand_page_size);
531 while (i < size / nand_page_size) {
532 /*
533 * Check if we have crossed a block boundary, and if so
534 * check for bad block.
535 */
536 if (force_bad_block_check || !(page % nand_page_num)) {
537 /*
538 * Yes, new block. See if this block is good. If not,
539 * loop until we find a good block.
540 */
541 while (is_badblock(page)) {
542 page = page + nand_page_num;
543 /* Check i we've reached the end of flash. */
544 if (page >= maxpages)
545 return -EIO;
546 }
547 }
548
549 force_bad_block_check = 0;
550
551 if (nandc_read_page(page, buf) < 0)
552 return -EIO;
553
554 page++;
555 i++;
556 buf = buf + nand_page_size;
557 }
558 return 0;
559 }
560
nand_init(void)561 void nand_init(void)
562 {
563 board_nand_init();
564 }
565
rk_nand_init(void)566 int rk_nand_init(void)
567 {
568 board_nand_init();
569 if (g_rk_nand && g_rk_nand->chipnr)
570 return 0;
571 else
572 return -ENODEV;
573 }
574 #endif
575
nand_deselect(void)576 void nand_deselect(void) {}
577
578