1 /* 2 * (c) 2009 Magnus Lilja <lilja.magnus@gmail.com> 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #ifndef __MXC_NAND_H 8 #define __MXC_NAND_H 9 10 /* 11 * Register map and bit definitions for the Freescale NAND Flash Controller 12 * present in various i.MX devices. 13 * 14 * MX31 and MX27 have version 1, which has: 15 * 4 512-byte main buffers and 16 * 4 16-byte spare buffers 17 * to support up to 2K byte pagesize nand. 18 * Reading or writing a 2K page requires 4 FDI/FDO cycles. 19 * 20 * MX25 and MX35 have version 2.1, and MX51 and MX53 have version 3.2, which 21 * have: 22 * 8 512-byte main buffers and 23 * 8 64-byte spare buffers 24 * to support up to 4K byte pagesize nand. 25 * Reading or writing a 2K or 4K page requires only 1 FDI/FDO cycle. 26 * Also some of registers are moved and/or changed meaning as seen below. 27 */ 28 #if defined(CONFIG_MX27) || defined(CONFIG_MX31) 29 #define MXC_NFC_V1 30 #define is_mxc_nfc_1() 1 31 #define is_mxc_nfc_21() 0 32 #define is_mxc_nfc_32() 0 33 #elif defined(CONFIG_MX25) || defined(CONFIG_MX35) 34 #define MXC_NFC_V2_1 35 #define is_mxc_nfc_1() 0 36 #define is_mxc_nfc_21() 1 37 #define is_mxc_nfc_32() 0 38 #elif defined(CONFIG_MX51) || defined(CONFIG_MX53) 39 #define MXC_NFC_V3 40 #define MXC_NFC_V3_2 41 #define is_mxc_nfc_1() 0 42 #define is_mxc_nfc_21() 0 43 #define is_mxc_nfc_32() 1 44 #else 45 #error "MXC NFC implementation not supported" 46 #endif 47 #define is_mxc_nfc_3() is_mxc_nfc_32() 48 49 #if defined(MXC_NFC_V1) 50 #define NAND_MXC_NR_BUFS 4 51 #define NAND_MXC_SPARE_BUF_SIZE 16 52 #define NAND_MXC_REG_OFFSET 0xe00 53 #define NAND_MXC_2K_MULTI_CYCLE 54 #elif defined(MXC_NFC_V2_1) || defined(MXC_NFC_V3_2) 55 #define NAND_MXC_NR_BUFS 8 56 #define NAND_MXC_SPARE_BUF_SIZE 64 57 #define NAND_MXC_REG_OFFSET 0x1e00 58 #endif 59 60 struct mxc_nand_regs { 61 u8 main_area[NAND_MXC_NR_BUFS][0x200]; 62 u8 spare_area[NAND_MXC_NR_BUFS][NAND_MXC_SPARE_BUF_SIZE]; 63 /* 64 * reserved size is offset of nfc registers 65 * minus total main and spare sizes 66 */ 67 u8 reserved1[NAND_MXC_REG_OFFSET 68 - NAND_MXC_NR_BUFS * (512 + NAND_MXC_SPARE_BUF_SIZE)]; 69 #if defined(MXC_NFC_V1) 70 u16 buf_size; 71 u16 reserved2; 72 u16 buf_addr; 73 u16 flash_addr; 74 u16 flash_cmd; 75 u16 config; 76 u16 ecc_status_result; 77 u16 rsltmain_area; 78 u16 rsltspare_area; 79 u16 wrprot; 80 u16 unlockstart_blkaddr; 81 u16 unlockend_blkaddr; 82 u16 nf_wrprst; 83 u16 config1; 84 u16 config2; 85 #elif defined(MXC_NFC_V2_1) 86 u16 reserved2[2]; 87 u16 buf_addr; 88 u16 flash_addr; 89 u16 flash_cmd; 90 u16 config; 91 u32 ecc_status_result; 92 u16 spare_area_size; 93 u16 wrprot; 94 u16 reserved3[2]; 95 u16 nf_wrprst; 96 u16 config1; 97 u16 config2; 98 u16 reserved4; 99 u16 unlockstart_blkaddr; 100 u16 unlockend_blkaddr; 101 u16 unlockstart_blkaddr1; 102 u16 unlockend_blkaddr1; 103 u16 unlockstart_blkaddr2; 104 u16 unlockend_blkaddr2; 105 u16 unlockstart_blkaddr3; 106 u16 unlockend_blkaddr3; 107 #elif defined(MXC_NFC_V3_2) 108 u32 flash_cmd; 109 u32 flash_addr[12]; 110 u32 config1; 111 u32 ecc_status_result; 112 u32 status_sum; 113 u32 launch; 114 #endif 115 }; 116 117 #ifdef MXC_NFC_V3_2 118 struct mxc_nand_ip_regs { 119 u32 wrprot; 120 u32 wrprot_unlock_blkaddr[8]; 121 u32 config2; 122 u32 config3; 123 u32 ipc; 124 u32 err_addr; 125 u32 delay_line; 126 }; 127 #endif 128 129 /* Set FCMD to 1, rest to 0 for Command operation */ 130 #define NFC_CMD 0x1 131 132 /* Set FADD to 1, rest to 0 for Address operation */ 133 #define NFC_ADDR 0x2 134 135 /* Set FDI to 1, rest to 0 for Input operation */ 136 #define NFC_INPUT 0x4 137 138 /* Set FDO to 001, rest to 0 for Data Output operation */ 139 #define NFC_OUTPUT 0x8 140 141 /* Set FDO to 010, rest to 0 for Read ID operation */ 142 #define NFC_ID 0x10 143 144 /* Set FDO to 100, rest to 0 for Read Status operation */ 145 #define NFC_STATUS 0x20 146 147 #if defined(MXC_NFC_V1) || defined(MXC_NFC_V2_1) 148 #define NFC_CONFIG1_SP_EN (1 << 2) 149 #define NFC_CONFIG1_RST (1 << 6) 150 #define NFC_CONFIG1_CE (1 << 7) 151 #elif defined(MXC_NFC_V3_2) 152 #define NFC_CONFIG1_SP_EN (1 << 0) 153 #define NFC_CONFIG1_CE (1 << 1) 154 #define NFC_CONFIG1_RST (1 << 2) 155 #endif 156 #define NFC_V1_V2_CONFIG1_ECC_EN (1 << 3) 157 #define NFC_V1_V2_CONFIG1_INT_MSK (1 << 4) 158 #define NFC_V1_V2_CONFIG1_BIG (1 << 5) 159 #define NFC_V2_CONFIG1_ECC_MODE_4 (1 << 0) 160 #define NFC_V2_CONFIG1_ONE_CYCLE (1 << 8) 161 #define NFC_V2_CONFIG1_FP_INT (1 << 11) 162 #define NFC_V3_CONFIG1_RBA_MASK (0x7 << 4) 163 #define NFC_V3_CONFIG1_RBA(x) (((x) & 0x7) << 4) 164 165 #define NFC_V1_V2_CONFIG2_INT (1 << 15) 166 #define NFC_V3_CONFIG2_PS_MASK (0x3 << 0) 167 #define NFC_V3_CONFIG2_PS_512 (0 << 0) 168 #define NFC_V3_CONFIG2_PS_2048 (1 << 0) 169 #define NFC_V3_CONFIG2_PS_4096 (2 << 0) 170 #define NFC_V3_CONFIG2_ONE_CYCLE (1 << 2) 171 #define NFC_V3_CONFIG2_ECC_EN (1 << 3) 172 #define NFC_V3_CONFIG2_2CMD_PHASES (1 << 4) 173 #define NFC_V3_CONFIG2_NUM_ADDR_PH0 (1 << 5) 174 #define NFC_V3_CONFIG2_ECC_MODE_8 (1 << 6) 175 #define NFC_V3_CONFIG2_PPB_MASK (0x3 << 7) 176 #define NFC_V3_CONFIG2_PPB(x) (((x) & 0x3) << 7) 177 #define NFC_V3_CONFIG2_EDC_MASK (0x7 << 9) 178 #define NFC_V3_CONFIG2_EDC(x) (((x) & 0x7) << 9) 179 #define NFC_V3_CONFIG2_NUM_ADDR_PH1(x) (((x) & 0x3) << 12) 180 #define NFC_V3_CONFIG2_INT_MSK (1 << 15) 181 #define NFC_V3_CONFIG2_SPAS_MASK (0xff << 16) 182 #define NFC_V3_CONFIG2_SPAS(x) (((x) & 0xff) << 16) 183 #define NFC_V3_CONFIG2_ST_CMD_MASK (0xff << 24) 184 #define NFC_V3_CONFIG2_ST_CMD(x) (((x) & 0xff) << 24) 185 186 #define NFC_V3_CONFIG3_ADD_OP(x) (((x) & 0x3) << 0) 187 #define NFC_V3_CONFIG3_FW8 (1 << 3) 188 #define NFC_V3_CONFIG3_SBB(x) (((x) & 0x7) << 8) 189 #define NFC_V3_CONFIG3_NUM_OF_DEVS(x) (((x) & 0x7) << 12) 190 #define NFC_V3_CONFIG3_RBB_MODE (1 << 15) 191 #define NFC_V3_CONFIG3_NO_SDMA (1 << 20) 192 193 #define NFC_V3_WRPROT_UNLOCK (1 << 2) 194 #define NFC_V3_WRPROT_BLS_UNLOCK (2 << 6) 195 196 #define NFC_V3_IPC_CREQ (1 << 0) 197 #define NFC_V3_IPC_INT (1 << 31) 198 199 #if defined(MXC_NFC_V1) || defined(MXC_NFC_V2_1) 200 #define operation config2 201 #define readnfc readw 202 #define writenfc writew 203 #elif defined(MXC_NFC_V3_2) 204 #define operation launch 205 #define readnfc readl 206 #define writenfc writel 207 #endif 208 209 #endif /* __MXC_NAND_H */ 210