1 // SPDX-License-Identifier: GPL-2.0+
2
3 #include <common.h>
4 #include <asm/io.h>
5 #include <memalign.h>
6 #include <nand.h>
7 #include <linux/errno.h>
8 #include <linux/io.h>
9 #include <linux/ioport.h>
10 #include <dm.h>
11
12 #include "brcmnand.h"
13
14 struct bcm63158_nand_soc {
15 struct brcmnand_soc soc;
16 void __iomem *base;
17 };
18
19 #define BCM63158_NAND_INT 0x00
20 #define BCM63158_NAND_STATUS_SHIFT 0
21 #define BCM63158_NAND_STATUS_MASK (0xfff << BCM63158_NAND_STATUS_SHIFT)
22
23 #define BCM63158_NAND_INT_EN 0x04
24 #define BCM63158_NAND_ENABLE_SHIFT 0
25 #define BCM63158_NAND_ENABLE_MASK (0xffff << BCM63158_NAND_ENABLE_SHIFT)
26
27 enum {
28 BCM63158_NP_READ = BIT(0),
29 BCM63158_BLOCK_ERASE = BIT(1),
30 BCM63158_COPY_BACK = BIT(2),
31 BCM63158_PAGE_PGM = BIT(3),
32 BCM63158_CTRL_READY = BIT(4),
33 BCM63158_DEV_RBPIN = BIT(5),
34 BCM63158_ECC_ERR_UNC = BIT(6),
35 BCM63158_ECC_ERR_CORR = BIT(7),
36 };
37
bcm63158_nand_intc_ack(struct brcmnand_soc * soc)38 static bool bcm63158_nand_intc_ack(struct brcmnand_soc *soc)
39 {
40 struct bcm63158_nand_soc *priv =
41 container_of(soc, struct bcm63158_nand_soc, soc);
42 void __iomem *mmio = priv->base + BCM63158_NAND_INT;
43 u32 val = brcmnand_readl(mmio);
44
45 if (val & (BCM63158_CTRL_READY << BCM63158_NAND_STATUS_SHIFT)) {
46 /* Ack interrupt */
47 val &= ~BCM63158_NAND_STATUS_MASK;
48 val |= BCM63158_CTRL_READY << BCM63158_NAND_STATUS_SHIFT;
49 brcmnand_writel(val, mmio);
50 return true;
51 }
52
53 return false;
54 }
55
bcm63158_nand_intc_set(struct brcmnand_soc * soc,bool en)56 static void bcm63158_nand_intc_set(struct brcmnand_soc *soc, bool en)
57 {
58 struct bcm63158_nand_soc *priv =
59 container_of(soc, struct bcm63158_nand_soc, soc);
60 void __iomem *mmio = priv->base + BCM63158_NAND_INT_EN;
61 u32 val = brcmnand_readl(mmio);
62
63 /* Don't ack any interrupts */
64 val &= ~BCM63158_NAND_STATUS_MASK;
65
66 if (en)
67 val |= BCM63158_CTRL_READY << BCM63158_NAND_ENABLE_SHIFT;
68 else
69 val &= ~(BCM63158_CTRL_READY << BCM63158_NAND_ENABLE_SHIFT);
70
71 brcmnand_writel(val, mmio);
72 }
73
bcm63158_nand_probe(struct udevice * dev)74 static int bcm63158_nand_probe(struct udevice *dev)
75 {
76 struct udevice *pdev = dev;
77 struct bcm63158_nand_soc *priv = dev_get_priv(dev);
78 struct brcmnand_soc *soc;
79 struct resource res;
80
81 soc = &priv->soc;
82
83 dev_read_resource_byname(pdev, "nand-int-base", &res);
84 priv->base = devm_ioremap(dev, res.start, resource_size(&res));
85 if (IS_ERR(priv->base))
86 return PTR_ERR(priv->base);
87
88 soc->ctlrdy_ack = bcm63158_nand_intc_ack;
89 soc->ctlrdy_set_enabled = bcm63158_nand_intc_set;
90
91 /* Disable and ack all interrupts */
92 brcmnand_writel(0, priv->base + BCM63158_NAND_INT_EN);
93 brcmnand_writel(0, priv->base + BCM63158_NAND_INT);
94
95 return brcmnand_probe(pdev, soc);
96 }
97
98 static const struct udevice_id bcm63158_nand_dt_ids[] = {
99 {
100 .compatible = "brcm,nand-bcm63158",
101 },
102 { /* sentinel */ }
103 };
104
105 U_BOOT_DRIVER(bcm63158_nand) = {
106 .name = "bcm63158-nand",
107 .id = UCLASS_MTD,
108 .of_match = bcm63158_nand_dt_ids,
109 .probe = bcm63158_nand_probe,
110 .priv_auto_alloc_size = sizeof(struct bcm63158_nand_soc),
111 };
112
board_nand_init(void)113 void board_nand_init(void)
114 {
115 struct udevice *dev;
116 int ret;
117
118 ret = uclass_get_device_by_driver(UCLASS_MTD,
119 DM_GET_DRIVER(bcm63158_nand), &dev);
120 if (ret && ret != -ENODEV)
121 pr_err("Failed to initialize %s. (error %d)\n", dev->name,
122 ret);
123 }
124