1 /*
2 * (C) Copyright 2015 Google, Inc
3 *
4 * (C) Copyright 2008-2020 Rockchip Electronics
5 * Peter, Software Engineering, <superpeter.cai@gmail.com>.
6 * Jianqun Xu, Software Engineering, <jay.xu@rock-chips.com>.
7 *
8 * SPDX-License-Identifier: GPL-2.0+
9 */
10
11 #include <common.h>
12 #include <dm.h>
13 #include <dm/of_access.h>
14 #include <syscon.h>
15 #include <linux/errno.h>
16 #include <asm/gpio.h>
17 #include <asm/io.h>
18 #include <asm/arch/clock.h>
19 #include <dm/pinctrl.h>
20 #include <dt-bindings/clock/rk3288-cru.h>
21
22 #include "../pinctrl/rockchip/pinctrl-rockchip.h"
23
24 #define OFFSET_TO_BIT(bit) (1UL << (bit))
25
26 #ifdef CONFIG_ROCKCHIP_GPIO_V2
27 #define REG_L(R) (R##_l)
28 #define REG_H(R) (R##_h)
29 #define READ_REG(REG) ((readl(REG_L(REG)) & 0xFFFF) | \
30 ((readl(REG_H(REG)) & 0xFFFF) << 16))
31 #define WRITE_REG(REG, VAL) \
32 {\
33 writel(((VAL) & 0xFFFF) | 0xFFFF0000, REG_L(REG)); \
34 writel((((VAL) & 0xFFFF0000) >> 16) | 0xFFFF0000, REG_H(REG));\
35 }
36 #define CLRBITS_LE32(REG, MASK) WRITE_REG(REG, READ_REG(REG) & ~(MASK))
37 #define SETBITS_LE32(REG, MASK) WRITE_REG(REG, READ_REG(REG) | (MASK))
38 #define CLRSETBITS_LE32(REG, MASK, VAL) WRITE_REG(REG, \
39 (READ_REG(REG) & ~(MASK)) | (VAL))
40
41 #else
42 #define READ_REG(REG) readl(REG)
43 #define WRITE_REG(REG, VAL) writel(VAL, REG)
44 #define CLRBITS_LE32(REG, MASK) clrbits_le32(REG, MASK)
45 #define SETBITS_LE32(REG, MASK) setbits_le32(REG, MASK)
46 #define CLRSETBITS_LE32(REG, MASK, VAL) clrsetbits_le32(REG, MASK, VAL)
47 #endif
48
49
50 struct rockchip_gpio_priv {
51 struct rockchip_gpio_regs *regs;
52 struct udevice *pinctrl;
53 int bank;
54 char name[2];
55 };
56
rockchip_gpio_direction_input(struct udevice * dev,unsigned offset)57 static int rockchip_gpio_direction_input(struct udevice *dev, unsigned offset)
58 {
59 struct rockchip_gpio_priv *priv = dev_get_priv(dev);
60 struct rockchip_gpio_regs *regs = priv->regs;
61
62 CLRBITS_LE32(®s->swport_ddr, OFFSET_TO_BIT(offset));
63
64 return 0;
65 }
66
rockchip_gpio_direction_output(struct udevice * dev,unsigned offset,int value)67 static int rockchip_gpio_direction_output(struct udevice *dev, unsigned offset,
68 int value)
69 {
70 struct rockchip_gpio_priv *priv = dev_get_priv(dev);
71 struct rockchip_gpio_regs *regs = priv->regs;
72 int mask = OFFSET_TO_BIT(offset);
73
74 CLRSETBITS_LE32(®s->swport_dr, mask, value ? mask : 0);
75 SETBITS_LE32(®s->swport_ddr, mask);
76
77 return 0;
78 }
79
rockchip_gpio_get_value(struct udevice * dev,unsigned offset)80 static int rockchip_gpio_get_value(struct udevice *dev, unsigned offset)
81 {
82 struct rockchip_gpio_priv *priv = dev_get_priv(dev);
83 struct rockchip_gpio_regs *regs = priv->regs;
84
85 return readl(®s->ext_port) & OFFSET_TO_BIT(offset) ? 1 : 0;
86 }
87
rockchip_gpio_set_value(struct udevice * dev,unsigned offset,int value)88 static int rockchip_gpio_set_value(struct udevice *dev, unsigned offset,
89 int value)
90 {
91 struct rockchip_gpio_priv *priv = dev_get_priv(dev);
92 struct rockchip_gpio_regs *regs = priv->regs;
93 int mask = OFFSET_TO_BIT(offset);
94
95 CLRSETBITS_LE32(®s->swport_dr, mask, value ? mask : 0);
96
97 return 0;
98 }
99
rockchip_gpio_get_function(struct udevice * dev,unsigned offset)100 static int rockchip_gpio_get_function(struct udevice *dev, unsigned offset)
101 {
102 #ifdef CONFIG_SPL_BUILD
103 return -ENODATA;
104 #else
105 struct rockchip_gpio_priv *priv = dev_get_priv(dev);
106 struct rockchip_gpio_regs *regs = priv->regs;
107 bool is_output;
108 int ret;
109
110 ret = pinctrl_get_gpio_mux(priv->pinctrl, priv->bank, offset);
111 if (ret < 0) {
112 dev_err(dev, "fail to get gpio mux %d\n", ret);
113 return ret;
114 }
115
116 /* If it's not 0, then it is not a GPIO */
117 if (ret > 0)
118 return GPIOF_FUNC;
119
120 is_output = READ_REG(®s->swport_ddr) & OFFSET_TO_BIT(offset);
121
122 return is_output ? GPIOF_OUTPUT : GPIOF_INPUT;
123 #endif
124 }
125
rockchip_gpio_probe(struct udevice * dev)126 static int rockchip_gpio_probe(struct udevice *dev)
127 {
128 struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
129 struct rockchip_gpio_priv *priv = dev_get_priv(dev);
130 struct rockchip_pinctrl_priv *pctrl_priv;
131 struct rockchip_pin_bank *bank;
132 char *end = NULL;
133 int id = -1, ret;
134
135 priv->regs = dev_read_addr_ptr(dev);
136 ret = uclass_get_device_by_seq(UCLASS_PINCTRL, 0, &priv->pinctrl);
137 if (ret) {
138 ret = uclass_first_device_err(UCLASS_PINCTRL, &priv->pinctrl);
139 if (ret) {
140 dev_err(dev, "failed to get pinctrl device %d\n", ret);
141 return ret;
142 }
143 }
144
145 pctrl_priv = dev_get_priv(priv->pinctrl);
146 if (!pctrl_priv) {
147 dev_err(dev, "failed to get pinctrl priv\n");
148 return -EINVAL;
149 }
150
151 end = strrchr(dev->name, '@');
152 if (end)
153 id = trailing_strtoln(dev->name, end);
154 if (id < 0)
155 dev_read_alias_seq(dev, &id);
156
157 if (id < 0 || id >= pctrl_priv->ctrl->nr_banks) {
158 dev_err(dev, "nr_banks=%d, bank id=%d invalid\n",
159 pctrl_priv->ctrl->nr_banks, id);
160 return -EINVAL;
161 }
162
163 bank = &pctrl_priv->ctrl->pin_banks[id];
164 if (bank->bank_num != id) {
165 dev_err(dev, "bank id mismatch with pinctrl\n");
166 return -EINVAL;
167 }
168
169 priv->bank = bank->bank_num;
170 uc_priv->gpio_count = bank->nr_pins;
171 uc_priv->gpio_base = bank->pin_base;
172 uc_priv->bank_name = bank->name;
173
174 return 0;
175 }
176
177 static const struct dm_gpio_ops gpio_rockchip_ops = {
178 .direction_input = rockchip_gpio_direction_input,
179 .direction_output = rockchip_gpio_direction_output,
180 .get_value = rockchip_gpio_get_value,
181 .set_value = rockchip_gpio_set_value,
182 .get_function = rockchip_gpio_get_function,
183 };
184
185 static const struct udevice_id rockchip_gpio_ids[] = {
186 { .compatible = "rockchip,gpio-bank" },
187 { }
188 };
189
190 U_BOOT_DRIVER(gpio_rockchip) = {
191 .name = "gpio_rockchip",
192 .id = UCLASS_GPIO,
193 .of_match = rockchip_gpio_ids,
194 .ops = &gpio_rockchip_ops,
195 .priv_auto_alloc_size = sizeof(struct rockchip_gpio_priv),
196 .probe = rockchip_gpio_probe,
197 };
198