1 /* 2 * Copyright (C) Marvell International Ltd. and its affiliates 3 * 4 * SPDX-License-Identifier: GPL-2.0 5 */ 6 7 #ifndef _DDR3_HWS_HW_TRAINING_H 8 #define _DDR3_HWS_HW_TRAINING_H 9 10 /* struct used for DLB configuration array */ 11 struct dlb_config { 12 u32 reg_addr; 13 u32 reg_data; 14 }; 15 16 /* Topology update structure */ 17 struct topology_update_info { 18 int update_ecc; 19 u8 ecc; 20 int update_width; 21 u8 width; 22 int update_ecc_pup3_mode; 23 u8 ecc_pup_mode_offset; 24 }; 25 26 /* Topology update defines */ 27 #define TOPOLOGY_UPDATE_WIDTH_16BIT 1 28 #define TOPOLOGY_UPDATE_WIDTH_32BIT 0 29 #define TOPOLOGY_UPDATE_WIDTH_32BIT_MASK 0xf 30 #define TOPOLOGY_UPDATE_WIDTH_16BIT_MASK 0x3 31 32 #define TOPOLOGY_UPDATE_ECC_ON 1 33 #define TOPOLOGY_UPDATE_ECC_OFF 0 34 #define TOPOLOGY_UPDATE_ECC_OFFSET_PUP4 4 35 #define TOPOLOGY_UPDATE_ECC_OFFSET_PUP3 3 36 37 /* 38 * 1. L2 filter should be set at binary header to 0xd000000, 39 * to avoid conflict with internal register IO. 40 * 2. U-Boot modifies internal registers base to 0xf100000, 41 * and than should update L2 filter accordingly to 0xf000000 (3.75 GB) 42 */ 43 /* temporary limit l2 filter to 3GiB (LSP issue) */ 44 #define L2_FILTER_FOR_MAX_MEMORY_SIZE 0xc0000000 45 #define ADDRESS_FILTERING_END_REGISTER 0x8c04 46 47 #define SUB_VERSION 0 48 49 #endif /* _DDR3_HWS_HW_TRAINING_H */ 50