1 /*
2 * Copyright (C) 2016 Socionext Inc.
3 * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
4 *
5 * SPDX-License-Identifier: GPL-2.0+
6 */
7
8 #include <common.h>
9 #include <clk-uclass.h>
10 #include <dm.h>
11 #include <linux/bitops.h>
12 #include <linux/io.h>
13 #include <linux/sizes.h>
14
15 #include "clk-uniphier.h"
16
17 /**
18 * struct uniphier_clk_priv - private data for UniPhier clock driver
19 *
20 * @base: base address of the clock provider
21 * @data: SoC specific data
22 */
23 struct uniphier_clk_priv {
24 void __iomem *base;
25 const struct uniphier_clk_data *data;
26 };
27
uniphier_clk_enable(struct clk * clk)28 static int uniphier_clk_enable(struct clk *clk)
29 {
30 struct uniphier_clk_priv *priv = dev_get_priv(clk->dev);
31 unsigned long id = clk->id;
32 const struct uniphier_clk_gate_data *p;
33
34 for (p = priv->data->gate; p->id != UNIPHIER_CLK_ID_END; p++) {
35 u32 val;
36
37 if (p->id != id)
38 continue;
39
40 val = readl(priv->base + p->reg);
41 val |= BIT(p->bit);
42 writel(val, priv->base + p->reg);
43
44 return 0;
45 }
46
47 dev_err(priv->dev, "clk_id=%lu was not handled\n", id);
48 return -EINVAL;
49 }
50
51 static const struct uniphier_clk_mux_data *
uniphier_clk_get_mux_data(struct uniphier_clk_priv * priv,unsigned long id)52 uniphier_clk_get_mux_data(struct uniphier_clk_priv *priv, unsigned long id)
53 {
54 const struct uniphier_clk_mux_data *p;
55
56 for (p = priv->data->mux; p->id != UNIPHIER_CLK_ID_END; p++) {
57 if (p->id == id)
58 return p;
59 }
60
61 return NULL;
62 }
63
uniphier_clk_get_rate(struct clk * clk)64 static ulong uniphier_clk_get_rate(struct clk *clk)
65 {
66 struct uniphier_clk_priv *priv = dev_get_priv(clk->dev);
67 const struct uniphier_clk_mux_data *mux;
68 u32 val;
69 int i;
70
71 mux = uniphier_clk_get_mux_data(priv, clk->id);
72 if (!mux)
73 return 0;
74
75 if (!mux->nr_muxs) /* fixed-rate */
76 return mux->rates[0];
77
78 val = readl(priv->base + mux->reg);
79
80 for (i = 0; i < mux->nr_muxs; i++)
81 if ((mux->masks[i] & val) == mux->vals[i])
82 return mux->rates[i];
83
84 return -EINVAL;
85 }
86
uniphier_clk_set_rate(struct clk * clk,ulong rate)87 static ulong uniphier_clk_set_rate(struct clk *clk, ulong rate)
88 {
89 struct uniphier_clk_priv *priv = dev_get_priv(clk->dev);
90 const struct uniphier_clk_mux_data *mux;
91 u32 val;
92 int i, best_rate_id = -1;
93 ulong best_rate = 0;
94
95 mux = uniphier_clk_get_mux_data(priv, clk->id);
96 if (!mux)
97 return 0;
98
99 if (!mux->nr_muxs) /* fixed-rate */
100 return mux->rates[0];
101
102 /* first, decide the best match rate */
103 for (i = 0; i < mux->nr_muxs; i++) {
104 if (mux->rates[i] > best_rate && mux->rates[i] <= rate) {
105 best_rate = mux->rates[i];
106 best_rate_id = i;
107 }
108 }
109
110 if (best_rate_id < 0)
111 return -EINVAL;
112
113 val = readl(priv->base + mux->reg);
114 val &= ~mux->masks[best_rate_id];
115 val |= mux->vals[best_rate_id];
116 writel(val, priv->base + mux->reg);
117
118 debug("%s: requested rate = %lu, set rate = %lu\n", __func__,
119 rate, best_rate);
120
121 return best_rate;
122 }
123
124 static const struct clk_ops uniphier_clk_ops = {
125 .enable = uniphier_clk_enable,
126 .get_rate = uniphier_clk_get_rate,
127 .set_rate = uniphier_clk_set_rate,
128 };
129
uniphier_clk_probe(struct udevice * dev)130 static int uniphier_clk_probe(struct udevice *dev)
131 {
132 struct uniphier_clk_priv *priv = dev_get_priv(dev);
133 fdt_addr_t addr;
134
135 addr = devfdt_get_addr(dev->parent);
136 if (addr == FDT_ADDR_T_NONE)
137 return -EINVAL;
138
139 priv->base = devm_ioremap(dev, addr, SZ_4K);
140 if (!priv->base)
141 return -ENOMEM;
142
143 priv->data = (void *)dev_get_driver_data(dev);
144
145 return 0;
146 }
147
148 static const struct udevice_id uniphier_clk_match[] = {
149 /* System clock */
150 {
151 .compatible = "socionext,uniphier-ld4-clock",
152 .data = (ulong)&uniphier_pxs2_sys_clk_data,
153 },
154 {
155 .compatible = "socionext,uniphier-pro4-clock",
156 .data = (ulong)&uniphier_pxs2_sys_clk_data,
157 },
158 {
159 .compatible = "socionext,uniphier-sld8-clock",
160 .data = (ulong)&uniphier_pxs2_sys_clk_data,
161 },
162 {
163 .compatible = "socionext,uniphier-pro5-clock",
164 .data = (ulong)&uniphier_pxs2_sys_clk_data,
165 },
166 {
167 .compatible = "socionext,uniphier-pxs2-clock",
168 .data = (ulong)&uniphier_pxs2_sys_clk_data,
169 },
170 {
171 .compatible = "socionext,uniphier-ld11-clock",
172 .data = (ulong)&uniphier_ld20_sys_clk_data,
173 },
174 {
175 .compatible = "socionext,uniphier-ld20-clock",
176 .data = (ulong)&uniphier_ld20_sys_clk_data,
177 },
178 /* Media I/O clock */
179 {
180 .compatible = "socionext,uniphier-ld4-mio-clock",
181 .data = (ulong)&uniphier_mio_clk_data,
182 },
183 {
184 .compatible = "socionext,uniphier-pro4-mio-clock",
185 .data = (ulong)&uniphier_mio_clk_data,
186 },
187 {
188 .compatible = "socionext,uniphier-sld8-mio-clock",
189 .data = (ulong)&uniphier_mio_clk_data,
190 },
191 {
192 .compatible = "socionext,uniphier-pro5-sd-clock",
193 .data = (ulong)&uniphier_mio_clk_data,
194 },
195 {
196 .compatible = "socionext,uniphier-pxs2-sd-clock",
197 .data = (ulong)&uniphier_mio_clk_data,
198 },
199 {
200 .compatible = "socionext,uniphier-ld11-mio-clock",
201 .data = (ulong)&uniphier_mio_clk_data,
202 },
203 {
204 .compatible = "socionext,uniphier-ld20-sd-clock",
205 .data = (ulong)&uniphier_mio_clk_data,
206 },
207 { /* sentinel */ }
208 };
209
210 U_BOOT_DRIVER(uniphier_clk) = {
211 .name = "uniphier-clk",
212 .id = UCLASS_CLK,
213 .of_match = uniphier_clk_match,
214 .probe = uniphier_clk_probe,
215 .priv_auto_alloc_size = sizeof(struct uniphier_clk_priv),
216 .ops = &uniphier_clk_ops,
217 };
218