1 /*
2 * (C) Copyright 2001 Sysgo Real-Time Solutions, GmbH <www.elinos.com>
3 * Andreas Heppel <aheppel@sysgo.de>
4 *
5 * (C) Copyright 2002
6 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
7 * Wolfgang Grandegger, DENX Software Engineering, wg@denx.de.
8 *
9 * SPDX-License-Identifier: GPL-2.0+
10 */
11
12 /*
13 * PCI routines
14 */
15
16 #include <common.h>
17 #include <bootretry.h>
18 #include <cli.h>
19 #include <command.h>
20 #include <console.h>
21 #include <dm.h>
22 #include <asm/processor.h>
23 #include <asm/io.h>
24 #include <pci.h>
25
26 struct pci_reg_info {
27 const char *name;
28 enum pci_size_t size;
29 u8 offset;
30 };
31
pci_byte_size(enum pci_size_t size)32 static int pci_byte_size(enum pci_size_t size)
33 {
34 switch (size) {
35 case PCI_SIZE_8:
36 return 1;
37 case PCI_SIZE_16:
38 return 2;
39 case PCI_SIZE_32:
40 default:
41 return 4;
42 }
43 }
44
pci_field_width(enum pci_size_t size)45 static int pci_field_width(enum pci_size_t size)
46 {
47 return pci_byte_size(size) * 2;
48 }
49
pci_show_regs(struct udevice * dev,struct pci_reg_info * regs)50 static void pci_show_regs(struct udevice *dev, struct pci_reg_info *regs)
51 {
52 for (; regs->name; regs++) {
53 unsigned long val;
54
55 dm_pci_read_config(dev, regs->offset, &val, regs->size);
56 printf(" %s =%*s%#.*lx\n", regs->name,
57 (int)(28 - strlen(regs->name)), "",
58 pci_field_width(regs->size), val);
59 }
60 }
61
pci_bar_show(struct udevice * dev)62 static int pci_bar_show(struct udevice *dev)
63 {
64 u8 header_type;
65 int bar_cnt, bar_id, mem_type;
66 bool is_64, is_io;
67 u32 base_low, base_high;
68 u32 size_low, size_high;
69 u64 base, size;
70 u32 reg_addr;
71 int prefetchable;
72
73 dm_pci_read_config8(dev, PCI_HEADER_TYPE, &header_type);
74 header_type &= 0x7f;
75
76 if (header_type == PCI_HEADER_TYPE_CARDBUS) {
77 printf("CardBus doesn't support BARs\n");
78 return -ENOSYS;
79 } else if (header_type != PCI_HEADER_TYPE_NORMAL &&
80 header_type != PCI_HEADER_TYPE_BRIDGE) {
81 printf("unknown header type\n");
82 return -ENOSYS;
83 }
84
85 bar_cnt = (header_type == PCI_HEADER_TYPE_NORMAL) ? 6 : 2;
86
87 printf("ID Base Size Width Type\n");
88 printf("----------------------------------------------------------\n");
89
90 bar_id = 0;
91 reg_addr = PCI_BASE_ADDRESS_0;
92 while (bar_cnt) {
93 dm_pci_read_config32(dev, reg_addr, &base_low);
94 dm_pci_write_config32(dev, reg_addr, 0xffffffff);
95 dm_pci_read_config32(dev, reg_addr, &size_low);
96 dm_pci_write_config32(dev, reg_addr, base_low);
97 reg_addr += 4;
98
99 base = base_low & ~0xf;
100 size = size_low & ~0xf;
101 base_high = 0x0;
102 size_high = 0xffffffff;
103 is_64 = 0;
104 prefetchable = base_low & PCI_BASE_ADDRESS_MEM_PREFETCH;
105 is_io = base_low & PCI_BASE_ADDRESS_SPACE_IO;
106 mem_type = base_low & PCI_BASE_ADDRESS_MEM_TYPE_MASK;
107
108 if (mem_type == PCI_BASE_ADDRESS_MEM_TYPE_64) {
109 dm_pci_read_config32(dev, reg_addr, &base_high);
110 dm_pci_write_config32(dev, reg_addr, 0xffffffff);
111 dm_pci_read_config32(dev, reg_addr, &size_high);
112 dm_pci_write_config32(dev, reg_addr, base_high);
113 bar_cnt--;
114 reg_addr += 4;
115 is_64 = 1;
116 }
117
118 base = base | ((u64)base_high << 32);
119 size = size | ((u64)size_high << 32);
120
121 if ((!is_64 && size_low) || (is_64 && size)) {
122 size = ~size + 1;
123 printf(" %d %#018llx %#018llx %d %s %s\n",
124 bar_id, (unsigned long long)base,
125 (unsigned long long)size, is_64 ? 64 : 32,
126 is_io ? "I/O" : "MEM",
127 prefetchable ? "Prefetchable" : "");
128 }
129
130 bar_id++;
131 bar_cnt--;
132 }
133
134 return 0;
135 }
136
137 static struct pci_reg_info regs_start[] = {
138 { "vendor ID", PCI_SIZE_16, PCI_VENDOR_ID },
139 { "device ID", PCI_SIZE_16, PCI_DEVICE_ID },
140 { "command register ID", PCI_SIZE_16, PCI_COMMAND },
141 { "status register", PCI_SIZE_16, PCI_STATUS },
142 { "revision ID", PCI_SIZE_8, PCI_REVISION_ID },
143 {},
144 };
145
146 static struct pci_reg_info regs_rest[] = {
147 { "sub class code", PCI_SIZE_8, PCI_CLASS_SUB_CODE },
148 { "programming interface", PCI_SIZE_8, PCI_CLASS_PROG },
149 { "cache line", PCI_SIZE_8, PCI_CACHE_LINE_SIZE },
150 { "latency time", PCI_SIZE_8, PCI_LATENCY_TIMER },
151 { "header type", PCI_SIZE_8, PCI_HEADER_TYPE },
152 { "BIST", PCI_SIZE_8, PCI_BIST },
153 { "base address 0", PCI_SIZE_32, PCI_BASE_ADDRESS_0 },
154 {},
155 };
156
157 static struct pci_reg_info regs_normal[] = {
158 { "base address 1", PCI_SIZE_32, PCI_BASE_ADDRESS_1 },
159 { "base address 2", PCI_SIZE_32, PCI_BASE_ADDRESS_2 },
160 { "base address 3", PCI_SIZE_32, PCI_BASE_ADDRESS_3 },
161 { "base address 4", PCI_SIZE_32, PCI_BASE_ADDRESS_4 },
162 { "base address 5", PCI_SIZE_32, PCI_BASE_ADDRESS_5 },
163 { "cardBus CIS pointer", PCI_SIZE_32, PCI_CARDBUS_CIS },
164 { "sub system vendor ID", PCI_SIZE_16, PCI_SUBSYSTEM_VENDOR_ID },
165 { "sub system ID", PCI_SIZE_16, PCI_SUBSYSTEM_ID },
166 { "expansion ROM base address", PCI_SIZE_32, PCI_ROM_ADDRESS },
167 { "interrupt line", PCI_SIZE_8, PCI_INTERRUPT_LINE },
168 { "interrupt pin", PCI_SIZE_8, PCI_INTERRUPT_PIN },
169 { "min Grant", PCI_SIZE_8, PCI_MIN_GNT },
170 { "max Latency", PCI_SIZE_8, PCI_MAX_LAT },
171 {},
172 };
173
174 static struct pci_reg_info regs_bridge[] = {
175 { "base address 1", PCI_SIZE_32, PCI_BASE_ADDRESS_1 },
176 { "primary bus number", PCI_SIZE_8, PCI_PRIMARY_BUS },
177 { "secondary bus number", PCI_SIZE_8, PCI_SECONDARY_BUS },
178 { "subordinate bus number", PCI_SIZE_8, PCI_SUBORDINATE_BUS },
179 { "secondary latency timer", PCI_SIZE_8, PCI_SEC_LATENCY_TIMER },
180 { "IO base", PCI_SIZE_8, PCI_IO_BASE },
181 { "IO limit", PCI_SIZE_8, PCI_IO_LIMIT },
182 { "secondary status", PCI_SIZE_16, PCI_SEC_STATUS },
183 { "memory base", PCI_SIZE_16, PCI_MEMORY_BASE },
184 { "memory limit", PCI_SIZE_16, PCI_MEMORY_LIMIT },
185 { "prefetch memory base", PCI_SIZE_16, PCI_PREF_MEMORY_BASE },
186 { "prefetch memory limit", PCI_SIZE_16, PCI_PREF_MEMORY_LIMIT },
187 { "prefetch memory base upper", PCI_SIZE_32, PCI_PREF_BASE_UPPER32 },
188 { "prefetch memory limit upper", PCI_SIZE_32, PCI_PREF_LIMIT_UPPER32 },
189 { "IO base upper 16 bits", PCI_SIZE_16, PCI_IO_BASE_UPPER16 },
190 { "IO limit upper 16 bits", PCI_SIZE_16, PCI_IO_LIMIT_UPPER16 },
191 { "expansion ROM base address", PCI_SIZE_32, PCI_ROM_ADDRESS1 },
192 { "interrupt line", PCI_SIZE_8, PCI_INTERRUPT_LINE },
193 { "interrupt pin", PCI_SIZE_8, PCI_INTERRUPT_PIN },
194 { "bridge control", PCI_SIZE_16, PCI_BRIDGE_CONTROL },
195 {},
196 };
197
198 static struct pci_reg_info regs_cardbus[] = {
199 { "capabilities", PCI_SIZE_8, PCI_CB_CAPABILITY_LIST },
200 { "secondary status", PCI_SIZE_16, PCI_CB_SEC_STATUS },
201 { "primary bus number", PCI_SIZE_8, PCI_CB_PRIMARY_BUS },
202 { "CardBus number", PCI_SIZE_8, PCI_CB_CARD_BUS },
203 { "subordinate bus number", PCI_SIZE_8, PCI_CB_SUBORDINATE_BUS },
204 { "CardBus latency timer", PCI_SIZE_8, PCI_CB_LATENCY_TIMER },
205 { "CardBus memory base 0", PCI_SIZE_32, PCI_CB_MEMORY_BASE_0 },
206 { "CardBus memory limit 0", PCI_SIZE_32, PCI_CB_MEMORY_LIMIT_0 },
207 { "CardBus memory base 1", PCI_SIZE_32, PCI_CB_MEMORY_BASE_1 },
208 { "CardBus memory limit 1", PCI_SIZE_32, PCI_CB_MEMORY_LIMIT_1 },
209 { "CardBus IO base 0", PCI_SIZE_16, PCI_CB_IO_BASE_0 },
210 { "CardBus IO base high 0", PCI_SIZE_16, PCI_CB_IO_BASE_0_HI },
211 { "CardBus IO limit 0", PCI_SIZE_16, PCI_CB_IO_LIMIT_0 },
212 { "CardBus IO limit high 0", PCI_SIZE_16, PCI_CB_IO_LIMIT_0_HI },
213 { "CardBus IO base 1", PCI_SIZE_16, PCI_CB_IO_BASE_1 },
214 { "CardBus IO base high 1", PCI_SIZE_16, PCI_CB_IO_BASE_1_HI },
215 { "CardBus IO limit 1", PCI_SIZE_16, PCI_CB_IO_LIMIT_1 },
216 { "CardBus IO limit high 1", PCI_SIZE_16, PCI_CB_IO_LIMIT_1_HI },
217 { "interrupt line", PCI_SIZE_8, PCI_INTERRUPT_LINE },
218 { "interrupt pin", PCI_SIZE_8, PCI_INTERRUPT_PIN },
219 { "bridge control", PCI_SIZE_16, PCI_CB_BRIDGE_CONTROL },
220 { "subvendor ID", PCI_SIZE_16, PCI_CB_SUBSYSTEM_VENDOR_ID },
221 { "subdevice ID", PCI_SIZE_16, PCI_CB_SUBSYSTEM_ID },
222 { "PC Card 16bit base address", PCI_SIZE_32, PCI_CB_LEGACY_MODE_BASE },
223 {},
224 };
225
226 /**
227 * pci_header_show() - Show the header of the specified PCI device.
228 *
229 * @dev: Bus+Device+Function number
230 */
pci_header_show(struct udevice * dev)231 static void pci_header_show(struct udevice *dev)
232 {
233 unsigned long class, header_type;
234
235 dm_pci_read_config(dev, PCI_CLASS_CODE, &class, PCI_SIZE_8);
236 dm_pci_read_config(dev, PCI_HEADER_TYPE, &header_type, PCI_SIZE_8);
237 pci_show_regs(dev, regs_start);
238 printf(" class code = 0x%.2x (%s)\n", (int)class,
239 pci_class_str(class));
240 pci_show_regs(dev, regs_rest);
241
242 switch (header_type & 0x7f) {
243 case PCI_HEADER_TYPE_NORMAL: /* "normal" PCI device */
244 pci_show_regs(dev, regs_normal);
245 break;
246 case PCI_HEADER_TYPE_BRIDGE: /* PCI-to-PCI bridge */
247 pci_show_regs(dev, regs_bridge);
248 break;
249 case PCI_HEADER_TYPE_CARDBUS: /* PCI-to-CardBus bridge */
250 pci_show_regs(dev, regs_cardbus);
251 break;
252
253 default:
254 printf("unknown header\n");
255 break;
256 }
257 }
258
pciinfo_header(bool short_listing)259 static void pciinfo_header(bool short_listing)
260 {
261 if (short_listing) {
262 printf("BusDevFun VendorId DeviceId Device Class Sub-Class\n");
263 printf("_____________________________________________________________\n");
264 }
265 }
266
267 /**
268 * pci_header_show_brief() - Show the short-form PCI device header
269 *
270 * Reads and prints the header of the specified PCI device in short form.
271 *
272 * @dev: PCI device to show
273 */
pci_header_show_brief(struct udevice * dev)274 static void pci_header_show_brief(struct udevice *dev)
275 {
276 ulong vendor, device;
277 ulong class, subclass;
278
279 dm_pci_read_config(dev, PCI_VENDOR_ID, &vendor, PCI_SIZE_16);
280 dm_pci_read_config(dev, PCI_DEVICE_ID, &device, PCI_SIZE_16);
281 dm_pci_read_config(dev, PCI_CLASS_CODE, &class, PCI_SIZE_8);
282 dm_pci_read_config(dev, PCI_CLASS_SUB_CODE, &subclass, PCI_SIZE_8);
283
284 printf("0x%.4lx 0x%.4lx %-23s 0x%.2lx\n",
285 vendor, device,
286 pci_class_str(class), subclass);
287 }
288
pciinfo(struct udevice * bus,bool short_listing,bool multi)289 static void pciinfo(struct udevice *bus, bool short_listing, bool multi)
290 {
291 struct udevice *dev;
292
293 if (!multi)
294 printf("Scanning PCI devices on bus %d\n", bus->seq);
295
296 if (!multi || bus->seq == 0)
297 pciinfo_header(short_listing);
298
299 for (device_find_first_child(bus, &dev);
300 dev;
301 device_find_next_child(&dev)) {
302 struct pci_child_platdata *pplat;
303
304 pplat = dev_get_parent_platdata(dev);
305 if (short_listing) {
306 printf("%02x.%02x.%02x ", bus->seq,
307 PCI_DEV(pplat->devfn), PCI_FUNC(pplat->devfn));
308 pci_header_show_brief(dev);
309 } else {
310 printf("\nFound PCI device %02x.%02x.%02x:\n", bus->seq,
311 PCI_DEV(pplat->devfn), PCI_FUNC(pplat->devfn));
312 pci_header_show(dev);
313 }
314 }
315 }
316
317 /**
318 * get_pci_dev() - Convert the "bus.device.function" identifier into a number
319 *
320 * @name: Device string in the form "bus.device.function" where each is in hex
321 * @return encoded pci_dev_t or -1 if the string was invalid
322 */
get_pci_dev(char * name)323 static pci_dev_t get_pci_dev(char *name)
324 {
325 char cnum[12];
326 int len, i, iold, n;
327 int bdfs[3] = {0,0,0};
328
329 len = strlen(name);
330 if (len > 8)
331 return -1;
332 for (i = 0, iold = 0, n = 0; i < len; i++) {
333 if (name[i] == '.') {
334 memcpy(cnum, &name[iold], i - iold);
335 cnum[i - iold] = '\0';
336 bdfs[n++] = simple_strtoul(cnum, NULL, 16);
337 iold = i + 1;
338 }
339 }
340 strcpy(cnum, &name[iold]);
341 if (n == 0)
342 n = 1;
343 bdfs[n] = simple_strtoul(cnum, NULL, 16);
344
345 return PCI_BDF(bdfs[0], bdfs[1], bdfs[2]);
346 }
347
pci_cfg_display(struct udevice * dev,ulong addr,enum pci_size_t size,ulong length)348 static int pci_cfg_display(struct udevice *dev, ulong addr,
349 enum pci_size_t size, ulong length)
350 {
351 #define DISP_LINE_LEN 16
352 ulong i, nbytes, linebytes;
353 int byte_size;
354 int rc = 0;
355
356 byte_size = pci_byte_size(size);
357 if (length == 0)
358 length = 0x40 / byte_size; /* Standard PCI config space */
359
360 /* Print the lines.
361 * once, and all accesses are with the specified bus width.
362 */
363 nbytes = length * byte_size;
364 do {
365 printf("%08lx:", addr);
366 linebytes = (nbytes > DISP_LINE_LEN) ? DISP_LINE_LEN : nbytes;
367 for (i = 0; i < linebytes; i += byte_size) {
368 unsigned long val;
369
370 dm_pci_read_config(dev, addr, &val, size);
371 printf(" %0*lx", pci_field_width(size), val);
372 addr += byte_size;
373 }
374 printf("\n");
375 nbytes -= linebytes;
376 if (ctrlc()) {
377 rc = 1;
378 break;
379 }
380 } while (nbytes > 0);
381
382 return (rc);
383 }
384
pci_cfg_modify(struct udevice * dev,ulong addr,ulong size,ulong value,int incrflag)385 static int pci_cfg_modify(struct udevice *dev, ulong addr, ulong size,
386 ulong value, int incrflag)
387 {
388 ulong i;
389 int nbytes;
390 ulong val;
391
392 /* Print the address, followed by value. Then accept input for
393 * the next value. A non-converted value exits.
394 */
395 do {
396 printf("%08lx:", addr);
397 dm_pci_read_config(dev, addr, &val, size);
398 printf(" %0*lx", pci_field_width(size), val);
399
400 nbytes = cli_readline(" ? ");
401 if (nbytes == 0 || (nbytes == 1 && console_buffer[0] == '-')) {
402 /* <CR> pressed as only input, don't modify current
403 * location and move to next. "-" pressed will go back.
404 */
405 if (incrflag)
406 addr += nbytes ? -size : size;
407 nbytes = 1;
408 /* good enough to not time out */
409 bootretry_reset_cmd_timeout();
410 }
411 #ifdef CONFIG_BOOT_RETRY_TIME
412 else if (nbytes == -2) {
413 break; /* timed out, exit the command */
414 }
415 #endif
416 else {
417 char *endp;
418 i = simple_strtoul(console_buffer, &endp, 16);
419 nbytes = endp - console_buffer;
420 if (nbytes) {
421 /* good enough to not time out
422 */
423 bootretry_reset_cmd_timeout();
424 dm_pci_write_config(dev, addr, i, size);
425 if (incrflag)
426 addr += size;
427 }
428 }
429 } while (nbytes);
430
431 return 0;
432 }
433
434 static const struct pci_flag_info {
435 uint flag;
436 const char *name;
437 } pci_flag_info[] = {
438 { PCI_REGION_IO, "io" },
439 { PCI_REGION_PREFETCH, "prefetch" },
440 { PCI_REGION_SYS_MEMORY, "sysmem" },
441 { PCI_REGION_RO, "readonly" },
442 { PCI_REGION_IO, "io" },
443 };
444
pci_show_regions(struct udevice * bus)445 static void pci_show_regions(struct udevice *bus)
446 {
447 struct pci_controller *hose = dev_get_uclass_priv(pci_get_controller(bus));
448 const struct pci_region *reg;
449 int i, j;
450
451 if (!hose) {
452 printf("Bus '%s' is not a PCI controller\n", bus->name);
453 return;
454 }
455
456 printf("Buses %02x-%02x\n", hose->first_busno, hose->last_busno);
457 printf("# %-18s %-18s %-18s %s\n", "Bus start", "Phys start", "Size",
458 "Flags");
459 for (i = 0, reg = hose->regions; i < hose->region_count; i++, reg++) {
460 printf("%d %#018llx %#018llx %#018llx ", i,
461 (unsigned long long)reg->bus_start,
462 (unsigned long long)reg->phys_start,
463 (unsigned long long)reg->size);
464 if (!(reg->flags & PCI_REGION_TYPE))
465 printf("mem ");
466 for (j = 0; j < ARRAY_SIZE(pci_flag_info); j++) {
467 if (reg->flags & pci_flag_info[j].flag)
468 printf("%s ", pci_flag_info[j].name);
469 }
470 printf("\n");
471 }
472 }
473
474 /* PCI Configuration Space access commands
475 *
476 * Syntax:
477 * pci display[.b, .w, .l] bus.device.function} [addr] [len]
478 * pci next[.b, .w, .l] bus.device.function [addr]
479 * pci modify[.b, .w, .l] bus.device.function [addr]
480 * pci write[.b, .w, .l] bus.device.function addr value
481 */
do_pci(cmd_tbl_t * cmdtp,int flag,int argc,char * const argv[])482 static int do_pci(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
483 {
484 ulong addr = 0, value = 0, cmd_size = 0;
485 enum pci_size_t size = PCI_SIZE_32;
486 struct udevice *dev, *bus;
487 int busnum = -1;
488 pci_dev_t bdf = 0;
489 char cmd = 's';
490 int ret = 0;
491 char *endp;
492
493 if (argc > 1)
494 cmd = argv[1][0];
495
496 switch (cmd) {
497 case 'd': /* display */
498 case 'n': /* next */
499 case 'm': /* modify */
500 case 'w': /* write */
501 /* Check for a size specification. */
502 cmd_size = cmd_get_data_size(argv[1], 4);
503 size = (cmd_size == 4) ? PCI_SIZE_32 : cmd_size - 1;
504 if (argc > 3)
505 addr = simple_strtoul(argv[3], NULL, 16);
506 if (argc > 4)
507 value = simple_strtoul(argv[4], NULL, 16);
508 case 'h': /* header */
509 case 'b': /* bars */
510 if (argc < 3)
511 goto usage;
512 if ((bdf = get_pci_dev(argv[2])) == -1)
513 return 1;
514 break;
515 case 'e':
516 pci_init();
517 return 0;
518 case 'r': /* no break */
519 default: /* scan bus */
520 value = 1; /* short listing */
521 if (argc > 1) {
522 if (cmd != 'r' && argv[argc-1][0] == 'l') {
523 value = 0;
524 argc--;
525 }
526 if (argc > 2 || (argc > 1 && cmd != 'r' && argv[1][0] != 's')) {
527 if (argv[argc - 1][0] != '*') {
528 busnum = simple_strtoul(argv[argc - 1], &endp, 16);
529 if (*endp)
530 goto usage;
531 }
532 argc--;
533 }
534 if (cmd == 'r' && argc > 2)
535 goto usage;
536 else if (cmd != 'r' && (argc > 2 || (argc == 2 && argv[1][0] != 's')))
537 goto usage;
538 }
539 if (busnum == -1) {
540 if (cmd != 'r') {
541 for (busnum = 0;
542 uclass_get_device_by_seq(UCLASS_PCI, busnum, &bus) == 0;
543 busnum++)
544 pciinfo(bus, value, true);
545 } else {
546 for (busnum = 0;
547 uclass_get_device_by_seq(UCLASS_PCI, busnum, &bus) == 0;
548 busnum++) {
549 /* Regions are controller specific so skip non-root buses */
550 if (device_is_on_pci_bus(bus))
551 continue;
552 pci_show_regions(bus);
553 }
554 }
555 return 0;
556 }
557 ret = uclass_get_device_by_seq(UCLASS_PCI, busnum, &bus);
558 if (ret) {
559 printf("No such bus\n");
560 return CMD_RET_FAILURE;
561 }
562 if (cmd == 'r')
563 pci_show_regions(bus);
564 else
565 pciinfo(bus, value, false);
566 return 0;
567 }
568
569 ret = dm_pci_bus_find_bdf(bdf, &dev);
570 if (ret) {
571 printf("No such device\n");
572 return CMD_RET_FAILURE;
573 }
574
575 switch (argv[1][0]) {
576 case 'h': /* header */
577 pci_header_show(dev);
578 break;
579 case 'd': /* display */
580 return pci_cfg_display(dev, addr, size, value);
581 case 'n': /* next */
582 if (argc < 4)
583 goto usage;
584 ret = pci_cfg_modify(dev, addr, size, value, 0);
585 break;
586 case 'm': /* modify */
587 if (argc < 4)
588 goto usage;
589 ret = pci_cfg_modify(dev, addr, size, value, 1);
590 break;
591 case 'w': /* write */
592 if (argc < 5)
593 goto usage;
594 ret = dm_pci_write_config(dev, addr, value, size);
595 break;
596 case 'b': /* bars */
597 return pci_bar_show(dev);
598 default:
599 ret = CMD_RET_USAGE;
600 break;
601 }
602
603 return ret;
604 usage:
605 return CMD_RET_USAGE;
606 }
607
608 /***************************************************/
609
610 #ifdef CONFIG_SYS_LONGHELP
611 static char pci_help_text[] =
612 "[bus|*] [long]\n"
613 " - short or long list of PCI devices on bus 'bus'\n"
614 "pci enum\n"
615 " - Enumerate PCI buses\n"
616 "pci header b.d.f\n"
617 " - show header of PCI device 'bus.device.function'\n"
618 "pci bar b.d.f\n"
619 " - show BARs base and size for device b.d.f'\n"
620 "pci regions [bus|*]\n"
621 " - show PCI regions\n"
622 "pci display[.b, .w, .l] b.d.f [address] [# of objects]\n"
623 " - display PCI configuration space (CFG)\n"
624 "pci next[.b, .w, .l] b.d.f address\n"
625 " - modify, read and keep CFG address\n"
626 "pci modify[.b, .w, .l] b.d.f address\n"
627 " - modify, auto increment CFG address\n"
628 "pci write[.b, .w, .l] b.d.f address value\n"
629 " - write to CFG address";
630 #endif
631
632 U_BOOT_CMD(
633 pci, 5, 1, do_pci,
634 "list and access PCI Configuration Space", pci_help_text
635 );
636