1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * Copyright 2017 Toradex AG
3*4882a593Smuzhiyun *
4*4882a593Smuzhiyun * FSL DCU platform driver
5*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+
6*4882a593Smuzhiyun */
7*4882a593Smuzhiyun
8*4882a593Smuzhiyun #include <asm/arch/crm_regs.h>
9*4882a593Smuzhiyun #include <asm/io.h>
10*4882a593Smuzhiyun #include <common.h>
11*4882a593Smuzhiyun #include <fsl_dcu_fb.h>
12*4882a593Smuzhiyun #include "div64.h"
13*4882a593Smuzhiyun
14*4882a593Smuzhiyun DECLARE_GLOBAL_DATA_PTR;
15*4882a593Smuzhiyun
dcu_set_pixel_clock(unsigned int pixclock)16*4882a593Smuzhiyun unsigned int dcu_set_pixel_clock(unsigned int pixclock)
17*4882a593Smuzhiyun {
18*4882a593Smuzhiyun struct ccm_reg *ccm = (struct ccm_reg *)CCM_BASE_ADDR;
19*4882a593Smuzhiyun unsigned long long div;
20*4882a593Smuzhiyun
21*4882a593Smuzhiyun clrbits_le32(&ccm->cscmr1, CCM_CSCMR1_DCU0_CLK_SEL);
22*4882a593Smuzhiyun clrsetbits_le32(&ccm->cscdr3,
23*4882a593Smuzhiyun CCM_CSCDR3_DCU0_DIV_MASK | CCM_CSCDR3_DCU0_EN,
24*4882a593Smuzhiyun CCM_CSCDR3_DCU0_DIV(0) | CCM_CSCDR3_DCU0_EN);
25*4882a593Smuzhiyun div = (unsigned long long)(PLL1_PFD2_FREQ / 1000);
26*4882a593Smuzhiyun do_div(div, pixclock);
27*4882a593Smuzhiyun
28*4882a593Smuzhiyun return div;
29*4882a593Smuzhiyun }
30*4882a593Smuzhiyun
platform_dcu_init(unsigned int xres,unsigned int yres,const char * port,struct fb_videomode * dcu_fb_videomode)31*4882a593Smuzhiyun int platform_dcu_init(unsigned int xres, unsigned int yres,
32*4882a593Smuzhiyun const char *port,
33*4882a593Smuzhiyun struct fb_videomode *dcu_fb_videomode)
34*4882a593Smuzhiyun {
35*4882a593Smuzhiyun fsl_dcu_init(xres, yres, 32);
36*4882a593Smuzhiyun
37*4882a593Smuzhiyun return 0;
38*4882a593Smuzhiyun }
39