1 // SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
2 /*
3 * Copyright (C) 2018, STMicroelectronics - All Rights Reserved
4 */
5 #include <common.h>
6 #include <adc.h>
7 #include <config.h>
8 #include <clk.h>
9 #include <dm.h>
10 #include <g_dnl.h>
11 #include <generic-phy.h>
12 #include <i2c.h>
13 #include <led.h>
14 #include <misc.h>
15 #include <mtd.h>
16 #include <mtd_node.h>
17 #include <netdev.h>
18 #include <phy.h>
19 #include <reset.h>
20 #include <syscon.h>
21 #include <usb.h>
22 #include <asm/io.h>
23 #include <asm/gpio.h>
24 #include <asm/arch/stm32.h>
25 #include <power/regulator.h>
26 #include <usb/dwc2_udc.h>
27
28 /* SYSCFG registers */
29 #define SYSCFG_BOOTR 0x00
30 #define SYSCFG_PMCSETR 0x04
31 #define SYSCFG_IOCTRLSETR 0x18
32 #define SYSCFG_ICNR 0x1C
33 #define SYSCFG_CMPCR 0x20
34 #define SYSCFG_CMPENSETR 0x24
35 #define SYSCFG_PMCCLRR 0x44
36
37 #define SYSCFG_BOOTR_BOOT_MASK GENMASK(2, 0)
38 #define SYSCFG_BOOTR_BOOTPD_SHIFT 4
39
40 #define SYSCFG_IOCTRLSETR_HSLVEN_TRACE BIT(0)
41 #define SYSCFG_IOCTRLSETR_HSLVEN_QUADSPI BIT(1)
42 #define SYSCFG_IOCTRLSETR_HSLVEN_ETH BIT(2)
43 #define SYSCFG_IOCTRLSETR_HSLVEN_SDMMC BIT(3)
44 #define SYSCFG_IOCTRLSETR_HSLVEN_SPI BIT(4)
45
46 #define SYSCFG_CMPCR_SW_CTRL BIT(1)
47 #define SYSCFG_CMPCR_READY BIT(8)
48
49 #define SYSCFG_CMPENSETR_MPU_EN BIT(0)
50
51 #define SYSCFG_PMCSETR_ETH_CLK_SEL BIT(16)
52 #define SYSCFG_PMCSETR_ETH_REF_CLK_SEL BIT(17)
53
54 #define SYSCFG_PMCSETR_ETH_SELMII BIT(20)
55
56 #define SYSCFG_PMCSETR_ETH_SEL_MASK GENMASK(23, 21)
57 #define SYSCFG_PMCSETR_ETH_SEL_GMII_MII (0 << 21)
58 #define SYSCFG_PMCSETR_ETH_SEL_RGMII (1 << 21)
59 #define SYSCFG_PMCSETR_ETH_SEL_RMII (4 << 21)
60
61 /*
62 * Get a global data pointer
63 */
64 DECLARE_GLOBAL_DATA_PTR;
65
66 #define USB_WARNING_LOW_THRESHOLD_UV 660000
67 #define USB_START_LOW_THRESHOLD_UV 1230000
68 #define USB_START_HIGH_THRESHOLD_UV 2100000
69
checkboard(void)70 int checkboard(void)
71 {
72 int ret;
73 char *mode;
74 u32 otp;
75 struct udevice *dev;
76 const char *fdt_compat;
77 int fdt_compat_len;
78
79 if (IS_ENABLED(CONFIG_STM32MP1_TRUSTED))
80 mode = "trusted";
81 else
82 mode = "basic";
83
84 printf("Board: stm32mp1 in %s mode", mode);
85 fdt_compat = fdt_getprop(gd->fdt_blob, 0, "compatible",
86 &fdt_compat_len);
87 if (fdt_compat && fdt_compat_len)
88 printf(" (%s)", fdt_compat);
89 puts("\n");
90
91 ret = uclass_get_device_by_driver(UCLASS_MISC,
92 DM_GET_DRIVER(stm32mp_bsec),
93 &dev);
94
95 if (!ret)
96 ret = misc_read(dev, STM32_BSEC_SHADOW(BSEC_OTP_BOARD),
97 &otp, sizeof(otp));
98 if (!ret && otp) {
99 printf("Board: MB%04x Var%d Rev.%c-%02d\n",
100 otp >> 16,
101 (otp >> 12) & 0xF,
102 ((otp >> 8) & 0xF) - 1 + 'A',
103 otp & 0xF);
104 }
105
106 return 0;
107 }
108
board_key_check(void)109 static void board_key_check(void)
110 {
111 #if defined(CONFIG_FASTBOOT) || defined(CONFIG_CMD_STM32PROG)
112 ofnode node;
113 struct gpio_desc gpio;
114 enum forced_boot_mode boot_mode = BOOT_NORMAL;
115
116 node = ofnode_path("/config");
117 if (!ofnode_valid(node)) {
118 debug("%s: no /config node?\n", __func__);
119 return;
120 }
121 #ifdef CONFIG_FASTBOOT
122 if (gpio_request_by_name_nodev(node, "st,fastboot-gpios", 0,
123 &gpio, GPIOD_IS_IN)) {
124 debug("%s: could not find a /config/st,fastboot-gpios\n",
125 __func__);
126 } else {
127 if (dm_gpio_get_value(&gpio)) {
128 puts("Fastboot key pressed, ");
129 boot_mode = BOOT_FASTBOOT;
130 }
131
132 dm_gpio_free(NULL, &gpio);
133 }
134 #endif
135 #ifdef CONFIG_CMD_STM32PROG
136 if (gpio_request_by_name_nodev(node, "st,stm32prog-gpios", 0,
137 &gpio, GPIOD_IS_IN)) {
138 debug("%s: could not find a /config/st,stm32prog-gpios\n",
139 __func__);
140 } else {
141 if (dm_gpio_get_value(&gpio)) {
142 puts("STM32Programmer key pressed, ");
143 boot_mode = BOOT_STM32PROG;
144 }
145 dm_gpio_free(NULL, &gpio);
146 }
147 #endif
148
149 if (boot_mode != BOOT_NORMAL) {
150 puts("entering download mode...\n");
151 clrsetbits_le32(TAMP_BOOT_CONTEXT,
152 TAMP_BOOT_FORCED_MASK,
153 boot_mode);
154 }
155 #endif
156 }
157
158 #if defined(CONFIG_USB_GADGET) && defined(CONFIG_USB_GADGET_DWC2_OTG)
159
160 /* STMicroelectronics STUSB1600 Type-C controller */
161 #define STUSB1600_CC_CONNECTION_STATUS 0x0E
162
163 /* STUSB1600_CC_CONNECTION_STATUS bitfields */
164 #define STUSB1600_CC_ATTACH BIT(0)
165
stusb1600_init(struct udevice ** dev_stusb1600)166 static int stusb1600_init(struct udevice **dev_stusb1600)
167 {
168 ofnode node;
169 struct udevice *dev, *bus;
170 int ret;
171 u32 chip_addr;
172
173 *dev_stusb1600 = NULL;
174
175 /* if node stusb1600 is present, means DK1 or DK2 board */
176 node = ofnode_by_compatible(ofnode_null(), "st,stusb1600");
177 if (!ofnode_valid(node))
178 return -ENODEV;
179
180 ret = ofnode_read_u32(node, "reg", &chip_addr);
181 if (ret)
182 return -EINVAL;
183
184 ret = uclass_get_device_by_ofnode(UCLASS_I2C, ofnode_get_parent(node),
185 &bus);
186 if (ret) {
187 printf("bus for stusb1600 not found\n");
188 return -ENODEV;
189 }
190
191 ret = dm_i2c_probe(bus, chip_addr, 0, &dev);
192 if (!ret)
193 *dev_stusb1600 = dev;
194
195 return ret;
196 }
197
stusb1600_cable_connected(struct udevice * dev)198 static int stusb1600_cable_connected(struct udevice *dev)
199 {
200 u8 status;
201
202 if (dm_i2c_read(dev, STUSB1600_CC_CONNECTION_STATUS, &status, 1))
203 return 0;
204
205 return status & STUSB1600_CC_ATTACH;
206 }
207
208 #include <usb/dwc2_udc.h>
g_dnl_board_usb_cable_connected(void)209 int g_dnl_board_usb_cable_connected(void)
210 {
211 struct udevice *stusb1600;
212 struct udevice *dwc2_udc_otg;
213 int ret;
214
215 if (!stusb1600_init(&stusb1600))
216 return stusb1600_cable_connected(stusb1600);
217
218 ret = uclass_get_device_by_driver(UCLASS_USB_GADGET_GENERIC,
219 DM_GET_DRIVER(dwc2_udc_otg),
220 &dwc2_udc_otg);
221 if (!ret)
222 debug("dwc2_udc_otg init failed\n");
223
224 return dwc2_udc_B_session_valid(dwc2_udc_otg);
225 }
226 #endif /* CONFIG_USB_GADGET */
227
get_led(struct udevice ** dev,char * led_string)228 static int get_led(struct udevice **dev, char *led_string)
229 {
230 char *led_name;
231 int ret;
232
233 led_name = fdtdec_get_config_string(gd->fdt_blob, led_string);
234 if (!led_name) {
235 pr_debug("%s: could not find %s config string\n",
236 __func__, led_string);
237 return -ENOENT;
238 }
239 ret = led_get_by_label(led_name, dev);
240 if (ret) {
241 debug("%s: get=%d\n", __func__, ret);
242 return ret;
243 }
244
245 return 0;
246 }
247
setup_led(enum led_state_t cmd)248 static int setup_led(enum led_state_t cmd)
249 {
250 struct udevice *dev;
251 int ret;
252
253 ret = get_led(&dev, "u-boot,boot-led");
254 if (ret)
255 return ret;
256
257 ret = led_set_state(dev, cmd);
258 return ret;
259 }
260
board_check_usb_power(void)261 static int board_check_usb_power(void)
262 {
263 struct ofnode_phandle_args adc_args;
264 struct udevice *adc;
265 struct udevice *led;
266 ofnode node;
267 unsigned int raw;
268 int max_uV = 0;
269 int ret, uV, adc_count;
270 u8 i, nb_blink;
271
272 node = ofnode_path("/config");
273 if (!ofnode_valid(node)) {
274 debug("%s: no /config node?\n", __func__);
275 return -ENOENT;
276 }
277
278 /*
279 * Retrieve the ADC channels devices and get measurement
280 * for each of them
281 */
282 adc_count = ofnode_count_phandle_with_args(node, "st,adc_usb_pd",
283 "#io-channel-cells");
284 if (adc_count < 0) {
285 if (adc_count == -ENOENT)
286 return 0;
287
288 pr_err("%s: can't find adc channel (%d)\n", __func__,
289 adc_count);
290
291 return adc_count;
292 }
293
294 for (i = 0; i < adc_count; i++) {
295 if (ofnode_parse_phandle_with_args(node, "st,adc_usb_pd",
296 "#io-channel-cells", 0, i,
297 &adc_args)) {
298 pr_debug("%s: can't find /config/st,adc_usb_pd\n",
299 __func__);
300 return 0;
301 }
302
303 ret = uclass_get_device_by_ofnode(UCLASS_ADC, adc_args.node,
304 &adc);
305
306 if (ret) {
307 pr_err("%s: Can't get adc device(%d)\n", __func__,
308 ret);
309 return ret;
310 }
311
312 ret = adc_channel_single_shot(adc->name, adc_args.args[0],
313 &raw);
314 if (ret) {
315 pr_err("%s: single shot failed for %s[%d]!\n",
316 __func__, adc->name, adc_args.args[0]);
317 return ret;
318 }
319 /* Convert to uV */
320 if (!adc_raw_to_uV(adc, raw, &uV)) {
321 if (uV > max_uV)
322 max_uV = uV;
323 pr_debug("%s: %s[%02d] = %u, %d uV\n", __func__,
324 adc->name, adc_args.args[0], raw, uV);
325 } else {
326 pr_err("%s: Can't get uV value for %s[%d]\n",
327 __func__, adc->name, adc_args.args[0]);
328 }
329 }
330
331 /*
332 * If highest value is inside 1.23 Volts and 2.10 Volts, that means
333 * board is plugged on an USB-C 3A power supply and boot process can
334 * continue.
335 */
336 if (max_uV > USB_START_LOW_THRESHOLD_UV &&
337 max_uV < USB_START_HIGH_THRESHOLD_UV)
338 return 0;
339
340 /* Display warning message and make u-boot,error-led blinking */
341 pr_err("\n*******************************************\n");
342
343 if (max_uV < USB_WARNING_LOW_THRESHOLD_UV) {
344 pr_err("* WARNING 500mA power supply detected *\n");
345 nb_blink = 2;
346 } else {
347 pr_err("* WARNING 1.5A power supply detected *\n");
348 nb_blink = 3;
349 }
350
351 pr_err("* Current too low, use a 3A power supply! *\n");
352 pr_err("*******************************************\n\n");
353
354 ret = get_led(&led, "u-boot,error-led");
355 if (ret)
356 return ret;
357
358 for (i = 0; i < nb_blink * 2; i++) {
359 led_set_state(led, LEDST_TOGGLE);
360 mdelay(125);
361 }
362 led_set_state(led, LEDST_ON);
363
364 return 0;
365 }
366
sysconf_init(void)367 static void sysconf_init(void)
368 {
369 #ifndef CONFIG_STM32MP1_TRUSTED
370 u8 *syscfg;
371 #ifdef CONFIG_DM_REGULATOR
372 struct udevice *pwr_dev;
373 struct udevice *pwr_reg;
374 struct udevice *dev;
375 int ret;
376 u32 otp = 0;
377 #endif
378 u32 bootr;
379
380 syscfg = (u8 *)syscon_get_first_range(STM32MP_SYSCON_SYSCFG);
381
382 /* interconnect update : select master using the port 1 */
383 /* LTDC = AXI_M9 */
384 /* GPU = AXI_M8 */
385 /* today information is hardcoded in U-Boot */
386 writel(BIT(9), syscfg + SYSCFG_ICNR);
387
388 /* disable Pull-Down for boot pin connected to VDD */
389 bootr = readl(syscfg + SYSCFG_BOOTR);
390 bootr &= ~(SYSCFG_BOOTR_BOOT_MASK << SYSCFG_BOOTR_BOOTPD_SHIFT);
391 bootr |= (bootr & SYSCFG_BOOTR_BOOT_MASK) << SYSCFG_BOOTR_BOOTPD_SHIFT;
392 writel(bootr, syscfg + SYSCFG_BOOTR);
393
394 #ifdef CONFIG_DM_REGULATOR
395 /* High Speed Low Voltage Pad mode Enable for SPI, SDMMC, ETH, QSPI
396 * and TRACE. Needed above ~50MHz and conditioned by AFMUX selection.
397 * The customer will have to disable this for low frequencies
398 * or if AFMUX is selected but the function not used, typically for
399 * TRACE. Otherwise, impact on power consumption.
400 *
401 * WARNING:
402 * enabling High Speed mode while VDD>2.7V
403 * with the OTP product_below_2v5 (OTP 18, BIT 13)
404 * erroneously set to 1 can damage the IC!
405 * => U-Boot set the register only if VDD < 2.7V (in DT)
406 * but this value need to be consistent with board design
407 */
408 ret = syscon_get_by_driver_data(STM32MP_SYSCON_PWR, &pwr_dev);
409 if (!ret) {
410 ret = uclass_get_device_by_driver(UCLASS_MISC,
411 DM_GET_DRIVER(stm32mp_bsec),
412 &dev);
413 if (ret) {
414 pr_err("Can't find stm32mp_bsec driver\n");
415 return;
416 }
417
418 ret = misc_read(dev, STM32_BSEC_SHADOW(18), &otp, 4);
419 if (!ret)
420 otp = otp & BIT(13);
421
422 /* get VDD = pwr-supply */
423 ret = device_get_supply_regulator(pwr_dev, "pwr-supply",
424 &pwr_reg);
425
426 /* check if VDD is Low Voltage */
427 if (!ret) {
428 if (regulator_get_value(pwr_reg) < 2700000) {
429 writel(SYSCFG_IOCTRLSETR_HSLVEN_TRACE |
430 SYSCFG_IOCTRLSETR_HSLVEN_QUADSPI |
431 SYSCFG_IOCTRLSETR_HSLVEN_ETH |
432 SYSCFG_IOCTRLSETR_HSLVEN_SDMMC |
433 SYSCFG_IOCTRLSETR_HSLVEN_SPI,
434 syscfg + SYSCFG_IOCTRLSETR);
435
436 if (!otp)
437 pr_err("product_below_2v5=0: HSLVEN protected by HW\n");
438 } else {
439 if (otp)
440 pr_err("product_below_2v5=1: HSLVEN update is destructive, no update as VDD>2.7V\n");
441 }
442 } else {
443 debug("VDD unknown");
444 }
445 }
446 #endif
447
448 /* activate automatic I/O compensation
449 * warning: need to ensure CSI enabled and ready in clock driver
450 */
451 writel(SYSCFG_CMPENSETR_MPU_EN, syscfg + SYSCFG_CMPENSETR);
452
453 while (!(readl(syscfg + SYSCFG_CMPCR) & SYSCFG_CMPCR_READY))
454 ;
455 clrbits_le32(syscfg + SYSCFG_CMPCR, SYSCFG_CMPCR_SW_CTRL);
456 #endif
457 }
458
459 /* board dependent setup after realloc */
board_init(void)460 int board_init(void)
461 {
462 struct udevice *dev;
463
464 /* address of boot parameters */
465 gd->bd->bi_boot_params = STM32_DDR_BASE + 0x100;
466
467 /* probe all PINCTRL for hog */
468 for (uclass_first_device(UCLASS_PINCTRL, &dev);
469 dev;
470 uclass_next_device(&dev)) {
471 pr_debug("probe pincontrol = %s\n", dev->name);
472 }
473
474 board_key_check();
475
476 sysconf_init();
477
478 if (IS_ENABLED(CONFIG_LED))
479 led_default_state();
480
481 return 0;
482 }
483
board_late_init(void)484 int board_late_init(void)
485 {
486 #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
487 const void *fdt_compat;
488 int fdt_compat_len;
489
490 fdt_compat = fdt_getprop(gd->fdt_blob, 0, "compatible",
491 &fdt_compat_len);
492 if (fdt_compat && fdt_compat_len) {
493 if (strncmp(fdt_compat, "st,", 3) != 0)
494 env_set("board_name", fdt_compat);
495 else
496 env_set("board_name", fdt_compat + 3);
497 }
498 #endif
499
500 /* for DK1/DK2 boards */
501 board_check_usb_power();
502
503 return 0;
504 }
505
board_quiesce_devices(void)506 void board_quiesce_devices(void)
507 {
508 setup_led(LEDST_OFF);
509 }
510
511 /* eth init function : weak called in eqos driver */
board_interface_eth_init(struct udevice * dev,phy_interface_t interface_type)512 int board_interface_eth_init(struct udevice *dev,
513 phy_interface_t interface_type)
514 {
515 u8 *syscfg;
516 u32 value;
517 bool eth_clk_sel_reg = false;
518 bool eth_ref_clk_sel_reg = false;
519
520 /* Gigabit Ethernet 125MHz clock selection. */
521 eth_clk_sel_reg = dev_read_bool(dev, "st,eth_clk_sel");
522
523 /* Ethernet 50Mhz RMII clock selection */
524 eth_ref_clk_sel_reg =
525 dev_read_bool(dev, "st,eth_ref_clk_sel");
526
527 syscfg = (u8 *)syscon_get_first_range(STM32MP_SYSCON_SYSCFG);
528
529 if (!syscfg)
530 return -ENODEV;
531
532 switch (interface_type) {
533 case PHY_INTERFACE_MODE_MII:
534 value = SYSCFG_PMCSETR_ETH_SEL_GMII_MII |
535 SYSCFG_PMCSETR_ETH_REF_CLK_SEL;
536 debug("%s: PHY_INTERFACE_MODE_MII\n", __func__);
537 break;
538 case PHY_INTERFACE_MODE_GMII:
539 if (eth_clk_sel_reg)
540 value = SYSCFG_PMCSETR_ETH_SEL_GMII_MII |
541 SYSCFG_PMCSETR_ETH_CLK_SEL;
542 else
543 value = SYSCFG_PMCSETR_ETH_SEL_GMII_MII;
544 debug("%s: PHY_INTERFACE_MODE_GMII\n", __func__);
545 break;
546 case PHY_INTERFACE_MODE_RMII:
547 if (eth_ref_clk_sel_reg)
548 value = SYSCFG_PMCSETR_ETH_SEL_RMII |
549 SYSCFG_PMCSETR_ETH_REF_CLK_SEL;
550 else
551 value = SYSCFG_PMCSETR_ETH_SEL_RMII;
552 debug("%s: PHY_INTERFACE_MODE_RMII\n", __func__);
553 break;
554 case PHY_INTERFACE_MODE_RGMII:
555 case PHY_INTERFACE_MODE_RGMII_ID:
556 case PHY_INTERFACE_MODE_RGMII_RXID:
557 case PHY_INTERFACE_MODE_RGMII_TXID:
558 if (eth_clk_sel_reg)
559 value = SYSCFG_PMCSETR_ETH_SEL_RGMII |
560 SYSCFG_PMCSETR_ETH_CLK_SEL;
561 else
562 value = SYSCFG_PMCSETR_ETH_SEL_RGMII;
563 debug("%s: PHY_INTERFACE_MODE_RGMII\n", __func__);
564 break;
565 default:
566 debug("%s: Do not manage %d interface\n",
567 __func__, interface_type);
568 /* Do not manage others interfaces */
569 return -EINVAL;
570 }
571
572 /* clear and set ETH configuration bits */
573 writel(SYSCFG_PMCSETR_ETH_SEL_MASK | SYSCFG_PMCSETR_ETH_SELMII |
574 SYSCFG_PMCSETR_ETH_REF_CLK_SEL | SYSCFG_PMCSETR_ETH_CLK_SEL,
575 syscfg + SYSCFG_PMCCLRR);
576 writel(value, syscfg + SYSCFG_PMCSETR);
577
578 return 0;
579 }
580