1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * Copyright (C) 2010 Samsung Electronics
3*4882a593Smuzhiyun * Minkyu Kang <mk7.kang@samsung.com>
4*4882a593Smuzhiyun * Kyungmin Park <kyungmin.park@samsung.com>
5*4882a593Smuzhiyun *
6*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+
7*4882a593Smuzhiyun */
8*4882a593Smuzhiyun
9*4882a593Smuzhiyun #include <common.h>
10*4882a593Smuzhiyun #include <spi.h>
11*4882a593Smuzhiyun #include <lcd.h>
12*4882a593Smuzhiyun #include <asm/io.h>
13*4882a593Smuzhiyun #include <asm/gpio.h>
14*4882a593Smuzhiyun #include <asm/arch/adc.h>
15*4882a593Smuzhiyun #include <asm/arch/pinmux.h>
16*4882a593Smuzhiyun #include <asm/arch/watchdog.h>
17*4882a593Smuzhiyun #include <ld9040.h>
18*4882a593Smuzhiyun #include <power/pmic.h>
19*4882a593Smuzhiyun #include <usb.h>
20*4882a593Smuzhiyun #include <usb/dwc2_udc.h>
21*4882a593Smuzhiyun #include <asm/arch/cpu.h>
22*4882a593Smuzhiyun #include <power/max8998_pmic.h>
23*4882a593Smuzhiyun #include <libtizen.h>
24*4882a593Smuzhiyun #include <samsung/misc.h>
25*4882a593Smuzhiyun #include <usb_mass_storage.h>
26*4882a593Smuzhiyun #include <asm/mach-types.h>
27*4882a593Smuzhiyun
28*4882a593Smuzhiyun DECLARE_GLOBAL_DATA_PTR;
29*4882a593Smuzhiyun
30*4882a593Smuzhiyun unsigned int board_rev;
31*4882a593Smuzhiyun static int init_pmic_lcd(void);
32*4882a593Smuzhiyun
get_board_rev(void)33*4882a593Smuzhiyun u32 get_board_rev(void)
34*4882a593Smuzhiyun {
35*4882a593Smuzhiyun return board_rev;
36*4882a593Smuzhiyun }
37*4882a593Smuzhiyun
exynos_power_init(void)38*4882a593Smuzhiyun int exynos_power_init(void)
39*4882a593Smuzhiyun {
40*4882a593Smuzhiyun return init_pmic_lcd();
41*4882a593Smuzhiyun }
42*4882a593Smuzhiyun
get_hwrev(void)43*4882a593Smuzhiyun static int get_hwrev(void)
44*4882a593Smuzhiyun {
45*4882a593Smuzhiyun return board_rev & 0xFF;
46*4882a593Smuzhiyun }
47*4882a593Smuzhiyun
get_adc_value(int channel)48*4882a593Smuzhiyun static unsigned short get_adc_value(int channel)
49*4882a593Smuzhiyun {
50*4882a593Smuzhiyun struct s5p_adc *adc = (struct s5p_adc *)samsung_get_base_adc();
51*4882a593Smuzhiyun unsigned short ret = 0;
52*4882a593Smuzhiyun unsigned int reg;
53*4882a593Smuzhiyun unsigned int loop = 0;
54*4882a593Smuzhiyun
55*4882a593Smuzhiyun writel(channel & 0xF, &adc->adcmux);
56*4882a593Smuzhiyun writel((1 << 14) | (49 << 6), &adc->adccon);
57*4882a593Smuzhiyun writel(1000 & 0xffff, &adc->adcdly);
58*4882a593Smuzhiyun writel(readl(&adc->adccon) | (1 << 16), &adc->adccon); /* 12 bit */
59*4882a593Smuzhiyun udelay(10);
60*4882a593Smuzhiyun writel(readl(&adc->adccon) | (1 << 0), &adc->adccon); /* Enable */
61*4882a593Smuzhiyun udelay(10);
62*4882a593Smuzhiyun
63*4882a593Smuzhiyun do {
64*4882a593Smuzhiyun udelay(1);
65*4882a593Smuzhiyun reg = readl(&adc->adccon);
66*4882a593Smuzhiyun } while (!(reg & (1 << 15)) && (loop++ < 1000));
67*4882a593Smuzhiyun
68*4882a593Smuzhiyun ret = readl(&adc->adcdat0) & 0xFFF;
69*4882a593Smuzhiyun
70*4882a593Smuzhiyun return ret;
71*4882a593Smuzhiyun }
72*4882a593Smuzhiyun
adc_power_control(int on)73*4882a593Smuzhiyun static int adc_power_control(int on)
74*4882a593Smuzhiyun {
75*4882a593Smuzhiyun struct udevice *dev;
76*4882a593Smuzhiyun int ret;
77*4882a593Smuzhiyun u8 reg;
78*4882a593Smuzhiyun
79*4882a593Smuzhiyun ret = pmic_get("max8998-pmic", &dev);
80*4882a593Smuzhiyun if (ret) {
81*4882a593Smuzhiyun puts("Failed to get MAX8998!\n");
82*4882a593Smuzhiyun return ret;
83*4882a593Smuzhiyun }
84*4882a593Smuzhiyun
85*4882a593Smuzhiyun reg = pmic_reg_read(dev, MAX8998_REG_ONOFF1);
86*4882a593Smuzhiyun if (on)
87*4882a593Smuzhiyun reg |= MAX8998_LDO4;
88*4882a593Smuzhiyun else
89*4882a593Smuzhiyun reg &= ~MAX8998_LDO4;
90*4882a593Smuzhiyun
91*4882a593Smuzhiyun ret = pmic_reg_write(dev, MAX8998_REG_ONOFF1, reg);
92*4882a593Smuzhiyun if (ret) {
93*4882a593Smuzhiyun puts("MAX8998 LDO setting error\n");
94*4882a593Smuzhiyun return -EINVAL;
95*4882a593Smuzhiyun }
96*4882a593Smuzhiyun
97*4882a593Smuzhiyun return 0;
98*4882a593Smuzhiyun }
99*4882a593Smuzhiyun
get_hw_revision(void)100*4882a593Smuzhiyun static unsigned int get_hw_revision(void)
101*4882a593Smuzhiyun {
102*4882a593Smuzhiyun int hwrev, mode0, mode1;
103*4882a593Smuzhiyun
104*4882a593Smuzhiyun adc_power_control(1);
105*4882a593Smuzhiyun
106*4882a593Smuzhiyun mode0 = get_adc_value(1); /* HWREV_MODE0 */
107*4882a593Smuzhiyun mode1 = get_adc_value(2); /* HWREV_MODE1 */
108*4882a593Smuzhiyun
109*4882a593Smuzhiyun /*
110*4882a593Smuzhiyun * XXX Always set the default hwrev as the latest board
111*4882a593Smuzhiyun * ADC = (voltage) / 3.3 * 4096
112*4882a593Smuzhiyun */
113*4882a593Smuzhiyun hwrev = 3;
114*4882a593Smuzhiyun
115*4882a593Smuzhiyun #define IS_RANGE(x, min, max) ((x) > (min) && (x) < (max))
116*4882a593Smuzhiyun if (IS_RANGE(mode0, 80, 200) && IS_RANGE(mode1, 80, 200))
117*4882a593Smuzhiyun hwrev = 0x0; /* 0.01V 0.01V */
118*4882a593Smuzhiyun if (IS_RANGE(mode0, 750, 1000) && IS_RANGE(mode1, 80, 200))
119*4882a593Smuzhiyun hwrev = 0x1; /* 610mV 0.01V */
120*4882a593Smuzhiyun if (IS_RANGE(mode0, 1300, 1700) && IS_RANGE(mode1, 80, 200))
121*4882a593Smuzhiyun hwrev = 0x2; /* 1.16V 0.01V */
122*4882a593Smuzhiyun if (IS_RANGE(mode0, 2000, 2400) && IS_RANGE(mode1, 80, 200))
123*4882a593Smuzhiyun hwrev = 0x3; /* 1.79V 0.01V */
124*4882a593Smuzhiyun #undef IS_RANGE
125*4882a593Smuzhiyun
126*4882a593Smuzhiyun debug("mode0: %d, mode1: %d, hwrev 0x%x\n", mode0, mode1, hwrev);
127*4882a593Smuzhiyun
128*4882a593Smuzhiyun adc_power_control(0);
129*4882a593Smuzhiyun
130*4882a593Smuzhiyun return hwrev;
131*4882a593Smuzhiyun }
132*4882a593Smuzhiyun
check_hw_revision(void)133*4882a593Smuzhiyun static void check_hw_revision(void)
134*4882a593Smuzhiyun {
135*4882a593Smuzhiyun int hwrev;
136*4882a593Smuzhiyun
137*4882a593Smuzhiyun hwrev = get_hw_revision();
138*4882a593Smuzhiyun
139*4882a593Smuzhiyun board_rev |= hwrev;
140*4882a593Smuzhiyun }
141*4882a593Smuzhiyun
142*4882a593Smuzhiyun #ifdef CONFIG_USB_GADGET
s5pc210_phy_control(int on)143*4882a593Smuzhiyun static int s5pc210_phy_control(int on)
144*4882a593Smuzhiyun {
145*4882a593Smuzhiyun struct udevice *dev;
146*4882a593Smuzhiyun int ret;
147*4882a593Smuzhiyun u8 reg;
148*4882a593Smuzhiyun
149*4882a593Smuzhiyun ret = pmic_get("max8998-pmic", &dev);
150*4882a593Smuzhiyun if (ret) {
151*4882a593Smuzhiyun puts("Failed to get MAX8998!\n");
152*4882a593Smuzhiyun return ret;
153*4882a593Smuzhiyun }
154*4882a593Smuzhiyun
155*4882a593Smuzhiyun if (on) {
156*4882a593Smuzhiyun reg = pmic_reg_read(dev, MAX8998_REG_BUCK_ACTIVE_DISCHARGE3);
157*4882a593Smuzhiyun reg |= MAX8998_SAFEOUT1;
158*4882a593Smuzhiyun ret |= pmic_reg_write(dev,
159*4882a593Smuzhiyun MAX8998_REG_BUCK_ACTIVE_DISCHARGE3, reg);
160*4882a593Smuzhiyun
161*4882a593Smuzhiyun reg = pmic_reg_read(dev, MAX8998_REG_ONOFF1);
162*4882a593Smuzhiyun reg |= MAX8998_LDO3;
163*4882a593Smuzhiyun ret |= pmic_reg_write(dev, MAX8998_REG_ONOFF1, reg);
164*4882a593Smuzhiyun
165*4882a593Smuzhiyun reg = pmic_reg_read(dev, MAX8998_REG_ONOFF2);
166*4882a593Smuzhiyun reg |= MAX8998_LDO8;
167*4882a593Smuzhiyun ret |= pmic_reg_write(dev, MAX8998_REG_ONOFF2, reg);
168*4882a593Smuzhiyun
169*4882a593Smuzhiyun } else {
170*4882a593Smuzhiyun reg = pmic_reg_read(dev, MAX8998_REG_ONOFF2);
171*4882a593Smuzhiyun reg &= ~MAX8998_LDO8;
172*4882a593Smuzhiyun ret |= pmic_reg_write(dev, MAX8998_REG_ONOFF2, reg);
173*4882a593Smuzhiyun
174*4882a593Smuzhiyun reg = pmic_reg_read(dev, MAX8998_REG_ONOFF1);
175*4882a593Smuzhiyun reg &= ~MAX8998_LDO3;
176*4882a593Smuzhiyun ret |= pmic_reg_write(dev, MAX8998_REG_ONOFF1, reg);
177*4882a593Smuzhiyun
178*4882a593Smuzhiyun reg = pmic_reg_read(dev, MAX8998_REG_BUCK_ACTIVE_DISCHARGE3);
179*4882a593Smuzhiyun reg &= ~MAX8998_SAFEOUT1;
180*4882a593Smuzhiyun ret |= pmic_reg_write(dev,
181*4882a593Smuzhiyun MAX8998_REG_BUCK_ACTIVE_DISCHARGE3, reg);
182*4882a593Smuzhiyun }
183*4882a593Smuzhiyun
184*4882a593Smuzhiyun if (ret) {
185*4882a593Smuzhiyun puts("MAX8998 LDO setting error!\n");
186*4882a593Smuzhiyun return -EINVAL;
187*4882a593Smuzhiyun }
188*4882a593Smuzhiyun
189*4882a593Smuzhiyun return 0;
190*4882a593Smuzhiyun }
191*4882a593Smuzhiyun
192*4882a593Smuzhiyun struct dwc2_plat_otg_data s5pc210_otg_data = {
193*4882a593Smuzhiyun .phy_control = s5pc210_phy_control,
194*4882a593Smuzhiyun .regs_phy = EXYNOS4_USBPHY_BASE,
195*4882a593Smuzhiyun .regs_otg = EXYNOS4_USBOTG_BASE,
196*4882a593Smuzhiyun .usb_phy_ctrl = EXYNOS4_USBPHY_CONTROL,
197*4882a593Smuzhiyun .usb_flags = PHY0_SLEEP,
198*4882a593Smuzhiyun };
199*4882a593Smuzhiyun #endif
200*4882a593Smuzhiyun
board_usb_init(int index,enum usb_init_type init)201*4882a593Smuzhiyun int board_usb_init(int index, enum usb_init_type init)
202*4882a593Smuzhiyun {
203*4882a593Smuzhiyun debug("USB_udc_probe\n");
204*4882a593Smuzhiyun return dwc2_udc_probe(&s5pc210_otg_data);
205*4882a593Smuzhiyun }
206*4882a593Smuzhiyun
exynos_early_init_f(void)207*4882a593Smuzhiyun int exynos_early_init_f(void)
208*4882a593Smuzhiyun {
209*4882a593Smuzhiyun wdt_stop();
210*4882a593Smuzhiyun
211*4882a593Smuzhiyun return 0;
212*4882a593Smuzhiyun }
213*4882a593Smuzhiyun
init_pmic_lcd(void)214*4882a593Smuzhiyun static int init_pmic_lcd(void)
215*4882a593Smuzhiyun {
216*4882a593Smuzhiyun struct udevice *dev;
217*4882a593Smuzhiyun unsigned char val;
218*4882a593Smuzhiyun int ret = 0;
219*4882a593Smuzhiyun
220*4882a593Smuzhiyun ret = pmic_get("max8998-pmic", &dev);
221*4882a593Smuzhiyun if (ret) {
222*4882a593Smuzhiyun puts("Failed to get MAX8998 for init_pmic_lcd()!\n");
223*4882a593Smuzhiyun return ret;
224*4882a593Smuzhiyun }
225*4882a593Smuzhiyun
226*4882a593Smuzhiyun /* LDO7 1.8V */
227*4882a593Smuzhiyun val = 0x02; /* (1800 - 1600) / 100; */
228*4882a593Smuzhiyun ret |= pmic_reg_write(dev, MAX8998_REG_LDO7, val);
229*4882a593Smuzhiyun
230*4882a593Smuzhiyun /* LDO17 3.0V */
231*4882a593Smuzhiyun val = 0xe; /* (3000 - 1600) / 100; */
232*4882a593Smuzhiyun ret |= pmic_reg_write(dev, MAX8998_REG_LDO17, val);
233*4882a593Smuzhiyun
234*4882a593Smuzhiyun /* Disable unneeded regulators */
235*4882a593Smuzhiyun /*
236*4882a593Smuzhiyun * ONOFF1
237*4882a593Smuzhiyun * Buck1 ON, Buck2 OFF, Buck3 ON, Buck4 ON
238*4882a593Smuzhiyun * LDO2 ON, LDO3 OFF, LDO4 OFF, LDO5 ON
239*4882a593Smuzhiyun */
240*4882a593Smuzhiyun val = 0xB9;
241*4882a593Smuzhiyun ret |= pmic_reg_write(dev, MAX8998_REG_ONOFF1, val);
242*4882a593Smuzhiyun
243*4882a593Smuzhiyun /* ONOFF2
244*4882a593Smuzhiyun * LDO6 OFF, LDO7 ON, LDO8 OFF, LDO9 ON,
245*4882a593Smuzhiyun * LDO10 OFF, LDO11 OFF, LDO12 OFF, LDO13 OFF
246*4882a593Smuzhiyun */
247*4882a593Smuzhiyun val = 0x50;
248*4882a593Smuzhiyun ret |= pmic_reg_write(dev, MAX8998_REG_ONOFF2, val);
249*4882a593Smuzhiyun
250*4882a593Smuzhiyun /* ONOFF3
251*4882a593Smuzhiyun * LDO14 OFF, LDO15 OFF, LGO16 OFF, LDO17 OFF
252*4882a593Smuzhiyun * EPWRHOLD OFF, EBATTMON OFF, ELBCNFG2 OFF, ELBCNFG1 OFF
253*4882a593Smuzhiyun */
254*4882a593Smuzhiyun val = 0x00;
255*4882a593Smuzhiyun ret |= pmic_reg_write(dev, MAX8998_REG_ONOFF3, val);
256*4882a593Smuzhiyun
257*4882a593Smuzhiyun if (ret) {
258*4882a593Smuzhiyun puts("LCD pmic initialisation error!\n");
259*4882a593Smuzhiyun return -EINVAL;
260*4882a593Smuzhiyun }
261*4882a593Smuzhiyun
262*4882a593Smuzhiyun return 0;
263*4882a593Smuzhiyun }
264*4882a593Smuzhiyun
exynos_cfg_lcd_gpio(void)265*4882a593Smuzhiyun void exynos_cfg_lcd_gpio(void)
266*4882a593Smuzhiyun {
267*4882a593Smuzhiyun unsigned int i, f3_end = 4;
268*4882a593Smuzhiyun
269*4882a593Smuzhiyun for (i = 0; i < 8; i++) {
270*4882a593Smuzhiyun /* set GPF0,1,2[0:7] for RGB Interface and Data lines (32bit) */
271*4882a593Smuzhiyun gpio_cfg_pin(EXYNOS4_GPIO_F00 + i, S5P_GPIO_FUNC(2));
272*4882a593Smuzhiyun gpio_cfg_pin(EXYNOS4_GPIO_F10 + i, S5P_GPIO_FUNC(2));
273*4882a593Smuzhiyun gpio_cfg_pin(EXYNOS4_GPIO_F20 + i, S5P_GPIO_FUNC(2));
274*4882a593Smuzhiyun /* pull-up/down disable */
275*4882a593Smuzhiyun gpio_set_pull(EXYNOS4_GPIO_F00 + i, S5P_GPIO_PULL_NONE);
276*4882a593Smuzhiyun gpio_set_pull(EXYNOS4_GPIO_F10 + i, S5P_GPIO_PULL_NONE);
277*4882a593Smuzhiyun gpio_set_pull(EXYNOS4_GPIO_F20 + i, S5P_GPIO_PULL_NONE);
278*4882a593Smuzhiyun
279*4882a593Smuzhiyun /* drive strength to max (24bit) */
280*4882a593Smuzhiyun gpio_set_drv(EXYNOS4_GPIO_F00 + i, S5P_GPIO_DRV_4X);
281*4882a593Smuzhiyun gpio_set_rate(EXYNOS4_GPIO_F00 + i, S5P_GPIO_DRV_SLOW);
282*4882a593Smuzhiyun gpio_set_drv(EXYNOS4_GPIO_F10 + i, S5P_GPIO_DRV_4X);
283*4882a593Smuzhiyun gpio_set_rate(EXYNOS4_GPIO_F10 + i, S5P_GPIO_DRV_SLOW);
284*4882a593Smuzhiyun gpio_set_drv(EXYNOS4_GPIO_F20 + i, S5P_GPIO_DRV_4X);
285*4882a593Smuzhiyun gpio_set_rate(EXYNOS4_GPIO_F00 + i, S5P_GPIO_DRV_SLOW);
286*4882a593Smuzhiyun }
287*4882a593Smuzhiyun
288*4882a593Smuzhiyun for (i = EXYNOS4_GPIO_F30; i < (EXYNOS4_GPIO_F30 + f3_end); i++) {
289*4882a593Smuzhiyun /* set GPF3[0:3] for RGB Interface and Data lines (32bit) */
290*4882a593Smuzhiyun gpio_cfg_pin(i, S5P_GPIO_FUNC(2));
291*4882a593Smuzhiyun /* pull-up/down disable */
292*4882a593Smuzhiyun gpio_set_pull(i, S5P_GPIO_PULL_NONE);
293*4882a593Smuzhiyun /* drive strength to max (24bit) */
294*4882a593Smuzhiyun gpio_set_drv(i, S5P_GPIO_DRV_4X);
295*4882a593Smuzhiyun gpio_set_rate(i, S5P_GPIO_DRV_SLOW);
296*4882a593Smuzhiyun }
297*4882a593Smuzhiyun
298*4882a593Smuzhiyun /* gpio pad configuration for LCD reset. */
299*4882a593Smuzhiyun gpio_request(EXYNOS4_GPIO_Y45, "lcd_reset");
300*4882a593Smuzhiyun gpio_cfg_pin(EXYNOS4_GPIO_Y45, S5P_GPIO_OUTPUT);
301*4882a593Smuzhiyun }
302*4882a593Smuzhiyun
mipi_power(void)303*4882a593Smuzhiyun int mipi_power(void)
304*4882a593Smuzhiyun {
305*4882a593Smuzhiyun return 0;
306*4882a593Smuzhiyun }
307*4882a593Smuzhiyun
exynos_reset_lcd(void)308*4882a593Smuzhiyun void exynos_reset_lcd(void)
309*4882a593Smuzhiyun {
310*4882a593Smuzhiyun gpio_set_value(EXYNOS4_GPIO_Y45, 1);
311*4882a593Smuzhiyun udelay(10000);
312*4882a593Smuzhiyun gpio_set_value(EXYNOS4_GPIO_Y45, 0);
313*4882a593Smuzhiyun udelay(10000);
314*4882a593Smuzhiyun gpio_set_value(EXYNOS4_GPIO_Y45, 1);
315*4882a593Smuzhiyun udelay(100);
316*4882a593Smuzhiyun }
317*4882a593Smuzhiyun
exynos_lcd_power_on(void)318*4882a593Smuzhiyun void exynos_lcd_power_on(void)
319*4882a593Smuzhiyun {
320*4882a593Smuzhiyun struct udevice *dev;
321*4882a593Smuzhiyun int ret;
322*4882a593Smuzhiyun u8 reg;
323*4882a593Smuzhiyun
324*4882a593Smuzhiyun ret = pmic_get("max8998-pmic", &dev);
325*4882a593Smuzhiyun if (ret) {
326*4882a593Smuzhiyun puts("Failed to get MAX8998!\n");
327*4882a593Smuzhiyun return;
328*4882a593Smuzhiyun }
329*4882a593Smuzhiyun
330*4882a593Smuzhiyun reg = pmic_reg_read(dev, MAX8998_REG_ONOFF3);
331*4882a593Smuzhiyun reg |= MAX8998_LDO17;
332*4882a593Smuzhiyun ret = pmic_reg_write(dev, MAX8998_REG_ONOFF3, reg);
333*4882a593Smuzhiyun if (ret) {
334*4882a593Smuzhiyun puts("MAX8998 LDO setting error\n");
335*4882a593Smuzhiyun return;
336*4882a593Smuzhiyun }
337*4882a593Smuzhiyun
338*4882a593Smuzhiyun reg = pmic_reg_read(dev, MAX8998_REG_ONOFF2);
339*4882a593Smuzhiyun reg |= MAX8998_LDO7;
340*4882a593Smuzhiyun ret = pmic_reg_write(dev, MAX8998_REG_ONOFF2, reg);
341*4882a593Smuzhiyun if (ret) {
342*4882a593Smuzhiyun puts("MAX8998 LDO setting error\n");
343*4882a593Smuzhiyun return;
344*4882a593Smuzhiyun }
345*4882a593Smuzhiyun }
346*4882a593Smuzhiyun
exynos_cfg_ldo(void)347*4882a593Smuzhiyun void exynos_cfg_ldo(void)
348*4882a593Smuzhiyun {
349*4882a593Smuzhiyun ld9040_cfg_ldo();
350*4882a593Smuzhiyun }
351*4882a593Smuzhiyun
exynos_enable_ldo(unsigned int onoff)352*4882a593Smuzhiyun void exynos_enable_ldo(unsigned int onoff)
353*4882a593Smuzhiyun {
354*4882a593Smuzhiyun ld9040_enable_ldo(onoff);
355*4882a593Smuzhiyun }
356*4882a593Smuzhiyun
exynos_init(void)357*4882a593Smuzhiyun int exynos_init(void)
358*4882a593Smuzhiyun {
359*4882a593Smuzhiyun gd->bd->bi_arch_number = MACH_TYPE_UNIVERSAL_C210;
360*4882a593Smuzhiyun
361*4882a593Smuzhiyun switch (get_hwrev()) {
362*4882a593Smuzhiyun case 0:
363*4882a593Smuzhiyun /*
364*4882a593Smuzhiyun * Set the low to enable LDO_EN
365*4882a593Smuzhiyun * But when you use the test board for eMMC booting
366*4882a593Smuzhiyun * you should set it HIGH since it removes the inverter
367*4882a593Smuzhiyun */
368*4882a593Smuzhiyun /* MASSMEMORY_EN: XMDMDATA_6: GPE3[6] */
369*4882a593Smuzhiyun gpio_request(EXYNOS4_GPIO_E36, "ldo_en");
370*4882a593Smuzhiyun gpio_direction_output(EXYNOS4_GPIO_E36, 0);
371*4882a593Smuzhiyun break;
372*4882a593Smuzhiyun default:
373*4882a593Smuzhiyun /*
374*4882a593Smuzhiyun * Default reset state is High and there's no inverter
375*4882a593Smuzhiyun * But set it as HIGH to ensure
376*4882a593Smuzhiyun */
377*4882a593Smuzhiyun /* MASSMEMORY_EN: XMDMADDR_3: GPE1[3] */
378*4882a593Smuzhiyun gpio_request(EXYNOS4_GPIO_E13, "massmemory_en");
379*4882a593Smuzhiyun gpio_direction_output(EXYNOS4_GPIO_E13, 1);
380*4882a593Smuzhiyun break;
381*4882a593Smuzhiyun }
382*4882a593Smuzhiyun
383*4882a593Smuzhiyun check_hw_revision();
384*4882a593Smuzhiyun printf("HW Revision:\t0x%x\n", board_rev);
385*4882a593Smuzhiyun
386*4882a593Smuzhiyun return 0;
387*4882a593Smuzhiyun }
388*4882a593Smuzhiyun
389*4882a593Smuzhiyun #ifdef CONFIG_LCD
exynos_lcd_misc_init(vidinfo_t * vid)390*4882a593Smuzhiyun void exynos_lcd_misc_init(vidinfo_t *vid)
391*4882a593Smuzhiyun {
392*4882a593Smuzhiyun #ifdef CONFIG_TIZEN
393*4882a593Smuzhiyun get_tizen_logo_info(vid);
394*4882a593Smuzhiyun #endif
395*4882a593Smuzhiyun
396*4882a593Smuzhiyun /* for LD9040. */
397*4882a593Smuzhiyun vid->pclk_name = 1; /* MPLL */
398*4882a593Smuzhiyun vid->sclk_div = 1;
399*4882a593Smuzhiyun
400*4882a593Smuzhiyun env_set("lcdinfo", "lcd=ld9040");
401*4882a593Smuzhiyun }
402*4882a593Smuzhiyun #endif
403