1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * PPC-AG BG0900 board
3*4882a593Smuzhiyun *
4*4882a593Smuzhiyun * Copyright (C) 2013 Marek Vasut <marex@denx.de>
5*4882a593Smuzhiyun *
6*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+
7*4882a593Smuzhiyun */
8*4882a593Smuzhiyun
9*4882a593Smuzhiyun #include <common.h>
10*4882a593Smuzhiyun #include <asm/gpio.h>
11*4882a593Smuzhiyun #include <asm/io.h>
12*4882a593Smuzhiyun #include <asm/arch/imx-regs.h>
13*4882a593Smuzhiyun #include <asm/arch/iomux-mx28.h>
14*4882a593Smuzhiyun #include <asm/arch/clock.h>
15*4882a593Smuzhiyun #include <asm/arch/sys_proto.h>
16*4882a593Smuzhiyun #include <linux/mii.h>
17*4882a593Smuzhiyun #include <miiphy.h>
18*4882a593Smuzhiyun #include <netdev.h>
19*4882a593Smuzhiyun #include <errno.h>
20*4882a593Smuzhiyun
21*4882a593Smuzhiyun DECLARE_GLOBAL_DATA_PTR;
22*4882a593Smuzhiyun
23*4882a593Smuzhiyun /*
24*4882a593Smuzhiyun * Functions
25*4882a593Smuzhiyun */
board_early_init_f(void)26*4882a593Smuzhiyun int board_early_init_f(void)
27*4882a593Smuzhiyun {
28*4882a593Smuzhiyun /* IO0 clock at 480MHz */
29*4882a593Smuzhiyun mxs_set_ioclk(MXC_IOCLK0, 480000);
30*4882a593Smuzhiyun /* IO1 clock at 480MHz */
31*4882a593Smuzhiyun mxs_set_ioclk(MXC_IOCLK1, 480000);
32*4882a593Smuzhiyun
33*4882a593Smuzhiyun /* SSP2 clock at 160MHz */
34*4882a593Smuzhiyun mxs_set_sspclk(MXC_SSPCLK2, 160000, 0);
35*4882a593Smuzhiyun
36*4882a593Smuzhiyun return 0;
37*4882a593Smuzhiyun }
38*4882a593Smuzhiyun
dram_init(void)39*4882a593Smuzhiyun int dram_init(void)
40*4882a593Smuzhiyun {
41*4882a593Smuzhiyun return mxs_dram_init();
42*4882a593Smuzhiyun }
43*4882a593Smuzhiyun
board_init(void)44*4882a593Smuzhiyun int board_init(void)
45*4882a593Smuzhiyun {
46*4882a593Smuzhiyun /* Adress of boot parameters */
47*4882a593Smuzhiyun gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
48*4882a593Smuzhiyun
49*4882a593Smuzhiyun return 0;
50*4882a593Smuzhiyun }
51*4882a593Smuzhiyun
52*4882a593Smuzhiyun #ifdef CONFIG_CMD_NET
board_eth_init(bd_t * bis)53*4882a593Smuzhiyun int board_eth_init(bd_t *bis)
54*4882a593Smuzhiyun {
55*4882a593Smuzhiyun struct mxs_clkctrl_regs *clkctrl_regs =
56*4882a593Smuzhiyun (struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
57*4882a593Smuzhiyun struct eth_device *dev;
58*4882a593Smuzhiyun int ret;
59*4882a593Smuzhiyun
60*4882a593Smuzhiyun ret = cpu_eth_init(bis);
61*4882a593Smuzhiyun
62*4882a593Smuzhiyun /* BG0900 uses ENET_CLK PAD to drive FEC clock */
63*4882a593Smuzhiyun writel(CLKCTRL_ENET_TIME_SEL_RMII_CLK | CLKCTRL_ENET_CLK_OUT_EN,
64*4882a593Smuzhiyun &clkctrl_regs->hw_clkctrl_enet);
65*4882a593Smuzhiyun
66*4882a593Smuzhiyun /* Reset FEC PHYs */
67*4882a593Smuzhiyun gpio_direction_output(MX28_PAD_ENET0_RX_CLK__GPIO_4_13, 0);
68*4882a593Smuzhiyun udelay(200);
69*4882a593Smuzhiyun gpio_set_value(MX28_PAD_ENET0_RX_CLK__GPIO_4_13, 1);
70*4882a593Smuzhiyun
71*4882a593Smuzhiyun ret = fecmxc_initialize_multi(bis, 0, 0, MXS_ENET0_BASE);
72*4882a593Smuzhiyun if (ret) {
73*4882a593Smuzhiyun puts("FEC MXS: Unable to init FEC0\n");
74*4882a593Smuzhiyun return ret;
75*4882a593Smuzhiyun }
76*4882a593Smuzhiyun
77*4882a593Smuzhiyun dev = eth_get_dev_by_name("FEC0");
78*4882a593Smuzhiyun if (!dev) {
79*4882a593Smuzhiyun puts("FEC MXS: Unable to get FEC0 device entry\n");
80*4882a593Smuzhiyun return -EINVAL;
81*4882a593Smuzhiyun }
82*4882a593Smuzhiyun
83*4882a593Smuzhiyun return ret;
84*4882a593Smuzhiyun }
85*4882a593Smuzhiyun
86*4882a593Smuzhiyun #endif
87